| 1 | /* |
| 2 | * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved |
| 3 | * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 |
| 4 | * |
| 5 | * Written by Nicolin Chen, Shameer Kolothum |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | */ |
| 9 | |
| 10 | #ifndef HW_ARM_TEGRA241_CMDQV_H |
| 11 | #define HW_ARM_TEGRA241_CMDQV_H |
| 12 | |
| 13 | #include "hw/core/registerfields.h" |
| 14 | |
| 15 | #define CMDQV_VER 1 |
| 16 | #define CMDQV_NUM_CMDQ_LOG2 1 |
| 17 | #define CMDQV_NUM_SID_PER_VI_LOG2 4 |
| 18 | |
| 19 | #define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) |
| 20 | #define TEGRA241_CMDQV_MAX_NUM_SID (1U << CMDQV_NUM_SID_PER_VI_LOG2) |
| 21 | |
| 22 | /* |
| 23 | * Tegra241 CMDQV MMIO layout (64KB pages) |
| 24 | * |
| 25 | * 0x00000 (CMDQ-V Config page) |
| 26 | * 0x10000 (CMDQ-V CMDQ Page0) |
| 27 | * 0x20000 (CMDQ-V CMDQ Page1) |
| 28 | * 0x30000 (Virtual Interface Page0) |
| 29 | * 0x40000 (Virtual Interface Page1) |
| 30 | */ |
| 31 | #define TEGRA241_CMDQV_IO_LEN 0x50000 |
| 32 | |
| 33 | /* CMDQV MMIO aperture bases and VCMDQ stride */ |
| 34 | #define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */ |
| 35 | #define CMDQV_VCMDQ_PAGE1_BASE 0x20000 |
| 36 | #define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */ |
| 37 | #define CMDQV_VINTF_PAGE1_BASE 0x40000 |
| 38 | #define CMDQV_VCMDQ_STRIDE 0x80 |
| 39 | |
| 40 | #define VINTF_PAGE_SIZE 0x10000 |
| 41 | |
| 42 | struct iommu_viommu_tegra241_cmdqv; |
| 43 | |
| 44 | typedef struct Tegra241CMDQV { |
| 45 | struct iommu_viommu_tegra241_cmdqv *cmdqv_data; |
| 46 | SMMUv3AccelState *s_accel; |
| 47 | MemoryRegion mmio_cmdqv; |
| 48 | qemu_irq irq; |
| 49 | IOMMUFDVeventq *veventq; |
| 50 | IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; |
| 51 | void *vintf_page0; |
| 52 | MemoryRegion *mr_vintf_page0; |
| 53 | |
| 54 | /* CMDQ-V Config page register cache */ |
| 55 | uint32_t config; |
| 56 | uint32_t param; |
| 57 | uint32_t status; |
| 58 | uint32_t vi_err_map[2]; |
| 59 | uint32_t vi_int_mask[2]; |
| 60 | uint32_t cmdq_err_map[4]; |
| 61 | uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; |
| 62 | |
| 63 | /* VINTF0 register cache (within CMDQ-V Config page) */ |
| 64 | uint32_t vintf_config; |
| 65 | uint32_t vintf_status; |
| 66 | uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID]; |
| 67 | uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID]; |
| 68 | uint32_t vintf_cmdq_err_map[4]; |
| 69 | /* |
| 70 | * VCMDQ register cache. The direct (VCMDQ aperture) and logical |
| 71 | * (VINTF aperture) views are hardware aliases; both are served from |
| 72 | * this single cached copy. |
| 73 | */ |
| 74 | uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ]; |
| 75 | uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ]; |
| 76 | uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ]; |
| 77 | uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ]; |
| 78 | uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ]; |
| 79 | uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ]; |
| 80 | uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ]; |
| 81 | uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ]; |
| 82 | } Tegra241CMDQV; |
| 83 | |
| 84 | /* CMDQ-V Config page registers (offset 0x00000) */ |
| 85 | REG32(CONFIG, 0x0) |
| 86 | FIELD(CONFIG, CMDQV_EN, 0, 1) |
| 87 | FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) |
| 88 | FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) |
| 89 | FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) |
| 90 | FIELD(CONFIG, CONS_DRAM_EN, 20, 1) |
| 91 | |
| 92 | /* CMDQV_EN=1, PER_CMD_OFFSET=16B, CLK_BATCH=256, CMD_BATCH=32. */ |
| 93 | #define V_CONFIG_RESET 0x00020083 |
| 94 | |
| 95 | REG32(PARAM, 0x4) |
| 96 | FIELD(PARAM, CMDQV_VER, 0, 4) |
| 97 | FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) |
| 98 | FIELD(PARAM, CMDQV_NUM_VI_LOG2, 8, 4) |
| 99 | FIELD(PARAM, CMDQV_NUM_SID_PER_VI_LOG2, 12, 4) |
| 100 | |
| 101 | REG32(STATUS, 0x8) |
| 102 | FIELD(STATUS, CMDQV_ENABLED, 0, 1) |
| 103 | |
| 104 | /* SMMU_CMDQV_VI_ERR_MAP_0/1 definitions */ |
| 105 | #define A_VI_ERR_MAP_0 0x14 |
| 106 | #define A_VI_ERR_MAP_1 0x18 |
| 107 | #define V_VI_ERR_MAP_NO_ERROR (0) |
| 108 | #define V_VI_ERR_MAP_ERROR (1) |
| 109 | |
| 110 | /* SMMU_CMDQV_VI_INT_MASK_0/1 definitions */ |
| 111 | #define A_VI_INT_MASK_0 0x1c |
| 112 | #define A_VI_INT_MASK_1 0x20 |
| 113 | #define V_VI_INT_MASK_NOT_MASKED (0) |
| 114 | #define V_VI_INT_MASK_MASKED (1) |
| 115 | |
| 116 | /* SMMU_CMDQV_CMDQ_ERR_MAP_0-3 definitions */ |
| 117 | #define A_CMDQ_ERR_MAP_0 0x24 |
| 118 | #define A_CMDQ_ERR_MAP_1 0x28 |
| 119 | #define A_CMDQ_ERR_MAP_2 0x2c |
| 120 | #define A_CMDQ_ERR_MAP_3 0x30 |
| 121 | |
| 122 | /* |
| 123 | * CMDQ_ALLOC_MAP: one entry per physical VCMDQ. Hardware supports up to 128 |
| 124 | * entries (CMDQV_NUM_CMDQ_LOG2=7), but QEMU only exposes |
| 125 | * TEGRA241_CMDQV_MAX_CMDQ (=2) VCMDQs per VM so only entries 0 and 1 are |
| 126 | * defined here. |
| 127 | */ |
| 128 | /* 2 identical register entries */ |
| 129 | #define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \ |
| 130 | REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ |
| 131 | FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ |
| 132 | FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ |
| 133 | FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) |
| 134 | |
| 135 | SMMU_CMDQV_CMDQ_ALLOC_MAP_(0) |
| 136 | SMMU_CMDQV_CMDQ_ALLOC_MAP_(1) |
| 137 | |
| 138 | /* SMMU_CMDQV_VINTF0 registers (only VINTF0 is exposed to the guest) */ |
| 139 | REG32(VINTF0_CONFIG, 0x1000) |
| 140 | FIELD(VINTF0_CONFIG, ENABLE, 0, 1) |
| 141 | FIELD(VINTF0_CONFIG, VMID, 1, 16) |
| 142 | FIELD(VINTF0_CONFIG, HYP_OWN, 17, 1) |
| 143 | |
| 144 | REG32(VINTF0_STATUS, 0x1004) |
| 145 | FIELD(VINTF0_STATUS, ENABLE_OK, 0, 1) |
| 146 | FIELD(VINTF0_STATUS, STATUS, 1, 3) |
| 147 | FIELD(VINTF0_STATUS, VI_NUM_LVCMDQ, 16, 8) |
| 148 | |
| 149 | #define V_VINTF_STATUS_NO_ERROR (0 << 1) |
| 150 | #define V_VINTF_STATUS_VCMDQ_ERROR (1 << 1) |
| 151 | |
| 152 | /* |
| 153 | * SMMU_CMDQV_VINTF0_SID_MATCH/_REPLACE: 16 entries per VINTF |
| 154 | * (CMDQV_NUM_SID_PER_VI_LOG2=4). Only _0 and _15 are defined, |
| 155 | * used as switch case range bounds. |
| 156 | */ |
| 157 | REG32(VINTF0_SID_MATCH_0, 0x1040) |
| 158 | FIELD(VINTF0_SID_MATCH_0, ENABLE, 0, 1) |
| 159 | FIELD(VINTF0_SID_MATCH_0, VIRT_SID, 1, 20) |
| 160 | #define A_VINTF0_SID_MATCH_15 (A_VINTF0_SID_MATCH_0 + 15 * 4) |
| 161 | |
| 162 | REG32(VINTF0_SID_REPLACE_0, 0x1080) |
| 163 | FIELD(VINTF0_SID_REPLACE_0, PHYS_SID, 0, 20) |
| 164 | #define A_VINTF0_SID_REPLACE_15 (A_VINTF0_SID_REPLACE_0 + 15 * 4) |
| 165 | |
| 166 | /* |
| 167 | * SMMU_CMDQV_VINTF0_LVCMDQ_ERR_MAP: 4 registers per VINTF covering 32 logical |
| 168 | * VCMDQs each. With TEGRA241_CMDQV_MAX_CMDQ=2, only MAP_0 bits [1:0] carry |
| 169 | * error state. MAP_1..MAP_3 always read as 0. Only _0 and _3 are defined, |
| 170 | * used as switch case range bounds. |
| 171 | */ |
| 172 | REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0) |
| 173 | FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32) |
| 174 | #define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4) |
| 175 | |
| 176 | /* |
| 177 | * Direct VCMDQ aperture register windows. |
| 178 | * |
| 179 | * Page 0 @ CMDQV_VCMDQ_PAGE0_BASE: VCMDQ control and status registers. |
| 180 | * Page 1 @ CMDQV_VCMDQ_PAGE1_BASE: VCMDQ base and DRAM address registers. |
| 181 | * |
| 182 | * Each VCMDQ occupies a CMDQV_VCMDQ_STRIDE-byte slot within its page. |
| 183 | */ |
| 184 | |
| 185 | /* --- Page 0 register macros --- */ |
| 186 | #define SMMU_CMDQV_VCMDQi_CONS_INDX_(i) \ |
| 187 | REG32(VCMDQ##i##_CONS_INDX, \ |
| 188 | CMDQV_VCMDQ_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ |
| 189 | FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ |
| 190 | FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) |
| 191 | |
| 192 | #define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 |
| 193 | #define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 |
| 194 | #define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 |
| 195 | #define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 |
| 196 | #define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 |
| 197 | |
| 198 | #define SMMU_CMDQV_VCMDQi_PROD_INDX_(i) \ |
| 199 | REG32(VCMDQ##i##_PROD_INDX, \ |
| 200 | CMDQV_VCMDQ_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ |
| 201 | FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) |
| 202 | |
| 203 | #define SMMU_CMDQV_VCMDQi_CONFIG_(i) \ |
| 204 | REG32(VCMDQ##i##_CONFIG, \ |
| 205 | CMDQV_VCMDQ_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ |
| 206 | FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) |
| 207 | |
| 208 | #define SMMU_CMDQV_VCMDQi_STATUS_(i) \ |
| 209 | REG32(VCMDQ##i##_STATUS, \ |
| 210 | CMDQV_VCMDQ_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ |
| 211 | FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) |
| 212 | |
| 213 | #define SMMU_CMDQV_VCMDQi_GERROR_(i) \ |
| 214 | REG32(VCMDQ##i##_GERROR, \ |
| 215 | CMDQV_VCMDQ_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ |
| 216 | FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ |
| 217 | FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ |
| 218 | FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) |
| 219 | |
| 220 | #define SMMU_CMDQV_VCMDQi_GERRORN_(i) \ |
| 221 | REG32(VCMDQ##i##_GERRORN, \ |
| 222 | CMDQV_VCMDQ_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ |
| 223 | FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ |
| 224 | FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ |
| 225 | FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) |
| 226 | |
| 227 | /* Page 0 layout: VCMDQ0 */ |
| 228 | SMMU_CMDQV_VCMDQi_CONS_INDX_(0) |
| 229 | SMMU_CMDQV_VCMDQi_PROD_INDX_(0) |
| 230 | SMMU_CMDQV_VCMDQi_CONFIG_(0) |
| 231 | SMMU_CMDQV_VCMDQi_STATUS_(0) |
| 232 | SMMU_CMDQV_VCMDQi_GERROR_(0) |
| 233 | SMMU_CMDQV_VCMDQi_GERRORN_(0) |
| 234 | |
| 235 | /* Page 0 layout: VCMDQ1 */ |
| 236 | SMMU_CMDQV_VCMDQi_CONS_INDX_(1) |
| 237 | SMMU_CMDQV_VCMDQi_PROD_INDX_(1) |
| 238 | SMMU_CMDQV_VCMDQi_CONFIG_(1) |
| 239 | SMMU_CMDQV_VCMDQi_STATUS_(1) |
| 240 | SMMU_CMDQV_VCMDQi_GERROR_(1) |
| 241 | SMMU_CMDQV_VCMDQi_GERRORN_(1) |
| 242 | |
| 243 | /* --- Page 1 register macros --- */ |
| 244 | #define SMMU_CMDQV_VCMDQi_BASE_L_(i) \ |
| 245 | REG32(VCMDQ##i##_BASE_L, CMDQV_VCMDQ_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \ |
| 246 | FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ |
| 247 | FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) |
| 248 | |
| 249 | #define SMMU_CMDQV_VCMDQi_BASE_H_(i) \ |
| 250 | REG32(VCMDQ##i##_BASE_H, \ |
| 251 | CMDQV_VCMDQ_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ |
| 252 | FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) |
| 253 | |
| 254 | #define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ |
| 255 | REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ |
| 256 | CMDQV_VCMDQ_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ |
| 257 | FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) |
| 258 | |
| 259 | #define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ |
| 260 | REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ |
| 261 | CMDQV_VCMDQ_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ |
| 262 | FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) |
| 263 | |
| 264 | /* Page 1 layout: VCMDQ0 */ |
| 265 | SMMU_CMDQV_VCMDQi_BASE_L_(0) |
| 266 | SMMU_CMDQV_VCMDQi_BASE_H_(0) |
| 267 | SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) |
| 268 | SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) |
| 269 | |
| 270 | /* Page 1 layout: VCMDQ1 */ |
| 271 | SMMU_CMDQV_VCMDQi_BASE_L_(1) |
| 272 | SMMU_CMDQV_VCMDQi_BASE_H_(1) |
| 273 | SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) |
| 274 | SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) |
| 275 | |
| 276 | /* |
| 277 | * VINTF0 logical VCMDQ aperture register windows. |
| 278 | * |
| 279 | * Page 0 @ CMDQV_VINTF_PAGE0_BASE: VCMDQ control and status registers. |
| 280 | * Page 1 @ CMDQV_VINTF_PAGE1_BASE: VCMDQ base and DRAM address registers. |
| 281 | * |
| 282 | * VCMDQs mapped via VINTF are accessed through this aperture as |
| 283 | * hardware aliases of the direct VCMDQ aperture above. |
| 284 | */ |
| 285 | |
| 286 | /* --- Page 0 register macros --- */ |
| 287 | #define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(i) \ |
| 288 | REG32(VI_VCMDQ##i##_CONS_INDX, \ |
| 289 | CMDQV_VINTF_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ |
| 290 | FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ |
| 291 | FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) |
| 292 | |
| 293 | #define SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(i) \ |
| 294 | REG32(VI_VCMDQ##i##_PROD_INDX, \ |
| 295 | CMDQV_VINTF_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ |
| 296 | FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) |
| 297 | |
| 298 | #define SMMU_CMDQV_VI_VCMDQi_CONFIG_(i) \ |
| 299 | REG32(VI_VCMDQ##i##_CONFIG, \ |
| 300 | CMDQV_VINTF_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ |
| 301 | FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) |
| 302 | |
| 303 | #define SMMU_CMDQV_VI_VCMDQi_STATUS_(i) \ |
| 304 | REG32(VI_VCMDQ##i##_STATUS, \ |
| 305 | CMDQV_VINTF_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ |
| 306 | FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) |
| 307 | |
| 308 | #define SMMU_CMDQV_VI_VCMDQi_GERROR_(i) \ |
| 309 | REG32(VI_VCMDQ##i##_GERROR, \ |
| 310 | CMDQV_VINTF_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ |
| 311 | FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ |
| 312 | FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ |
| 313 | FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) |
| 314 | |
| 315 | #define SMMU_CMDQV_VI_VCMDQi_GERRORN_(i) \ |
| 316 | REG32(VI_VCMDQ##i##_GERRORN, \ |
| 317 | CMDQV_VINTF_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ |
| 318 | FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ |
| 319 | FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ |
| 320 | FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) |
| 321 | |
| 322 | /* Page 0 layout: VCMDQ0 */ |
| 323 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(0) |
| 324 | SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(0) |
| 325 | SMMU_CMDQV_VI_VCMDQi_CONFIG_(0) |
| 326 | SMMU_CMDQV_VI_VCMDQi_STATUS_(0) |
| 327 | SMMU_CMDQV_VI_VCMDQi_GERROR_(0) |
| 328 | SMMU_CMDQV_VI_VCMDQi_GERRORN_(0) |
| 329 | |
| 330 | /* Page 0 layout: VCMDQ1 */ |
| 331 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(1) |
| 332 | SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(1) |
| 333 | SMMU_CMDQV_VI_VCMDQi_CONFIG_(1) |
| 334 | SMMU_CMDQV_VI_VCMDQi_STATUS_(1) |
| 335 | SMMU_CMDQV_VI_VCMDQi_GERROR_(1) |
| 336 | SMMU_CMDQV_VI_VCMDQi_GERRORN_(1) |
| 337 | |
| 338 | /* --- Page 1 register macros --- */ |
| 339 | #define SMMU_CMDQV_VI_VCMDQi_BASE_L_(i) \ |
| 340 | REG32(VI_VCMDQ##i##_BASE_L, \ |
| 341 | CMDQV_VINTF_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \ |
| 342 | FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ |
| 343 | FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) |
| 344 | |
| 345 | #define SMMU_CMDQV_VI_VCMDQi_BASE_H_(i) \ |
| 346 | REG32(VI_VCMDQ##i##_BASE_H, \ |
| 347 | CMDQV_VINTF_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ |
| 348 | FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) |
| 349 | |
| 350 | #define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ |
| 351 | REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ |
| 352 | CMDQV_VINTF_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ |
| 353 | FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) |
| 354 | |
| 355 | #define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ |
| 356 | REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ |
| 357 | CMDQV_VINTF_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ |
| 358 | FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) |
| 359 | |
| 360 | /* Page 1 layout: VCMDQ0 */ |
| 361 | SMMU_CMDQV_VI_VCMDQi_BASE_L_(0) |
| 362 | SMMU_CMDQV_VI_VCMDQi_BASE_H_(0) |
| 363 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) |
| 364 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) |
| 365 | |
| 366 | /* Page 1 layout: VCMDQ1 */ |
| 367 | SMMU_CMDQV_VI_VCMDQi_BASE_L_(1) |
| 368 | SMMU_CMDQV_VI_VCMDQi_BASE_H_(1) |
| 369 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) |
| 370 | SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) |
| 371 | |
| 372 | static inline bool tegra241_cmdqv_enabled(Tegra241CMDQV *cmdqv) |
| 373 | { |
| 374 | return cmdqv->status & R_STATUS_CMDQV_ENABLED_MASK; |
| 375 | } |
| 376 | |
| 377 | static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdqv) |
| 378 | { |
| 379 | return cmdqv->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK; |
| 380 | } |
| 381 | |
| 382 | const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); |
| 383 | |
| 384 | #endif /* HW_ARM_TEGRA241_CMDQV_H */ |