| 1 | /* |
| 2 | * ARM Versatile Express emulation. |
| 3 | * |
| 4 | * Copyright (c) 2010 - 2011 B Labs Ltd. |
| 5 | * Copyright (c) 2011 Linaro Limited |
| 6 | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | * |
| 20 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 21 | * GNU GPL, version 2 or (at your option) any later version. |
| 22 | */ |
| 23 | |
| 24 | #include "qemu/osdep.h" |
| 25 | #include "qapi/error.h" |
| 26 | #include "qemu/datadir.h" |
| 27 | #include "hw/core/sysbus.h" |
| 28 | #include "hw/arm/boot.h" |
| 29 | #include "hw/arm/machines-qom.h" |
| 30 | #include "hw/misc/arm_sysctl.h" |
| 31 | #include "hw/net/lan9118.h" |
| 32 | #include "hw/i2c/i2c.h" |
| 33 | #include "net/net.h" |
| 34 | #include "system/system.h" |
| 35 | #include "hw/core/boards.h" |
| 36 | #include "hw/core/loader.h" |
| 37 | #include "hw/block/flash.h" |
| 38 | #include "system/device_tree.h" |
| 39 | #include "qemu/error-report.h" |
| 40 | #include <libfdt.h> |
| 41 | #include "hw/char/pl011.h" |
| 42 | #include "hw/cpu/a9mpcore.h" |
| 43 | #include "hw/cpu/a15mpcore.h" |
| 44 | #include "hw/i2c/arm_sbcon_i2c.h" |
| 45 | #include "hw/sd/sd.h" |
| 46 | #include "qobject/qlist.h" |
| 47 | #include "qom/object.h" |
| 48 | #include "target/arm/cpu-qom.h" |
| 49 | |
| 50 | #define VEXPRESS_BOARD_ID 0x8e0 |
| 51 | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) |
| 52 | #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) |
| 53 | |
| 54 | #define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */ |
| 55 | |
| 56 | /* Number of virtio transports to create (0..8; limited by |
| 57 | * number of available IRQ lines). |
| 58 | */ |
| 59 | #define NUM_VIRTIO_TRANSPORTS 4 |
| 60 | |
| 61 | /* Address maps for peripherals: |
| 62 | * the Versatile Express motherboard has two possible maps, |
| 63 | * the "legacy" one (used for A9) and the "Cortex-A Series" |
| 64 | * map (used for newer cores). |
| 65 | * Individual daughterboards can also have different maps for |
| 66 | * their peripherals. |
| 67 | */ |
| 68 | |
| 69 | enum { |
| 70 | VE_SYSREGS, |
| 71 | VE_SP810, |
| 72 | VE_SERIALPCI, |
| 73 | VE_PL041, |
| 74 | VE_MMCI, |
| 75 | VE_KMI0, |
| 76 | VE_KMI1, |
| 77 | VE_UART0, |
| 78 | VE_UART1, |
| 79 | VE_UART2, |
| 80 | VE_UART3, |
| 81 | VE_WDT, |
| 82 | VE_TIMER01, |
| 83 | VE_TIMER23, |
| 84 | VE_SERIALDVI, |
| 85 | VE_RTC, |
| 86 | VE_COMPACTFLASH, |
| 87 | VE_CLCD, |
| 88 | VE_NORFLASH0, |
| 89 | VE_NORFLASH1, |
| 90 | VE_NORFLASHALIAS, |
| 91 | VE_SRAM, |
| 92 | VE_VIDEORAM, |
| 93 | VE_ETHERNET, |
| 94 | VE_USB, |
| 95 | VE_DAPROM, |
| 96 | VE_VIRTIO, |
| 97 | }; |
| 98 | |
| 99 | static hwaddr motherboard_legacy_map[] = { |
| 100 | [VE_NORFLASHALIAS] = 0, |
| 101 | /* CS7: 0x10000000 .. 0x10020000 */ |
| 102 | [VE_SYSREGS] = 0x10000000, |
| 103 | [VE_SP810] = 0x10001000, |
| 104 | [VE_SERIALPCI] = 0x10002000, |
| 105 | [VE_PL041] = 0x10004000, |
| 106 | [VE_MMCI] = 0x10005000, |
| 107 | [VE_KMI0] = 0x10006000, |
| 108 | [VE_KMI1] = 0x10007000, |
| 109 | [VE_UART0] = 0x10009000, |
| 110 | [VE_UART1] = 0x1000a000, |
| 111 | [VE_UART2] = 0x1000b000, |
| 112 | [VE_UART3] = 0x1000c000, |
| 113 | [VE_WDT] = 0x1000f000, |
| 114 | [VE_TIMER01] = 0x10011000, |
| 115 | [VE_TIMER23] = 0x10012000, |
| 116 | [VE_VIRTIO] = 0x10013000, |
| 117 | [VE_SERIALDVI] = 0x10016000, |
| 118 | [VE_RTC] = 0x10017000, |
| 119 | [VE_COMPACTFLASH] = 0x1001a000, |
| 120 | [VE_CLCD] = 0x1001f000, |
| 121 | /* CS0: 0x40000000 .. 0x44000000 */ |
| 122 | [VE_NORFLASH0] = 0x40000000, |
| 123 | /* CS1: 0x44000000 .. 0x48000000 */ |
| 124 | [VE_NORFLASH1] = 0x44000000, |
| 125 | /* CS2: 0x48000000 .. 0x4a000000 */ |
| 126 | [VE_SRAM] = 0x48000000, |
| 127 | /* CS3: 0x4c000000 .. 0x50000000 */ |
| 128 | [VE_VIDEORAM] = 0x4c000000, |
| 129 | [VE_ETHERNET] = 0x4e000000, |
| 130 | [VE_USB] = 0x4f000000, |
| 131 | }; |
| 132 | |
| 133 | static hwaddr motherboard_aseries_map[] = { |
| 134 | [VE_NORFLASHALIAS] = 0, |
| 135 | /* CS0: 0x08000000 .. 0x0c000000 */ |
| 136 | [VE_NORFLASH0] = 0x08000000, |
| 137 | /* CS4: 0x0c000000 .. 0x10000000 */ |
| 138 | [VE_NORFLASH1] = 0x0c000000, |
| 139 | /* CS5: 0x10000000 .. 0x14000000 */ |
| 140 | /* CS1: 0x14000000 .. 0x18000000 */ |
| 141 | [VE_SRAM] = 0x14000000, |
| 142 | /* CS2: 0x18000000 .. 0x1c000000 */ |
| 143 | [VE_VIDEORAM] = 0x18000000, |
| 144 | [VE_ETHERNET] = 0x1a000000, |
| 145 | [VE_USB] = 0x1b000000, |
| 146 | /* CS3: 0x1c000000 .. 0x20000000 */ |
| 147 | [VE_DAPROM] = 0x1c000000, |
| 148 | [VE_SYSREGS] = 0x1c010000, |
| 149 | [VE_SP810] = 0x1c020000, |
| 150 | [VE_SERIALPCI] = 0x1c030000, |
| 151 | [VE_PL041] = 0x1c040000, |
| 152 | [VE_MMCI] = 0x1c050000, |
| 153 | [VE_KMI0] = 0x1c060000, |
| 154 | [VE_KMI1] = 0x1c070000, |
| 155 | [VE_UART0] = 0x1c090000, |
| 156 | [VE_UART1] = 0x1c0a0000, |
| 157 | [VE_UART2] = 0x1c0b0000, |
| 158 | [VE_UART3] = 0x1c0c0000, |
| 159 | [VE_WDT] = 0x1c0f0000, |
| 160 | [VE_TIMER01] = 0x1c110000, |
| 161 | [VE_TIMER23] = 0x1c120000, |
| 162 | [VE_VIRTIO] = 0x1c130000, |
| 163 | [VE_SERIALDVI] = 0x1c160000, |
| 164 | [VE_RTC] = 0x1c170000, |
| 165 | [VE_COMPACTFLASH] = 0x1c1a0000, |
| 166 | [VE_CLCD] = 0x1c1f0000, |
| 167 | }; |
| 168 | |
| 169 | /* Structure defining the peculiarities of a specific daughterboard */ |
| 170 | |
| 171 | typedef struct VEDBoardInfo VEDBoardInfo; |
| 172 | |
| 173 | struct VexpressMachineClass { |
| 174 | MachineClass parent; |
| 175 | VEDBoardInfo *daughterboard; |
| 176 | }; |
| 177 | |
| 178 | struct VexpressMachineState { |
| 179 | MachineState parent; |
| 180 | MemoryRegion vram; |
| 181 | MemoryRegion sram; |
| 182 | MemoryRegion flashalias; |
| 183 | MemoryRegion a15sram; |
| 184 | bool secure; |
| 185 | bool virt; |
| 186 | }; |
| 187 | |
| 188 | #define TYPE_VEXPRESS_MACHINE "vexpress" |
| 189 | #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") |
| 190 | #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") |
| 191 | OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) |
| 192 | |
| 193 | typedef void DBoardInitFn(VexpressMachineState *machine, |
| 194 | ram_addr_t ram_size, |
| 195 | const char *cpu_type, |
| 196 | qemu_irq *pic); |
| 197 | |
| 198 | struct VEDBoardInfo { |
| 199 | struct arm_boot_info bootinfo; |
| 200 | const hwaddr *motherboard_map; |
| 201 | hwaddr loader_start; |
| 202 | const hwaddr gic_cpu_if_addr; |
| 203 | uint32_t proc_id; |
| 204 | uint32_t num_voltage_sensors; |
| 205 | const uint32_t *voltages; |
| 206 | uint32_t num_clocks; |
| 207 | const uint32_t *clocks; |
| 208 | DBoardInitFn *init; |
| 209 | }; |
| 210 | |
| 211 | static void init_cpus(MachineState *ms, const char *cpu_type, |
| 212 | const char *privdev, hwaddr periphbase, |
| 213 | qemu_irq *pic, bool secure, bool virt) |
| 214 | { |
| 215 | DeviceState *dev; |
| 216 | SysBusDevice *busdev; |
| 217 | int n; |
| 218 | unsigned int smp_cpus = ms->smp.cpus; |
| 219 | |
| 220 | /* Create the actual CPUs */ |
| 221 | for (n = 0; n < smp_cpus; n++) { |
| 222 | Object *cpuobj = object_new(cpu_type); |
| 223 | |
| 224 | if (!secure) { |
| 225 | object_property_set_bool(cpuobj, "has_el3", false, NULL); |
| 226 | } |
| 227 | if (!virt) { |
| 228 | if (object_property_find(cpuobj, "has_el2")) { |
| 229 | object_property_set_bool(cpuobj, "has_el2", false, NULL); |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | if (object_property_find(cpuobj, "reset-cbar")) { |
| 234 | object_property_set_int(cpuobj, "reset-cbar", periphbase, |
| 235 | &error_abort); |
| 236 | } |
| 237 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 238 | } |
| 239 | |
| 240 | /* Create the private peripheral devices (including the GIC); |
| 241 | * this must happen after the CPUs are created because a15mpcore_priv |
| 242 | * wires itself up to the CPU's generic_timer gpio out lines. |
| 243 | */ |
| 244 | dev = qdev_new(privdev); |
| 245 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
| 246 | qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); |
| 247 | busdev = SYS_BUS_DEVICE(dev); |
| 248 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 249 | sysbus_mmio_map(busdev, 0, periphbase); |
| 250 | |
| 251 | /* Interrupts [42:0] are from the motherboard; |
| 252 | * [47:43] are reserved; [63:48] are daughterboard |
| 253 | * peripherals. Note that some documentation numbers |
| 254 | * external interrupts starting from 32 (because there |
| 255 | * are internal interrupts 0..31). |
| 256 | */ |
| 257 | for (n = 0; n < GIC_EXT_IRQS; n++) { |
| 258 | pic[n] = qdev_get_gpio_in(dev, n); |
| 259 | } |
| 260 | |
| 261 | /* Connect the CPUs to the GIC */ |
| 262 | for (n = 0; n < smp_cpus; n++) { |
| 263 | DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); |
| 264 | |
| 265 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
| 266 | sysbus_connect_irq(busdev, n + smp_cpus, |
| 267 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); |
| 268 | sysbus_connect_irq(busdev, n + 2 * smp_cpus, |
| 269 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); |
| 270 | sysbus_connect_irq(busdev, n + 3 * smp_cpus, |
| 271 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | static void a9_daughterboard_init(VexpressMachineState *vms, |
| 276 | ram_addr_t ram_size, |
| 277 | const char *cpu_type, |
| 278 | qemu_irq *pic) |
| 279 | { |
| 280 | MachineState *machine = MACHINE(vms); |
| 281 | MemoryRegion *sysmem = get_system_memory(); |
| 282 | DeviceState *dev; |
| 283 | |
| 284 | if (ram_size > 0x40000000) { |
| 285 | /* 1GB is the maximum the address space permits */ |
| 286 | error_report("vexpress-a9: cannot model more than 1GB RAM"); |
| 287 | exit(1); |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * RAM is from 0x60000000 upwards. The bottom 64MB of the |
| 292 | * address space should in theory be remappable to various |
| 293 | * things including ROM or RAM; we always map the flash there. |
| 294 | */ |
| 295 | memory_region_add_subregion(sysmem, 0x60000000, machine->ram); |
| 296 | |
| 297 | /* 0x1e000000 A9MPCore (SCU) private memory region */ |
| 298 | init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, |
| 299 | vms->secure, vms->virt); |
| 300 | |
| 301 | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ |
| 302 | |
| 303 | /* 0x10020000 PL111 CLCD (daughterboard) */ |
| 304 | dev = qdev_new("pl111"); |
| 305 | object_property_set_link(OBJECT(dev), "framebuffer-memory", |
| 306 | OBJECT(sysmem), &error_fatal); |
| 307 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 308 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000); |
| 309 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]); |
| 310 | |
| 311 | /* 0x10060000 AXI RAM */ |
| 312 | /* 0x100e0000 PL341 Dynamic Memory Controller */ |
| 313 | /* 0x100e1000 PL354 Static Memory Controller */ |
| 314 | /* 0x100e2000 System Configuration Controller */ |
| 315 | |
| 316 | sysbus_create_simple("sp804", 0x100e4000, pic[48]); |
| 317 | /* 0x100e5000 SP805 Watchdog module */ |
| 318 | /* 0x100e6000 BP147 TrustZone Protection Controller */ |
| 319 | /* 0x100e9000 PL301 'Fast' AXI matrix */ |
| 320 | /* 0x100ea000 PL301 'Slow' AXI matrix */ |
| 321 | /* 0x100ec000 TrustZone Address Space Controller */ |
| 322 | /* 0x10200000 CoreSight debug APB */ |
| 323 | /* 0x1e00a000 PL310 L2 Cache Controller */ |
| 324 | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); |
| 325 | } |
| 326 | |
| 327 | /* Voltage values for SYS_CFG_VOLT daughterboard registers; |
| 328 | * values are in microvolts. |
| 329 | */ |
| 330 | static const uint32_t a9_voltages[] = { |
| 331 | 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ |
| 332 | 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ |
| 333 | 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ |
| 334 | 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ |
| 335 | 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ |
| 336 | 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ |
| 337 | }; |
| 338 | |
| 339 | /* Reset values for daughterboard oscillators (in Hz) */ |
| 340 | static const uint32_t a9_clocks[] = { |
| 341 | 45000000, /* AMBA AXI ACLK: 45MHz */ |
| 342 | 23750000, /* daughterboard CLCD clock: 23.75MHz */ |
| 343 | 66670000, /* Test chip reference clock: 66.67MHz */ |
| 344 | }; |
| 345 | |
| 346 | static VEDBoardInfo a9_daughterboard = { |
| 347 | .motherboard_map = motherboard_legacy_map, |
| 348 | .loader_start = 0x60000000, |
| 349 | .gic_cpu_if_addr = 0x1e000100, |
| 350 | .proc_id = 0x0c000191, |
| 351 | .num_voltage_sensors = ARRAY_SIZE(a9_voltages), |
| 352 | .voltages = a9_voltages, |
| 353 | .num_clocks = ARRAY_SIZE(a9_clocks), |
| 354 | .clocks = a9_clocks, |
| 355 | .init = a9_daughterboard_init, |
| 356 | }; |
| 357 | |
| 358 | static void a15_daughterboard_init(VexpressMachineState *vms, |
| 359 | ram_addr_t ram_size, |
| 360 | const char *cpu_type, |
| 361 | qemu_irq *pic) |
| 362 | { |
| 363 | MachineState *machine = MACHINE(vms); |
| 364 | MemoryRegion *sysmem = get_system_memory(); |
| 365 | |
| 366 | { |
| 367 | /* We have to use a separate 64 bit variable here to avoid the gcc |
| 368 | * "comparison is always false due to limited range of data type" |
| 369 | * warning if we are on a host where ram_addr_t is 32 bits. |
| 370 | */ |
| 371 | uint64_t rsz = ram_size; |
| 372 | if (rsz > (30ULL * 1024 * 1024 * 1024)) { |
| 373 | error_report("vexpress-a15: cannot model more than 30GB RAM"); |
| 374 | exit(1); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ |
| 379 | memory_region_add_subregion(sysmem, 0x80000000, machine->ram); |
| 380 | |
| 381 | /* 0x2c000000 A15MPCore private memory region (GIC) */ |
| 382 | init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, |
| 383 | 0x2c000000, pic, vms->secure, vms->virt); |
| 384 | |
| 385 | /* A15 daughterboard peripherals: */ |
| 386 | |
| 387 | /* 0x20000000: CoreSight interfaces: not modelled */ |
| 388 | /* 0x2a000000: PL301 AXI interconnect: not modelled */ |
| 389 | /* 0x2a420000: SCC: not modelled */ |
| 390 | /* 0x2a430000: system counter: not modelled */ |
| 391 | /* 0x2b000000: HDLCD controller: not modelled */ |
| 392 | /* 0x2b060000: SP805 watchdog: not modelled */ |
| 393 | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ |
| 394 | /* 0x2e000000: system SRAM */ |
| 395 | memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, |
| 396 | &error_fatal); |
| 397 | memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); |
| 398 | |
| 399 | /* 0x7ffb0000: DMA330 DMA controller: not modelled */ |
| 400 | /* 0x7ffd0000: PL354 static memory controller: not modelled */ |
| 401 | } |
| 402 | |
| 403 | static const uint32_t a15_voltages[] = { |
| 404 | 900000, /* Vcore: 0.9V : CPU core voltage */ |
| 405 | }; |
| 406 | |
| 407 | static const uint32_t a15_clocks[] = { |
| 408 | 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ |
| 409 | 0, /* OSCCLK1: reserved */ |
| 410 | 0, /* OSCCLK2: reserved */ |
| 411 | 0, /* OSCCLK3: reserved */ |
| 412 | 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ |
| 413 | 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ |
| 414 | 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ |
| 415 | 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ |
| 416 | 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ |
| 417 | }; |
| 418 | |
| 419 | static VEDBoardInfo a15_daughterboard = { |
| 420 | .motherboard_map = motherboard_aseries_map, |
| 421 | .loader_start = 0x80000000, |
| 422 | .gic_cpu_if_addr = 0x2c002000, |
| 423 | .proc_id = 0x14000237, |
| 424 | .num_voltage_sensors = ARRAY_SIZE(a15_voltages), |
| 425 | .voltages = a15_voltages, |
| 426 | .num_clocks = ARRAY_SIZE(a15_clocks), |
| 427 | .clocks = a15_clocks, |
| 428 | .init = a15_daughterboard_init, |
| 429 | }; |
| 430 | |
| 431 | static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, |
| 432 | hwaddr addr, hwaddr size, uint32_t intc, |
| 433 | int irq) |
| 434 | { |
| 435 | /* Add a virtio_mmio node to the device tree blob: |
| 436 | * virtio_mmio@ADDRESS { |
| 437 | * compatible = "virtio,mmio"; |
| 438 | * reg = <ADDRESS, SIZE>; |
| 439 | * interrupt-parent = <&intc>; |
| 440 | * interrupts = <0, irq, 1>; |
| 441 | * } |
| 442 | * (Note that the format of the interrupts property is dependent on the |
| 443 | * interrupt controller that interrupt-parent points to; these are for |
| 444 | * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) |
| 445 | */ |
| 446 | int rc; |
| 447 | char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); |
| 448 | |
| 449 | rc = qemu_fdt_add_subnode(fdt, nodename); |
| 450 | rc |= qemu_fdt_setprop_string(fdt, nodename, |
| 451 | "compatible", "virtio,mmio"); |
| 452 | rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", |
| 453 | acells, addr, scells, size); |
| 454 | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); |
| 455 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); |
| 456 | qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); |
| 457 | g_free(nodename); |
| 458 | if (rc) { |
| 459 | return -1; |
| 460 | } |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | static uint32_t find_int_controller(void *fdt) |
| 465 | { |
| 466 | /* Find the FDT node corresponding to the interrupt controller |
| 467 | * for virtio-mmio devices. We do this by scanning the fdt for |
| 468 | * a node with the right compatibility, since we know there is |
| 469 | * only one GIC on a vexpress board. |
| 470 | * We return the phandle of the node, or 0 if none was found. |
| 471 | */ |
| 472 | const char *compat = "arm,cortex-a9-gic"; |
| 473 | int offset; |
| 474 | |
| 475 | offset = fdt_node_offset_by_compatible(fdt, -1, compat); |
| 476 | if (offset >= 0) { |
| 477 | return fdt_get_phandle(fdt, offset); |
| 478 | } |
| 479 | return 0; |
| 480 | } |
| 481 | |
| 482 | static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) |
| 483 | { |
| 484 | uint32_t acells, scells, intc; |
| 485 | const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; |
| 486 | |
| 487 | acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", |
| 488 | NULL, &error_fatal); |
| 489 | scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", |
| 490 | NULL, &error_fatal); |
| 491 | intc = find_int_controller(fdt); |
| 492 | if (!intc) { |
| 493 | /* Not fatal, we just won't provide virtio. This will |
| 494 | * happen with older device tree blobs. |
| 495 | */ |
| 496 | warn_report("couldn't find interrupt controller in " |
| 497 | "dtb; will not include virtio-mmio devices in the dtb"); |
| 498 | } else { |
| 499 | int i; |
| 500 | const hwaddr *map = daughterboard->motherboard_map; |
| 501 | |
| 502 | /* We iterate backwards here because adding nodes |
| 503 | * to the dtb puts them in last-first. |
| 504 | */ |
| 505 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
| 506 | add_virtio_mmio_node(fdt, acells, scells, |
| 507 | map[VE_VIRTIO] + 0x200 * i, |
| 508 | 0x200, intc, 40 + i); |
| 509 | } |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | |
| 514 | /* Open code a private version of pflash registration since we |
| 515 | * need to set non-default device width for VExpress platform. |
| 516 | */ |
| 517 | static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, |
| 518 | DriveInfo *di) |
| 519 | { |
| 520 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 521 | |
| 522 | if (di) { |
| 523 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); |
| 524 | } |
| 525 | |
| 526 | qdev_prop_set_uint32(dev, "num-blocks", |
| 527 | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); |
| 528 | qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); |
| 529 | qdev_prop_set_uint8(dev, "width", 4); |
| 530 | qdev_prop_set_uint8(dev, "device-width", 2); |
| 531 | qdev_prop_set_bit(dev, "big-endian", false); |
| 532 | qdev_prop_set_uint16(dev, "id0", 0x89); |
| 533 | qdev_prop_set_uint16(dev, "id1", 0x18); |
| 534 | qdev_prop_set_uint16(dev, "id2", 0x00); |
| 535 | qdev_prop_set_uint16(dev, "id3", 0x00); |
| 536 | qdev_prop_set_string(dev, "name", name); |
| 537 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 538 | |
| 539 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 540 | return PFLASH_CFI01(dev); |
| 541 | } |
| 542 | |
| 543 | static void vexpress_common_init(MachineState *machine) |
| 544 | { |
| 545 | VexpressMachineState *vms = VEXPRESS_MACHINE(machine); |
| 546 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); |
| 547 | VEDBoardInfo *daughterboard = vmc->daughterboard; |
| 548 | DeviceState *dev, *sysctl, *pl041; |
| 549 | qemu_irq pic[GIC_EXT_IRQS]; |
| 550 | uint32_t sys_id; |
| 551 | DriveInfo *dinfo; |
| 552 | PFlashCFI01 *pflash0; |
| 553 | I2CBus *i2c; |
| 554 | ram_addr_t vram_size, sram_size; |
| 555 | MemoryRegion *sysmem = get_system_memory(); |
| 556 | const hwaddr *map = daughterboard->motherboard_map; |
| 557 | QList *db_voltage, *db_clock; |
| 558 | int i; |
| 559 | |
| 560 | daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); |
| 561 | |
| 562 | /* |
| 563 | * If a bios file was provided, attempt to map it into memory |
| 564 | */ |
| 565 | if (machine->firmware) { |
| 566 | char *fn; |
| 567 | int image_size; |
| 568 | |
| 569 | if (drive_get(IF_PFLASH, 0, 0)) { |
| 570 | error_report("The contents of the first flash device may be " |
| 571 | "specified with -bios or with -drive if=pflash... " |
| 572 | "but you cannot use both options at once"); |
| 573 | exit(1); |
| 574 | } |
| 575 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); |
| 576 | if (!fn) { |
| 577 | error_report("Could not find ROM image '%s'", machine->firmware); |
| 578 | exit(1); |
| 579 | } |
| 580 | image_size = load_image_targphys(fn, map[VE_NORFLASH0], |
| 581 | VEXPRESS_FLASH_SIZE, NULL); |
| 582 | g_free(fn); |
| 583 | if (image_size < 0) { |
| 584 | error_report("Could not load ROM image '%s'", machine->firmware); |
| 585 | exit(1); |
| 586 | } |
| 587 | } |
| 588 | |
| 589 | /* Motherboard peripherals: the wiring is the same but the |
| 590 | * addresses vary between the legacy and A-Series memory maps. |
| 591 | */ |
| 592 | |
| 593 | sys_id = 0x1190f500; |
| 594 | |
| 595 | sysctl = qdev_new("realview_sysctl"); |
| 596 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); |
| 597 | qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); |
| 598 | |
| 599 | db_voltage = qlist_new(); |
| 600 | for (i = 0; i < daughterboard->num_voltage_sensors; i++) { |
| 601 | qlist_append_int(db_voltage, daughterboard->voltages[i]); |
| 602 | } |
| 603 | qdev_prop_set_array(sysctl, "db-voltage", db_voltage); |
| 604 | |
| 605 | db_clock = qlist_new(); |
| 606 | for (i = 0; i < daughterboard->num_clocks; i++) { |
| 607 | qlist_append_int(db_clock, daughterboard->clocks[i]); |
| 608 | } |
| 609 | qdev_prop_set_array(sysctl, "db-clock", db_clock); |
| 610 | |
| 611 | sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); |
| 612 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); |
| 613 | |
| 614 | /* VE_SP810: not modelled */ |
| 615 | /* VE_SERIALPCI: not modelled */ |
| 616 | |
| 617 | pl041 = qdev_new("pl041"); |
| 618 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
| 619 | if (machine->audiodev) { |
| 620 | qdev_prop_set_string(pl041, "audiodev", machine->audiodev); |
| 621 | } |
| 622 | sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); |
| 623 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); |
| 624 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); |
| 625 | |
| 626 | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
| 627 | /* Wire up MMC card detect and read-only signals */ |
| 628 | qdev_connect_gpio_out_named(dev, "card-read-only", 0, |
| 629 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); |
| 630 | qdev_connect_gpio_out_named(dev, "card-inserted", 0, |
| 631 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); |
| 632 | dinfo = drive_get(IF_SD, 0, 0); |
| 633 | if (dinfo) { |
| 634 | DeviceState *card; |
| 635 | |
| 636 | card = qdev_new(TYPE_SD_CARD); |
| 637 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), |
| 638 | &error_fatal); |
| 639 | qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), |
| 640 | &error_fatal); |
| 641 | } |
| 642 | |
| 643 | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
| 644 | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); |
| 645 | |
| 646 | pl011_create(map[VE_UART0], pic[5], serial_hd(0)); |
| 647 | pl011_create(map[VE_UART1], pic[6], serial_hd(1)); |
| 648 | pl011_create(map[VE_UART2], pic[7], serial_hd(2)); |
| 649 | pl011_create(map[VE_UART3], pic[8], serial_hd(3)); |
| 650 | |
| 651 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
| 652 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); |
| 653 | |
| 654 | dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL); |
| 655 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
| 656 | i2c_slave_create_simple(i2c, "sii9022", 0x39); |
| 657 | |
| 658 | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
| 659 | |
| 660 | /* VE_COMPACTFLASH: not modelled */ |
| 661 | |
| 662 | dev = qdev_new("pl111"); |
| 663 | object_property_set_link(OBJECT(dev), "framebuffer-memory", |
| 664 | OBJECT(sysmem), &error_fatal); |
| 665 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 666 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]); |
| 667 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]); |
| 668 | |
| 669 | dinfo = drive_get(IF_PFLASH, 0, 0); |
| 670 | pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", |
| 671 | dinfo); |
| 672 | |
| 673 | if (map[VE_NORFLASHALIAS] != -1) { |
| 674 | /* Map flash 0 as an alias into low memory */ |
| 675 | MemoryRegion *flash0mem; |
| 676 | flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); |
| 677 | memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", |
| 678 | flash0mem, 0, VEXPRESS_FLASH_SIZE); |
| 679 | memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); |
| 680 | } |
| 681 | |
| 682 | dinfo = drive_get(IF_PFLASH, 0, 1); |
| 683 | ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); |
| 684 | |
| 685 | sram_size = 0x2000000; |
| 686 | memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, |
| 687 | &error_fatal); |
| 688 | memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); |
| 689 | |
| 690 | vram_size = 0x800000; |
| 691 | memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, |
| 692 | &error_fatal); |
| 693 | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); |
| 694 | |
| 695 | /* 0x4e000000 LAN9118 Ethernet */ |
| 696 | if (qemu_find_nic_info("lan9118", true, NULL)) { |
| 697 | lan9118_init(map[VE_ETHERNET], pic[15]); |
| 698 | } |
| 699 | |
| 700 | /* VE_USB: not modelled */ |
| 701 | |
| 702 | /* VE_DAPROM: not modelled */ |
| 703 | |
| 704 | /* Create mmio transports, so the user can create virtio backends |
| 705 | * (which will be automatically plugged in to the transports). If |
| 706 | * no backend is created the transport will just sit harmlessly idle. |
| 707 | */ |
| 708 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { |
| 709 | sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, |
| 710 | pic[40 + i]); |
| 711 | } |
| 712 | |
| 713 | daughterboard->bootinfo.ram_size = machine->ram_size; |
| 714 | daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; |
| 715 | daughterboard->bootinfo.loader_start = daughterboard->loader_start; |
| 716 | daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; |
| 717 | daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; |
| 718 | daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; |
| 719 | daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; |
| 720 | /* When booting Linux we should be in secure state if the CPU has one. */ |
| 721 | daughterboard->bootinfo.secure_boot = vms->secure; |
| 722 | arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); |
| 723 | } |
| 724 | |
| 725 | static bool vexpress_get_secure(Object *obj, Error **errp) |
| 726 | { |
| 727 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 728 | |
| 729 | return vms->secure; |
| 730 | } |
| 731 | |
| 732 | static void vexpress_set_secure(Object *obj, bool value, Error **errp) |
| 733 | { |
| 734 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 735 | |
| 736 | vms->secure = value; |
| 737 | } |
| 738 | |
| 739 | static bool vexpress_get_virt(Object *obj, Error **errp) |
| 740 | { |
| 741 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 742 | |
| 743 | return vms->virt; |
| 744 | } |
| 745 | |
| 746 | static void vexpress_set_virt(Object *obj, bool value, Error **errp) |
| 747 | { |
| 748 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 749 | |
| 750 | vms->virt = value; |
| 751 | } |
| 752 | |
| 753 | static void vexpress_instance_init(Object *obj) |
| 754 | { |
| 755 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 756 | |
| 757 | /* EL3 is enabled by default on vexpress */ |
| 758 | vms->secure = true; |
| 759 | } |
| 760 | |
| 761 | static void vexpress_a15_instance_init(Object *obj) |
| 762 | { |
| 763 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 764 | |
| 765 | /* |
| 766 | * For the vexpress-a15, EL2 is by default enabled if EL3 is, |
| 767 | * but can also be specifically set to on or off. |
| 768 | */ |
| 769 | vms->virt = true; |
| 770 | } |
| 771 | |
| 772 | static void vexpress_a9_instance_init(Object *obj) |
| 773 | { |
| 774 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); |
| 775 | |
| 776 | /* The A9 doesn't have the virt extensions */ |
| 777 | vms->virt = false; |
| 778 | } |
| 779 | |
| 780 | static void vexpress_class_init(ObjectClass *oc, const void *data) |
| 781 | { |
| 782 | MachineClass *mc = MACHINE_CLASS(oc); |
| 783 | |
| 784 | mc->desc = "ARM Versatile Express"; |
| 785 | mc->init = vexpress_common_init; |
| 786 | mc->max_cpus = 4; |
| 787 | mc->ignore_memory_transaction_failures = true; |
| 788 | mc->default_ram_id = "vexpress.highmem"; |
| 789 | |
| 790 | machine_add_audiodev_property(mc); |
| 791 | object_class_property_add_bool(oc, "secure", vexpress_get_secure, |
| 792 | vexpress_set_secure); |
| 793 | object_class_property_set_description(oc, "secure", |
| 794 | "Set on/off to enable/disable the ARM " |
| 795 | "Security Extensions (TrustZone)"); |
| 796 | } |
| 797 | |
| 798 | static void vexpress_a9_class_init(ObjectClass *oc, const void *data) |
| 799 | { |
| 800 | static const char * const valid_cpu_types[] = { |
| 801 | ARM_CPU_TYPE_NAME("cortex-a9"), |
| 802 | NULL |
| 803 | }; |
| 804 | MachineClass *mc = MACHINE_CLASS(oc); |
| 805 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); |
| 806 | |
| 807 | mc->desc = "ARM Versatile Express for Cortex-A9"; |
| 808 | mc->valid_cpu_types = valid_cpu_types; |
| 809 | mc->auto_create_sdcard = true; |
| 810 | |
| 811 | vmc->daughterboard = &a9_daughterboard; |
| 812 | } |
| 813 | |
| 814 | static void vexpress_a15_class_init(ObjectClass *oc, const void *data) |
| 815 | { |
| 816 | static const char * const valid_cpu_types[] = { |
| 817 | ARM_CPU_TYPE_NAME("cortex-a15"), |
| 818 | NULL |
| 819 | }; |
| 820 | MachineClass *mc = MACHINE_CLASS(oc); |
| 821 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); |
| 822 | |
| 823 | mc->desc = "ARM Versatile Express for Cortex-A15"; |
| 824 | mc->valid_cpu_types = valid_cpu_types; |
| 825 | mc->auto_create_sdcard = true; |
| 826 | |
| 827 | vmc->daughterboard = &a15_daughterboard; |
| 828 | |
| 829 | object_class_property_add_bool(oc, "virtualization", vexpress_get_virt, |
| 830 | vexpress_set_virt); |
| 831 | object_class_property_set_description(oc, "virtualization", |
| 832 | "Set on/off to enable/disable the ARM " |
| 833 | "Virtualization Extensions " |
| 834 | "(defaults to same as 'secure')"); |
| 835 | |
| 836 | } |
| 837 | |
| 838 | static const TypeInfo vexpress_info = { |
| 839 | .name = TYPE_VEXPRESS_MACHINE, |
| 840 | .parent = TYPE_MACHINE, |
| 841 | .abstract = true, |
| 842 | .instance_size = sizeof(VexpressMachineState), |
| 843 | .instance_init = vexpress_instance_init, |
| 844 | .class_size = sizeof(VexpressMachineClass), |
| 845 | .class_init = vexpress_class_init, |
| 846 | }; |
| 847 | |
| 848 | static const TypeInfo vexpress_a9_info = { |
| 849 | .name = TYPE_VEXPRESS_A9_MACHINE, |
| 850 | .parent = TYPE_VEXPRESS_MACHINE, |
| 851 | .class_init = vexpress_a9_class_init, |
| 852 | .instance_init = vexpress_a9_instance_init, |
| 853 | .interfaces = arm_machine_interfaces, |
| 854 | }; |
| 855 | |
| 856 | static const TypeInfo vexpress_a15_info = { |
| 857 | .name = TYPE_VEXPRESS_A15_MACHINE, |
| 858 | .parent = TYPE_VEXPRESS_MACHINE, |
| 859 | .class_init = vexpress_a15_class_init, |
| 860 | .instance_init = vexpress_a15_instance_init, |
| 861 | .interfaces = arm_machine_interfaces, |
| 862 | }; |
| 863 | |
| 864 | static void vexpress_machine_init(void) |
| 865 | { |
| 866 | type_register_static(&vexpress_info); |
| 867 | type_register_static(&vexpress_a9_info); |
| 868 | type_register_static(&vexpress_a15_info); |
| 869 | } |
| 870 | |
| 871 | type_init(vexpress_machine_init); |