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1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "qemu/error-report.h"
33 #include "trace.h"
34 #include "hw/core/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/pcihp.h"
38 #include "hw/nvram/fw_cfg_acpi.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/aml-build.h"
41 #include "hw/acpi/utils.h"
42 #include "hw/acpi/pci.h"
43 #include "hw/acpi/cxl.h"
44 #include "hw/acpi/memory_hotplug.h"
45 #include "hw/acpi/generic_event_device.h"
46 #include "hw/acpi/tpm.h"
47 #include "hw/acpi/hmat.h"
48 #include "hw/arm/smmuv3.h"
49 #include "hw/cxl/cxl.h"
50 #include "hw/pci/pcie_host.h"
51 #include "hw/pci/pci.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/gpex.h"
54 #include "hw/arm/virt.h"
55 #include "hw/intc/arm_gicv3_its_common.h"
56 #include "hw/mem/nvdimm.h"
57 #include "hw/core/platform-bus.h"
58 #include "system/numa.h"
59 #include "system/reset.h"
60 #include "system/tpm.h"
61 #include "migration/vmstate.h"
62 #include "hw/acpi/ghes.h"
63 #include "hw/acpi/viot.h"
64 #include "hw/virtio/virtio-acpi.h"
65 #include "target/arm/cpu.h"
66 #include "target/arm/multiprocessing.h"
67 #include "hw/watchdog/sbsa_gwdt.h"
68 #include "hw/acpi/wdat-gwdt.h"
69
70 #include "smmuv3-accel.h"
71 #include "tegra241-cmdqv.h"
72
73 #define ARM_SPI_BASE 32
74
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
76
77 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
78 {
79 MachineState *ms = MACHINE(vms);
80 uint16_t i;
81
82 for (i = 0; i < ms->smp.cpus; i++) {
83 Aml *dev = aml_device("C%.03X", i);
84 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
85 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
86 aml_append(scope, dev);
87 }
88 }
89
90 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
91 uint32_t uart_irq, int uartidx)
92 {
93 Aml *dev = aml_device("COM%d", uartidx);
94 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
95 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx)));
96
97 Aml *crs = aml_resource_template();
98 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
99 uart_memmap->size, AML_READ_WRITE));
100 aml_append(crs,
101 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
102 AML_EXCLUSIVE, &uart_irq, 1));
103 aml_append(dev, aml_name_decl("_CRS", crs));
104
105 aml_append(scope, dev);
106 }
107
108 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
109 {
110 Aml *dev, *crs;
111 hwaddr base = flash_memmap->base;
112 hwaddr size = flash_memmap->size / 2;
113
114 dev = aml_device("FLS0");
115 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
116 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
117
118 crs = aml_resource_template();
119 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
120 aml_append(dev, aml_name_decl("_CRS", crs));
121 aml_append(scope, dev);
122
123 dev = aml_device("FLS1");
124 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
125 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
126 crs = aml_resource_template();
127 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
128 aml_append(dev, aml_name_decl("_CRS", crs));
129 aml_append(scope, dev);
130 }
131
132 static void build_acpi0017(Aml *table)
133 {
134 Aml *dev, *scope, *method;
135
136 scope = aml_scope("_SB");
137 dev = aml_device("CXLM");
138 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
139
140 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
141 aml_append(method, aml_return(aml_int(0x0B)));
142 aml_append(dev, method);
143 build_cxl_dsm_method(dev);
144
145 aml_append(scope, dev);
146 aml_append(table, scope);
147 }
148
149 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
150 uint32_t irq, VirtMachineState *vms)
151 {
152 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
153 bool cxl_present = false;
154 PCIBus *bus;
155 bool acpi_pcihp = false;
156
157 if (vms->acpi_dev) {
158 acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
159 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
160 NULL);
161 }
162
163 struct GPEXConfig cfg = {
164 .mmio32 = memmap[VIRT_PCIE_MMIO],
165 .pio = memmap[VIRT_PCIE_PIO],
166 .ecam = memmap[ecam_id],
167 .irq = irq,
168 .bus = vms->bus,
169 .pci_native_hotplug = !acpi_pcihp,
170 };
171
172 /*
173 * Accel SMMU requires RMRs for MSI 1-1 mapping, which require _DSM
174 * function 5 (_DSM for Preserving PCI Boot Configurations).
175 */
176 if (vms->pci_preserve_config) {
177 cfg.preserve_config = true;
178 }
179
180 if (vms->highmem_mmio) {
181 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
182 }
183
184 acpi_dsdt_add_gpex(scope, &cfg);
185 QLIST_FOREACH(bus, &vms->bus->child, sibling) {
186 if (pci_bus_is_cxl(bus)) {
187 cxl_present = true;
188 }
189 }
190 if (cxl_present) {
191 build_acpi0017(scope);
192 }
193 }
194
195 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
196 uint32_t gpio_irq)
197 {
198 Aml *dev = aml_device("GPO0");
199 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
200 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
201
202 Aml *crs = aml_resource_template();
203 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
204 AML_READ_WRITE));
205 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
206 AML_EXCLUSIVE, &gpio_irq, 1));
207 aml_append(dev, aml_name_decl("_CRS", crs));
208
209 Aml *aei = aml_resource_template();
210
211 const uint32_t pin = GPIO_PIN_POWER_BUTTON;
212 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
213 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1,
214 "GPO0", NULL, 0));
215 aml_append(dev, aml_name_decl("_AEI", aei));
216
217 /* _E03 is handle for power button */
218 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
219 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
220 aml_int(0x80)));
221 aml_append(dev, method);
222 aml_append(scope, dev);
223 }
224
225 #ifdef CONFIG_TPM
226 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
227 {
228 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
229 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
230 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
231 MemoryRegion *sbdev_mr;
232 hwaddr tpm_base;
233
234 if (!sbdev) {
235 return;
236 }
237
238 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
239 assert(tpm_base != -1);
240
241 tpm_base += pbus_base;
242
243 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
244
245 Aml *dev = aml_device("TPM0");
246 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
247 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
248 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
249 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
250
251 Aml *crs = aml_resource_template();
252 aml_append(crs,
253 aml_memory32_fixed(tpm_base,
254 (uint32_t)memory_region_size(sbdev_mr),
255 AML_READ_WRITE));
256 aml_append(dev, aml_name_decl("_CRS", crs));
257
258 hwaddr ppi_base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
259 if (ppi_base != -1) {
260 ppi_base += pbus_base;
261 tpm_build_ppi_acpi(TPM_IF(sbdev), dev, ppi_base);
262 }
263 aml_append(scope, dev);
264 }
265 #endif
266
267 #define ID_MAPPING_ENTRY_SIZE 20
268 #define SMMU_V3_ENTRY_SIZE 68
269 #define ROOT_COMPLEX_ENTRY_SIZE 36
270 #define IORT_NODE_OFFSET 48
271
272 #define IORT_RMR_NUM_ID_MAPPINGS 1
273 #define IORT_RMR_NUM_MEM_RANGE_DESC 1
274 #define IORT_RMR_COMMON_HEADER_SIZE 28
275 #define IORT_RMR_MEM_RANGE_DESC_SIZE 20
276
277 /*
278 * IORT RMR flags:
279 * Bit[0] = 0 Disallow remapping of reserved ranges
280 * Bit[1] = 0 Unprivileged access
281 * Bits[9:2] = 0x00 Device nGnRnE memory
282 */
283 #define IORT_RMR_FLAGS 0
284
285 /*
286 * MSI doorbell IOVA window used by the host kernel SMMUv3 driver.
287 * Described in IORT RMR nodes to reserve the IOVA range where the host
288 * kernel maps physical MSI doorbells for devices. This ensures guests
289 * preserve a flat mapping for MSI doorbell in nested SMMUv3(accel=on)
290 * configurations.
291 */
292 #define MSI_IOVA_BASE 0x8000000
293 #define MSI_IOVA_LENGTH 0x100000
294
295 /*
296 * Append an ID mapping entry as described by "Table 4 ID mapping format" in
297 * "IO Remapping Table System Software on ARM Platforms", Chapter 3.
298 * Document number: ARM DEN 0049E.f, Apr 2024
299 *
300 * Note that @id_count gets internally subtracted by one, following the spec.
301 */
302 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
303 uint32_t id_count, uint32_t out_ref,
304 uint32_t flags)
305 {
306 build_append_int_noprefix(table_data, input_base, 4); /* Input base */
307 /* Number of IDs - The number of IDs in the range minus one */
308 build_append_int_noprefix(table_data, id_count - 1, 4);
309 build_append_int_noprefix(table_data, input_base, 4); /* Output base */
310 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
311 /* Flags */
312 build_append_int_noprefix(table_data, flags, 4);
313 }
314
315 struct AcpiIortIdMapping {
316 uint32_t input_base;
317 uint32_t id_count;
318 };
319 typedef struct AcpiIortIdMapping AcpiIortIdMapping;
320
321 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
322 static int
323 iort_host_bridges(Object *obj, void *opaque)
324 {
325 GArray *idmap_blob = opaque;
326
327 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
328 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
329
330 if (bus && !pci_bus_bypass_iommu(bus)) {
331 int min_bus, max_bus;
332
333 pci_bus_range(bus, &min_bus, &max_bus);
334
335 AcpiIortIdMapping idmap = {
336 .input_base = min_bus << 8,
337 .id_count = (max_bus - min_bus + 1) << 8,
338 };
339 g_array_append_val(idmap_blob, idmap);
340 }
341 }
342
343 return 0;
344 }
345
346 static int iort_idmap_compare(gconstpointer a, gconstpointer b)
347 {
348 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
349 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
350
351 return idmap_a->input_base - idmap_b->input_base;
352 }
353
354 typedef struct AcpiIortSMMUv3Dev {
355 int irq;
356 hwaddr base;
357 uint8_t id;
358 GArray *rc_smmu_idmaps;
359 /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */
360 size_t offset;
361 bool accel;
362 bool ats;
363 } AcpiIortSMMUv3Dev;
364
365 /*
366 * Populate the struct AcpiIortSMMUv3Dev for the legacy SMMUv3 and
367 * return the total number of associated idmaps.
368 */
369 static int populate_smmuv3_legacy_dev(GArray *sdev_blob)
370 {
371 VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
372 AcpiIortSMMUv3Dev sdev = {0};
373
374 sdev.rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
375 object_child_foreach_recursive(object_get_root(), iort_host_bridges,
376 sdev.rc_smmu_idmaps);
377 /*
378 * There can be only one legacy SMMUv3("iommu=smmuv3") as it is a machine
379 * wide one. Since it may cover multiple PCIe RCs(based on "bypass_iommu"
380 * property), may have multiple SMMUv3 idmaps. Sort it by input_base.
381 */
382 g_array_sort(sdev.rc_smmu_idmaps, iort_idmap_compare);
383
384 sdev.base = vms->memmap[VIRT_SMMU].base;
385 sdev.irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
386 g_array_append_val(sdev_blob, sdev);
387 return sdev.rc_smmu_idmaps->len;
388 }
389
390 static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b)
391 {
392 AcpiIortSMMUv3Dev *sdev_a = (AcpiIortSMMUv3Dev *)a;
393 AcpiIortSMMUv3Dev *sdev_b = (AcpiIortSMMUv3Dev *)b;
394 AcpiIortIdMapping *map_a = &g_array_index(sdev_a->rc_smmu_idmaps,
395 AcpiIortIdMapping, 0);
396 AcpiIortIdMapping *map_b = &g_array_index(sdev_b->rc_smmu_idmaps,
397 AcpiIortIdMapping, 0);
398 return map_a->input_base - map_b->input_base;
399 }
400
401 /*
402 * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and
403 * return the total number of idmaps.
404 */
405 static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob)
406 {
407 for (int i = 0; i < vms->smmuv3_devices->len; i++) {
408 Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));
409 AcpiIortSMMUv3Dev sdev = {0};
410 AcpiIortIdMapping idmap;
411 PlatformBusDevice *pbus;
412 int min_bus, max_bus;
413 SysBusDevice *sbdev;
414 PCIBus *bus;
415
416 bus = PCI_BUS(object_property_get_link(obj, "primary-bus",
417 &error_abort));
418 sdev.accel = object_property_get_bool(obj, "accel", &error_abort);
419 sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));
420 sdev.id = object_property_get_uint(obj, "identifier", &error_abort);
421 pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
422 sbdev = SYS_BUS_DEVICE(obj);
423 sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
424 sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;
425 sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);
426 sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];
427 sdev.irq += ARM_SPI_BASE;
428
429 pci_bus_range(bus, &min_bus, &max_bus);
430 sdev.rc_smmu_idmaps = g_array_new(false, true,
431 sizeof(AcpiIortIdMapping));
432 idmap.input_base = min_bus << 8;
433 idmap.id_count = (max_bus - min_bus + 1) << 8;
434 g_array_append_val(sdev.rc_smmu_idmaps, idmap);
435 g_array_append_val(sdev_blob, sdev);
436 }
437 /* Sort the smmuv3 devices(if any) by smmu idmap input_base */
438 g_array_sort(sdev_blob, smmuv3_dev_idmap_compare);
439 /*
440 * Since each SMMUv3 dev is assocaited with specific host bridge,
441 * total number of idmaps equals to total number of smmuv3 devices.
442 */
443 return sdev_blob->len;
444 }
445
446 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group node */
447 static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmuv3_devs)
448 {
449 AcpiIortIdMapping *idmap;
450 AcpiIortIdMapping next_range = {0};
451 AcpiIortSMMUv3Dev *sdev;
452
453 for (int i = 0; i < smmuv3_devs->len; i++) {
454 sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i);
455 /*
456 * Based on the RID ranges that are directed to the SMMU, determine the
457 * bypassed RID ranges, i.e., the ones that are directed to the ITS
458 * Group node and do not pass through the SMMU, by subtracting the
459 * SMMU-bound ranges from the full RID range (0x0000–0xFFFF).
460 */
461 for (int j = 0; j < sdev->rc_smmu_idmaps->len; j++) {
462 idmap = &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMapping, j);
463
464 if (next_range.input_base < idmap->input_base) {
465 next_range.id_count = idmap->input_base - next_range.input_base;
466 g_array_append_val(its_idmaps, next_range);
467 }
468
469 next_range.input_base = idmap->input_base + idmap->id_count;
470 }
471 }
472 /*
473 * Append the last RC -> ITS ID mapping.
474 *
475 * RIDs are 16-bit, according to the PCI Express 2.0 Base Specification, rev
476 * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Field",
477 * hence the end of the range is 0x10000.
478 */
479 if (next_range.input_base < 0x10000) {
480 next_range.id_count = 0x10000 - next_range.input_base;
481 g_array_append_val(its_idmaps, next_range);
482 }
483 }
484
485 static void
486 build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3_devices, uint32_t *id)
487 {
488 AcpiIortSMMUv3Dev *sdev;
489 AcpiIortIdMapping *idmap;
490 int i;
491
492 for (i = 0; i < smmuv3_devices->len; i++) {
493 uint16_t rmr_len;
494 int bdf;
495
496 sdev = &g_array_index(smmuv3_devices, AcpiIortSMMUv3Dev, i);
497 if (!sdev->accel) {
498 continue;
499 }
500
501 /*
502 * Spec reference:Arm IO Remapping Table(IORT), ARM DEN 0049E.d,
503 * Section 3.1.1.5 "Reserved Memory Range node"
504 */
505 idmap = &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMapping, 0);
506 bdf = idmap->input_base;
507 rmr_len = IORT_RMR_COMMON_HEADER_SIZE
508 + (IORT_RMR_NUM_ID_MAPPINGS * ID_MAPPING_ENTRY_SIZE)
509 + (IORT_RMR_NUM_MEM_RANGE_DESC * IORT_RMR_MEM_RANGE_DESC_SIZE);
510
511 /* Table 18 Reserved Memory Range Node */
512 build_append_int_noprefix(table_data, 6 /* RMR */, 1); /* Type */
513 /* Length */
514 build_append_int_noprefix(table_data, rmr_len, 2);
515 build_append_int_noprefix(table_data, 3, 1); /* Revision */
516 build_append_int_noprefix(table_data, (*id)++, 4); /* Identifier */
517 /* Number of ID mappings */
518 build_append_int_noprefix(table_data, IORT_RMR_NUM_ID_MAPPINGS, 4);
519 /* Reference to ID Array */
520 build_append_int_noprefix(table_data, IORT_RMR_COMMON_HEADER_SIZE, 4);
521
522 /* RMR specific data */
523
524 /* Flags */
525 build_append_int_noprefix(table_data, IORT_RMR_FLAGS, 4);
526 /* Number of Memory Range Descriptors */
527 build_append_int_noprefix(table_data, IORT_RMR_NUM_MEM_RANGE_DESC, 4);
528 /* Reference to Memory Range Descriptors */
529 build_append_int_noprefix(table_data, IORT_RMR_COMMON_HEADER_SIZE +
530 (IORT_RMR_NUM_ID_MAPPINGS * ID_MAPPING_ENTRY_SIZE), 4);
531 build_iort_id_mapping(table_data, bdf, idmap->id_count, sdev->offset,
532 1);
533
534 /* Table 19 Memory Range Descriptor */
535
536 /* Physical Range offset */
537 build_append_int_noprefix(table_data, MSI_IOVA_BASE, 8);
538 /* Physical Range length */
539 build_append_int_noprefix(table_data, MSI_IOVA_LENGTH, 8);
540 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
541 }
542 }
543
544 /*
545 * Input Output Remapping Table (IORT)
546 * Conforms to "IO Remapping Table System Software on ARM Platforms",
547 * Document number: ARM DEN 0049E.d, Feb 2022
548 */
549 static void
550 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
551 {
552 int i, nb_nodes, rc_mapping_count;
553 AcpiIortSMMUv3Dev *sdev;
554 size_t node_size;
555 bool ats_needed = false;
556 int num_smmus = 0;
557 uint32_t id = 0;
558 int rc_smmu_idmaps_len = 0;
559 GArray *smmuv3_devs = g_array_new(false, true, sizeof(AcpiIortSMMUv3Dev));
560 GArray *rc_its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
561
562 AcpiTable table = { .sig = "IORT", .rev = 5, .oem_id = vms->oem_id,
563 .oem_table_id = vms->oem_table_id };
564 /* Table 2 The IORT */
565 acpi_table_begin(&table, table_data);
566
567 if (vms->legacy_smmuv3_present) {
568 rc_smmu_idmaps_len = populate_smmuv3_legacy_dev(smmuv3_devs);
569 } else {
570 rc_smmu_idmaps_len = populate_smmuv3_dev(vms, smmuv3_devs);
571 }
572
573 num_smmus = smmuv3_devs->len;
574 if (num_smmus) {
575 nb_nodes = num_smmus + 1; /* RC and SMMUv3 */
576 rc_mapping_count = rc_smmu_idmaps_len;
577
578 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
579 /*
580 * Knowing the ID ranges from the RC to the SMMU, it's possible to
581 * determine the ID ranges from RC that go directly to ITS.
582 */
583 create_rc_its_idmaps(rc_its_idmaps, smmuv3_devs);
584
585 nb_nodes++; /* ITS */
586 rc_mapping_count += rc_its_idmaps->len;
587 }
588 /* Calculate RMR nodes required. One per SMMUv3 with accelerated mode */
589 for (i = 0; i < num_smmus; i++) {
590 sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i);
591 if (sdev->ats) {
592 ats_needed = true;
593 }
594 if (sdev->accel) {
595 nb_nodes++;
596 }
597 }
598 } else {
599 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
600 nb_nodes = 2; /* RC and ITS */
601 rc_mapping_count = 1; /* Direct map to ITS */
602 } else {
603 nb_nodes = 1; /* RC only */
604 rc_mapping_count = 0; /* No output mapping */
605 }
606 }
607 /* Number of IORT Nodes */
608 build_append_int_noprefix(table_data, nb_nodes, 4);
609
610 /* Offset to Array of IORT Nodes */
611 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
612 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
613
614 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
615 /* Table 12 ITS Group Format */
616 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
617 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
618 build_append_int_noprefix(table_data, node_size, 2); /* Length */
619 build_append_int_noprefix(table_data, 1, 1); /* Revision */
620 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
621 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
622 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
623 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
624 /* GIC ITS Identifier Array */
625 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
626 }
627
628 for (i = 0; i < num_smmus; i++) {
629 sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i);
630 int smmu_mapping_count, offset_to_id_array;
631 int irq = sdev->irq;
632
633 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
634 smmu_mapping_count = 1; /* ITS Group node */
635 offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */
636 } else {
637 smmu_mapping_count = 0; /* No ID mappings */
638 offset_to_id_array = 0; /* No ID mappings array */
639 }
640 sdev->offset = table_data->len - table.table_offset;
641 /* Table 9 SMMUv3 Format */
642 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
643 node_size = SMMU_V3_ENTRY_SIZE +
644 (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count);
645 build_append_int_noprefix(table_data, node_size, 2); /* Length */
646 build_append_int_noprefix(table_data, 4, 1); /* Revision */
647 build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier */
648 id++; /* advance shared counter for RC/RMR node uniqueness */
649 /* Number of ID mappings */
650 build_append_int_noprefix(table_data, smmu_mapping_count, 4);
651 /* Reference to ID Array */
652 build_append_int_noprefix(table_data, offset_to_id_array, 4);
653 /* Base address */
654 build_append_int_noprefix(table_data, sdev->base, 8);
655 /* Flags */
656 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
657 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
658 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
659 /* Model */
660 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
661 build_append_int_noprefix(table_data, irq, 4); /* Event */
662 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
663 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
664 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
665 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
666 /* DeviceID mapping index (ignored since interrupts are GSIV based) */
667 build_append_int_noprefix(table_data, 0, 4);
668 /* Array of ID mappings */
669 if (smmu_mapping_count) {
670 /* Output IORT node is the ITS Group node (the first node). */
671 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0);
672 }
673 }
674
675 /* Table 17 Root Complex Node */
676 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
677 node_size = ROOT_COMPLEX_ENTRY_SIZE +
678 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
679 build_append_int_noprefix(table_data, node_size, 2); /* Length */
680 build_append_int_noprefix(table_data, 3, 1); /* Revision */
681 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
682 /* Number of ID mappings */
683 build_append_int_noprefix(table_data, rc_mapping_count, 4);
684 /* Reference to ID Array */
685 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
686
687 /* Table 14 Memory access properties */
688 /* CCA: Cache Coherent Attribute */
689 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
690 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
691 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
692 /* Table 15 Memory Access Flags */
693 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
694 /* ATS Attribute */
695 build_append_int_noprefix(table_data, ats_needed, 4);
696 /* MCFG pci_segment */
697 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
698
699 /* Memory address size limit */
700 build_append_int_noprefix(table_data, 64, 1);
701
702 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
703
704 /* Output Reference */
705 if (num_smmus) {
706 AcpiIortIdMapping *range;
707
708 for (i = 0; i < num_smmus; i++) {
709 sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i);
710
711 /*
712 * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3.
713 *
714 * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS)
715 * is defined in the SMMUv3 table, where all SMMUv3 IDs are mapped
716 * to the ITS Group node, if ITS is available.
717 */
718 for (int j = 0; j < sdev->rc_smmu_idmaps->len; j++) {
719 range = &g_array_index(sdev->rc_smmu_idmaps,
720 AcpiIortIdMapping, j);
721 /* Output IORT node is the SMMUv3 node. */
722 build_iort_id_mapping(table_data, range->input_base,
723 range->id_count, sdev->offset, 0);
724 }
725 }
726
727 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
728 /*
729 * Map bypassed (don't go through the SMMU) RIDs (input) to
730 * ITS Group node directly: RC -> ITS.
731 */
732 for (i = 0; i < rc_its_idmaps->len; i++) {
733 range = &g_array_index(rc_its_idmaps, AcpiIortIdMapping, i);
734 /* Output IORT node is the ITS Group node (the first node). */
735 build_iort_id_mapping(table_data, range->input_base,
736 range->id_count, IORT_NODE_OFFSET, 0);
737 }
738 }
739 } else {
740 /*
741 * Map all RIDs (input) to ITS Group node directly, since there is no
742 * SMMU: RC -> ITS.
743 * Output IORT node is the ITS Group node (the first node).
744 */
745 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
746 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0);
747 }
748 }
749
750 build_iort_rmr_nodes(table_data, smmuv3_devs, &id);
751 acpi_table_end(linker, &table);
752 g_array_free(rc_its_idmaps, true);
753 for (i = 0; i < num_smmus; i++) {
754 sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i);
755 g_array_free(sdev->rc_smmu_idmaps, true);
756 }
757 g_array_free(smmuv3_devs, true);
758 }
759
760 /*
761 * Serial Port Console Redirection Table (SPCR)
762 * Rev: 1.07
763 */
764 static void
765 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
766 {
767 AcpiSpcrData serial = {
768 .interface_type = 3, /* ARM PL011 UART */
769 .base_addr.id = AML_AS_SYSTEM_MEMORY,
770 .base_addr.width = 32,
771 .base_addr.offset = 0,
772 .base_addr.size = 3,
773 .base_addr.addr = vms->memmap[VIRT_UART0].base,
774 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
775 .pc_interrupt = 0, /* IRQ */
776 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE),
777 .baud_rate = 3, /* 9600 */
778 .parity = 0, /* No Parity */
779 .stop_bits = 1, /* 1 Stop bit */
780 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
781 .terminal_type = 0, /* VT100 */
782 .language = 0, /* Language */
783 .pci_device_id = 0xffff, /* not a PCI device*/
784 .pci_vendor_id = 0xffff, /* not a PCI device*/
785 .pci_bus = 0,
786 .pci_device = 0,
787 .pci_function = 0,
788 .pci_flags = 0,
789 .pci_segment = 0,
790 };
791 /*
792 * Passing NULL as the SPCR Table for Revision 2 doesn't support
793 * NameSpaceString.
794 */
795 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
796 NULL);
797 }
798
799 /*
800 * ACPI spec, Revision 5.1
801 * 5.2.16 System Resource Affinity Table (SRAT)
802 */
803 static void
804 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
805 {
806 int i;
807 uint64_t mem_base;
808 MachineClass *mc = MACHINE_GET_CLASS(vms);
809 MachineState *ms = MACHINE(vms);
810 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
811 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
812 .oem_table_id = vms->oem_table_id };
813
814 acpi_table_begin(&table, table_data);
815 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
816 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
817
818 for (i = 0; i < cpu_list->len; ++i) {
819 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
820 /*
821 * 5.2.16.4 GICC Affinity Structure
822 */
823 build_append_int_noprefix(table_data, 3, 1); /* Type */
824 build_append_int_noprefix(table_data, 18, 1); /* Length */
825 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
826 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
827 /* Flags, Table 5-76 */
828 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
829 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
830 }
831
832 mem_base = vms->memmap[VIRT_MEM].base;
833 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
834 if (ms->numa_state->nodes[i].node_mem > 0) {
835 build_srat_memory(table_data, mem_base,
836 ms->numa_state->nodes[i].node_mem, i,
837 MEM_AFFINITY_ENABLED);
838 mem_base += ms->numa_state->nodes[i].node_mem;
839 }
840 }
841
842 build_srat_generic_affinity_structures(table_data);
843
844 if (ms->nvdimms_state->is_enabled) {
845 nvdimm_build_srat(table_data);
846 }
847
848 if (ms->device_memory) {
849 build_srat_memory(table_data, ms->device_memory->base,
850 memory_region_size(&ms->device_memory->mr),
851 ms->numa_state->num_nodes - 1,
852 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
853 }
854
855 acpi_table_end(linker, &table);
856 }
857
858 /*
859 * ACPI spec, Revision 6.5
860 * 5.2.25 Generic Timer Description Table (GTDT)
861 */
862 static void
863 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms,
864 bool add_watchdog)
865 {
866 /*
867 * Table 5-117 Flag Definitions
868 * set only "Timer interrupt Mode" and assume "Timer Interrupt
869 * polarity" bit as '0: Interrupt is Active high'
870 */
871 const uint32_t irqflags = 0; /* Interrupt is Level triggered */
872 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
873 .oem_table_id = vms->oem_table_id };
874 uint32_t gtdt_start = table_data->len;
875
876 acpi_table_begin(&table, table_data);
877
878 /* CntControlBase Physical Address */
879 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
880 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
881 /*
882 * FIXME: clarify comment:
883 * The interrupt values are the same with the device tree when adding 16
884 */
885 /* Secure EL1 timer GSIV */
886 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
887 /* Secure EL1 timer Flags */
888 build_append_int_noprefix(table_data, irqflags, 4);
889 /* Non-Secure EL1 timer GSIV */
890 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
891 /* Non-Secure EL1 timer Flags */
892 build_append_int_noprefix(table_data, irqflags |
893 1UL << 2, /* Always-on Capability */
894 4);
895 /* Virtual timer GSIV */
896 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
897 /* Virtual Timer Flags */
898 build_append_int_noprefix(table_data, irqflags, 4);
899 /* Non-Secure EL2 timer GSIV */
900 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
901 /* Non-Secure EL2 timer Flags */
902 build_append_int_noprefix(table_data, irqflags, 4);
903 /* CntReadBase Physical address */
904 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
905
906 /* Platform Timer Count */
907 build_append_int_noprefix(table_data, add_watchdog ? 1 : 0, 4);
908 /* Platform Timer Offset */
909 build_append_int_noprefix(table_data,
910 add_watchdog ? (table_data->len - gtdt_start) +
911 4 + 4 + 4 /* len of this & following 2 fields to skip */
912 : 0, 4);
913
914 if (vms->ns_el2_virt_timer_irq) {
915 /* Virtual EL2 Timer GSIV */
916 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
917 /* Virtual EL2 Timer Flags */
918 build_append_int_noprefix(table_data, irqflags, 4);
919 } else {
920 build_append_int_noprefix(table_data, 0, 4);
921 build_append_int_noprefix(table_data, 0, 4);
922 }
923
924 /* ACPI 6.5 spec: 5.2.25.2 ARM Generic Watchdog Structure (Table 5-124) */
925 if (add_watchdog) {
926 hwaddr rbase = vms->memmap[VIRT_GWDT_REFRESH].base;
927 hwaddr cbase = vms->memmap[VIRT_GWDT_CONTROL].base;
928 int irq = ARM_SPI_BASE + vms->irqmap[VIRT_GWDT_WS0];
929
930 build_append_int_noprefix(table_data, 1 /* Type: Watchdog GT */, 1);
931 build_append_int_noprefix(table_data, 28 /* Length */, 2);
932 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
933 /* RefreshFrame Physical Address */
934 build_append_int_noprefix(table_data, rbase, 8);
935 /* WatchdogControlFrame Physical Address */
936 build_append_int_noprefix(table_data, cbase, 8);
937 build_append_int_noprefix(table_data, irq, 4); /* Watchdog Timer GSIV */
938 build_append_int_noprefix(table_data, 0, 4); /* Watchdog Timer Flags */
939 }
940 acpi_table_end(linker, &table);
941 }
942
943 /* Debug Port Table 2 (DBG2) */
944 static void
945 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
946 {
947 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
948 .oem_table_id = vms->oem_table_id };
949 int dbg2devicelength;
950 const char name[] = "COM0";
951 const int namespace_length = sizeof(name);
952
953 acpi_table_begin(&table, table_data);
954
955 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
956 12 + /* BaseAddressRegister[] */
957 4 + /* AddressSize[] */
958 namespace_length /* NamespaceString[] */;
959
960 /* OffsetDbgDeviceInfo */
961 build_append_int_noprefix(table_data, 44, 4);
962 /* NumberDbgDeviceInfo */
963 build_append_int_noprefix(table_data, 1, 4);
964
965 /* Table 2. Debug Device Information structure format */
966 build_append_int_noprefix(table_data, 0, 1); /* Revision */
967 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
968 /* NumberofGenericAddressRegisters */
969 build_append_int_noprefix(table_data, 1, 1);
970 /* NameSpaceStringLength */
971 build_append_int_noprefix(table_data, namespace_length, 2);
972 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
973 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
974 /* OemDataOffset (0 means no OEM data) */
975 build_append_int_noprefix(table_data, 0, 2);
976
977 /* Port Type */
978 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
979 /* Port Subtype */
980 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
981 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
982 /* BaseAddressRegisterOffset */
983 build_append_int_noprefix(table_data, 22, 2);
984 /* AddressSizeOffset */
985 build_append_int_noprefix(table_data, 34, 2);
986
987 /* BaseAddressRegister[] */
988 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
989 vms->memmap[VIRT_UART0].base);
990
991 /* AddressSize[] */
992 build_append_int_noprefix(table_data,
993 vms->memmap[VIRT_UART0].size, 4);
994
995 /* NamespaceString[] */
996 g_array_append_vals(table_data, name, namespace_length);
997
998 acpi_table_end(linker, &table);
999 };
1000
1001 /*
1002 * ACPI spec, Revision 6.0 Errata A
1003 * 5.2.12 Multiple APIC Description Table (MADT)
1004 */
1005 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
1006 {
1007 build_append_int_noprefix(table_data, 0xE, 1); /* Type */
1008 build_append_int_noprefix(table_data, 16, 1); /* Length */
1009 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1010 /* Discovery Range Base Address */
1011 build_append_int_noprefix(table_data, base, 8);
1012 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
1013 }
1014
1015 static void
1016 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
1017 {
1018 int i;
1019 const MemMapEntry *memmap = vms->memmap;
1020 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
1021 .oem_table_id = vms->oem_table_id };
1022
1023 acpi_table_begin(&table, table_data);
1024 /* Local Interrupt Controller Address */
1025 build_append_int_noprefix(table_data, 0, 4);
1026 build_append_int_noprefix(table_data, 0, 4); /* Flags */
1027
1028 /* 5.2.12.15 GIC Distributor Structure */
1029 build_append_int_noprefix(table_data, 0xC, 1); /* Type */
1030 build_append_int_noprefix(table_data, 24, 1); /* Length */
1031 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1032 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
1033 /* Physical Base Address */
1034 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
1035 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
1036 /* GIC version */
1037 build_append_int_noprefix(table_data, vms->gic_version, 1);
1038 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
1039
1040 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
1041 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
1042 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
1043 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
1044 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
1045 VIRTUAL_PMU_IRQ : 0;
1046
1047 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1048 physical_base_address = memmap[VIRT_GIC_CPU].base;
1049 gicv = memmap[VIRT_GIC_VCPU].base;
1050 gich = memmap[VIRT_GIC_HYP].base;
1051 }
1052
1053 /* 5.2.12.14 GIC Structure */
1054 build_append_int_noprefix(table_data, 0xB, 1); /* Type */
1055 build_append_int_noprefix(table_data, 80, 1); /* Length */
1056 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1057 build_append_int_noprefix(table_data, i, 4); /* GIC ID */
1058 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
1059 /* Flags */
1060 build_append_int_noprefix(table_data, 1, 4); /* Enabled */
1061 /* Parking Protocol Version */
1062 build_append_int_noprefix(table_data, 0, 4);
1063 /* Performance Interrupt GSIV */
1064 build_append_int_noprefix(table_data, pmu_interrupt, 4);
1065 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
1066 /* Physical Base Address */
1067 build_append_int_noprefix(table_data, physical_base_address, 8);
1068 build_append_int_noprefix(table_data, gicv, 8); /* GICV */
1069 build_append_int_noprefix(table_data, gich, 8); /* GICH */
1070 /* VGIC Maintenance interrupt */
1071 build_append_int_noprefix(table_data, vgic_interrupt, 4);
1072 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
1073 /* MPIDR */
1074 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
1075 /* Processor Power Efficiency Class */
1076 build_append_int_noprefix(table_data, 0, 1);
1077 /* Reserved */
1078 build_append_int_noprefix(table_data, 0, 3);
1079 }
1080
1081 if (vms->gic_version != VIRT_GIC_VERSION_2) {
1082 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
1083 memmap[VIRT_GIC_REDIST].size);
1084 if (virt_gicv3_redist_region_count(vms) == 2) {
1085 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
1086 memmap[VIRT_HIGH_GIC_REDIST2].size);
1087 }
1088
1089 if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
1090 /*
1091 * ACPI spec, Revision 6.0 Errata A
1092 * (original 6.0 definition has invalid Length)
1093 * 5.2.12.18 GIC ITS Structure
1094 */
1095 build_append_int_noprefix(table_data, 0xF, 1); /* Type */
1096 build_append_int_noprefix(table_data, 20, 1); /* Length */
1097 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1098 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
1099 /* Physical Base Address */
1100 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
1101 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1102 }
1103 }
1104
1105 if (vms->msi_controller == VIRT_MSI_CTRL_GICV2M) {
1106 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
1107
1108 /* 5.2.12.16 GIC MSI Frame Structure */
1109 build_append_int_noprefix(table_data, 0xD, 1); /* Type */
1110 build_append_int_noprefix(table_data, 24, 1); /* Length */
1111 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1112 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
1113 /* Physical Base Address */
1114 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
1115 build_append_int_noprefix(table_data, 1, 4); /* Flags */
1116 /* SPI Count */
1117 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
1118 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
1119 }
1120 acpi_table_end(linker, &table);
1121 }
1122
1123 /* FADT */
1124 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
1125 VirtMachineState *vms, unsigned dsdt_tbl_offset)
1126 {
1127 /* ACPI v6.3 */
1128 AcpiFadtData fadt = {
1129 .rev = 6,
1130 .minor_ver = 3,
1131 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
1132 .xdsdt_tbl_offset = &dsdt_tbl_offset,
1133 };
1134
1135 switch (vms->psci_conduit) {
1136 case QEMU_PSCI_CONDUIT_DISABLED:
1137 fadt.arm_boot_arch = 0;
1138 break;
1139 case QEMU_PSCI_CONDUIT_HVC:
1140 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
1141 ACPI_FADT_ARM_PSCI_USE_HVC;
1142 break;
1143 case QEMU_PSCI_CONDUIT_SMC:
1144 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
1145 break;
1146 default:
1147 g_assert_not_reached();
1148 }
1149
1150 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
1151 }
1152
1153 static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms)
1154 {
1155 for (int i = 0; i < vms->smmuv3_devices->len; i++) {
1156 Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));
1157 PlatformBusDevice *pbus;
1158 Aml *dev, *crs, *addr;
1159 SysBusDevice *sbdev;
1160 hwaddr base;
1161 uint32_t id;
1162 int irq;
1163
1164 if (smmuv3_accel_cmdqv_type(obj) != SMMUV3_CMDQV_TEGRA241) {
1165 continue;
1166 }
1167 id = object_property_get_uint(obj, "identifier", &error_abort);
1168 pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
1169 sbdev = SYS_BUS_DEVICE(obj);
1170 base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
1171 base += vms->memmap[VIRT_PLATFORM_BUS].base;
1172 irq = platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS);
1173 irq += vms->irqmap[VIRT_PLATFORM_BUS];
1174 irq += ARM_SPI_BASE;
1175
1176 dev = aml_device("CV%.02u", id);
1177 aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C")));
1178 aml_append(dev, aml_name_decl("_UID", aml_int(id)));
1179 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
1180
1181 crs = aml_resource_template();
1182 addr = aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1183 AML_CACHEABLE, AML_READ_WRITE, 0x0, base,
1184 base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0,
1185 TEGRA241_CMDQV_IO_LEN);
1186 aml_append(crs, addr);
1187 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE,
1188 AML_ACTIVE_HIGH, AML_EXCLUSIVE,
1189 (uint32_t *)&irq, 1));
1190 aml_append(dev, aml_name_decl("_CRS", crs));
1191
1192 aml_append(scope, dev);
1193
1194 trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq);
1195 }
1196 }
1197
1198 /* DSDT */
1199 static void
1200 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
1201 {
1202 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1203 Aml *scope, *dsdt;
1204 MachineState *ms = MACHINE(vms);
1205 const MemMapEntry *memmap = vms->memmap;
1206 const int *irqmap = vms->irqmap;
1207 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
1208 .oem_table_id = vms->oem_table_id };
1209 Aml *pci0_scope;
1210 uint32_t bsel;
1211
1212 acpi_table_begin(&table, table_data);
1213 dsdt = init_aml_allocator();
1214
1215 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
1216 * While UEFI can use libfdt to disable the RTC device node in the DTB that
1217 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
1218 * the RTC ACPI device at all when using UEFI.
1219 */
1220 scope = aml_scope("\\_SB");
1221 acpi_dsdt_add_cpus(scope, vms);
1222 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0],
1223 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0);
1224 if (vms->second_ns_uart_present) {
1225 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1],
1226 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1);
1227 }
1228 if (vmc->acpi_expose_flash) {
1229 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
1230 }
1231 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
1232 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
1233 (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
1234 0, vms->virtio_transports);
1235 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
1236 if (vms->acpi_dev) {
1237 build_ged_aml(scope, "\\_SB."GED_DEVICE,
1238 HOTPLUG_HANDLER(vms->acpi_dev),
1239 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
1240 memmap[VIRT_ACPI_GED].base);
1241 } else {
1242 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
1243 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
1244 }
1245
1246 if (vms->acpi_dev) {
1247 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
1248 "ged-event", &error_abort);
1249
1250 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
1251 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
1252 AML_SYSTEM_MEMORY,
1253 memmap[VIRT_PCDIMM_ACPI].base);
1254 }
1255 }
1256
1257 acpi_dsdt_add_power_button(scope);
1258 aml_append(scope, aml_error_device());
1259 #ifdef CONFIG_TPM
1260 acpi_dsdt_add_tpm(scope, vms);
1261 #endif
1262
1263 if (!vms->legacy_smmuv3_present) {
1264 acpi_dsdt_add_tegra241_cmdqv(scope, vms);
1265 }
1266
1267 aml_append(dsdt, scope);
1268
1269 pci0_scope = aml_scope("\\_SB.PCI0");
1270
1271 aml_append(pci0_scope, build_pci_bridge_edsm());
1272 build_append_pci_bus_devices(pci0_scope, vms->bus);
1273 bsel = object_property_get_uint(OBJECT(vms->bus), ACPI_PCIHP_PROP_BSEL,
1274 &error_abort);
1275 if (bsel != UINT32_MAX) {
1276 build_append_pcihp_slots(pci0_scope, vms->bus);
1277 }
1278
1279 if (vms->acpi_dev) {
1280 bool acpi_pcihp;
1281
1282 acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
1283 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
1284 NULL);
1285
1286 if (acpi_pcihp) {
1287 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_MEMORY,
1288 memmap[VIRT_ACPI_PCIHP].base);
1289 build_append_pcihp_resources(pci0_scope,
1290 memmap[VIRT_ACPI_PCIHP].base,
1291 memmap[VIRT_ACPI_PCIHP].size);
1292
1293 build_append_notification_callback(pci0_scope, vms->bus);
1294 }
1295 }
1296 aml_append(dsdt, pci0_scope);
1297
1298 /* copy AML table into ACPI tables blob */
1299 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1300
1301 acpi_table_end(linker, &table);
1302 free_aml_allocator();
1303 }
1304
1305 typedef
1306 struct AcpiBuildState {
1307 /* Copy of table in RAM (for patching). */
1308 MemoryRegion *table_mr;
1309 MemoryRegion *rsdp_mr;
1310 MemoryRegion *linker_mr;
1311 /* Is table patched? */
1312 bool patched;
1313 } AcpiBuildState;
1314
1315 static void acpi_align_size(GArray *blob, unsigned align)
1316 {
1317 /*
1318 * Align size to multiple of given size. This reduces the chance
1319 * we need to change size in the future (breaking cross version migration).
1320 */
1321 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
1322 }
1323
1324 static const AcpiNotificationSourceId hest_ghes_notify[] = {
1325 { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA },
1326 { ACPI_HEST_SRC_ID_QMP, ACPI_GHES_NOTIFY_GPIO },
1327 };
1328
1329 static const AcpiNotificationSourceId hest_ghes_notify_10_0[] = {
1330 { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA },
1331 };
1332
1333 static
1334 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
1335 {
1336 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1337 GArray *table_offsets;
1338 unsigned dsdt, xsdt;
1339 bool has_wdat = false;
1340 GArray *tables_blob = tables->table_data;
1341 MachineState *ms = MACHINE(vms);
1342 CPUCoreCaches caches[CPU_MAX_CACHES];
1343 unsigned int num_caches;
1344 Object *wdt = object_resolve_type_unambiguous(TYPE_WDT_SBSA, NULL);
1345
1346 num_caches = virt_get_caches(vms, caches);
1347
1348 if (wdt) {
1349 has_wdat = object_property_get_bool(wdt, "wdat", &error_abort);
1350 }
1351
1352 table_offsets = g_array_new(false, true /* clear */,
1353 sizeof(uint32_t));
1354
1355 bios_linker_loader_alloc(tables->linker,
1356 ACPI_BUILD_TABLE_FILE, tables_blob,
1357 64, false /* high memory */);
1358
1359 /* DSDT is pointed to by FADT */
1360 dsdt = tables_blob->len;
1361 build_dsdt(tables_blob, tables->linker, vms);
1362
1363 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
1364 acpi_add_table(table_offsets, tables_blob);
1365 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt);
1366
1367 acpi_add_table(table_offsets, tables_blob);
1368 build_madt(tables_blob, tables->linker, vms);
1369
1370 acpi_add_table(table_offsets, tables_blob);
1371 if (wdt && has_wdat) {
1372 uint64_t freq = object_property_get_uint(wdt, "clock-frequency",
1373 &error_abort);
1374 build_gwdt_wdat(tables_blob, tables->linker,
1375 vms->oem_id, vms->oem_table_id,
1376 vms->memmap[VIRT_GWDT_REFRESH].base,
1377 vms->memmap[VIRT_GWDT_CONTROL].base,
1378 freq);
1379 }
1380
1381 if (!vmc->no_cpu_topology) {
1382 acpi_add_table(table_offsets, tables_blob);
1383 build_pptt(tables_blob, tables->linker, ms, vms->oem_id,
1384 vms->oem_table_id, num_caches, caches);
1385 }
1386
1387 acpi_add_table(table_offsets, tables_blob);
1388 build_gtdt(tables_blob, tables->linker, vms, wdt && !has_wdat);
1389
1390 acpi_add_table(table_offsets, tables_blob);
1391 {
1392 AcpiMcfgInfo mcfg = {
1393 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
1394 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
1395 };
1396 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
1397 vms->oem_table_id);
1398 }
1399
1400 acpi_add_table(table_offsets, tables_blob);
1401
1402 if (ms->acpi_spcr_enabled) {
1403 spcr_setup(tables_blob, tables->linker, vms);
1404 }
1405
1406 acpi_add_table(table_offsets, tables_blob);
1407 build_dbg2(tables_blob, tables->linker, vms);
1408
1409 if (vms->ras) {
1410 AcpiGedState *acpi_ged_state;
1411 static const AcpiNotificationSourceId *notify;
1412 unsigned int notify_sz;
1413 AcpiGhesState *ags;
1414
1415 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1416 ags = &acpi_ged_state->ghes_state;
1417 if (ags) {
1418 acpi_add_table(table_offsets, tables_blob);
1419
1420 if (!ags->use_hest_addr) {
1421 notify = hest_ghes_notify_10_0;
1422 notify_sz = ARRAY_SIZE(hest_ghes_notify_10_0);
1423 } else {
1424 notify = hest_ghes_notify;
1425 notify_sz = ARRAY_SIZE(hest_ghes_notify);
1426 }
1427
1428 acpi_build_hest(ags, tables_blob, tables->hardware_errors,
1429 tables->linker, notify, notify_sz,
1430 vms->oem_id, vms->oem_table_id);
1431 }
1432 }
1433
1434 if (ms->numa_state->num_nodes > 0) {
1435 acpi_add_table(table_offsets, tables_blob);
1436 build_srat(tables_blob, tables->linker, vms);
1437 if (ms->numa_state->have_numa_distance) {
1438 acpi_add_table(table_offsets, tables_blob);
1439 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
1440 vms->oem_table_id);
1441 }
1442
1443 if (ms->numa_state->hmat_enabled) {
1444 acpi_add_table(table_offsets, tables_blob);
1445 build_hmat(tables_blob, tables->linker, ms->numa_state,
1446 vms->oem_id, vms->oem_table_id);
1447 }
1448 }
1449
1450 if (vms->cxl_devices_state.is_enabled) {
1451 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
1452 vms->oem_id, vms->oem_table_id, &vms->cxl_devices_state);
1453 }
1454
1455 if (ms->nvdimms_state->is_enabled) {
1456 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
1457 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
1458 vms->oem_table_id);
1459 }
1460
1461 acpi_add_table(table_offsets, tables_blob);
1462 build_iort(tables_blob, tables->linker, vms);
1463
1464 #ifdef CONFIG_TPM
1465 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
1466 acpi_add_table(table_offsets, tables_blob);
1467 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
1468 vms->oem_table_id);
1469 }
1470 #endif
1471
1472 if (vms->iommu == VIRT_IOMMU_VIRTIO) {
1473 acpi_add_table(table_offsets, tables_blob);
1474 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
1475 vms->oem_id, vms->oem_table_id);
1476 }
1477
1478 /* XSDT is pointed to by RSDP */
1479 xsdt = tables_blob->len;
1480 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
1481 vms->oem_table_id);
1482
1483 /* RSDP is in FSEG memory, so allocate it separately */
1484 {
1485 AcpiRsdpData rsdp_data = {
1486 .revision = 2,
1487 .oem_id = vms->oem_id,
1488 .xsdt_tbl_offset = &xsdt,
1489 .rsdt_tbl_offset = NULL,
1490 };
1491 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1492 }
1493
1494 /*
1495 * The align size is 128, warn if 64k is not enough therefore
1496 * the align size could be resized.
1497 */
1498 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1499 warn_report("ACPI table size %u exceeds %d bytes,"
1500 " migration may not work",
1501 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1502 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1503 " or PCI bridges.\n");
1504 }
1505 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1506
1507
1508 /* Cleanup memory that's no longer used. */
1509 g_array_free(table_offsets, true);
1510 }
1511
1512 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1513 {
1514 uint32_t size = acpi_data_len(data);
1515
1516 /* Make sure RAM size is correct - in case it got changed
1517 * e.g. by migration */
1518 memory_region_ram_resize(mr, size, &error_abort);
1519
1520 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1521 memory_region_set_dirty(mr, 0, size);
1522 }
1523
1524 static void virt_acpi_build_update(void *build_opaque)
1525 {
1526 AcpiBuildState *build_state = build_opaque;
1527 AcpiBuildTables tables;
1528
1529 /* No state to update or already patched? Nothing to do. */
1530 if (!build_state || build_state->patched) {
1531 return;
1532 }
1533 build_state->patched = true;
1534
1535 acpi_build_tables_init(&tables);
1536
1537 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1538
1539 acpi_ram_update(build_state->table_mr, tables.table_data);
1540 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1541 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1542
1543 acpi_build_tables_cleanup(&tables, true);
1544 }
1545
1546 static void virt_acpi_build_reset(void *build_opaque)
1547 {
1548 AcpiBuildState *build_state = build_opaque;
1549 build_state->patched = false;
1550 }
1551
1552 static const VMStateDescription vmstate_virt_acpi_build = {
1553 .name = "virt_acpi_build",
1554 .version_id = 1,
1555 .minimum_version_id = 1,
1556 .fields = (const VMStateField[]) {
1557 VMSTATE_BOOL(patched, AcpiBuildState),
1558 VMSTATE_END_OF_LIST()
1559 },
1560 };
1561
1562 void virt_acpi_setup(VirtMachineState *vms)
1563 {
1564 AcpiBuildTables tables;
1565 AcpiBuildState *build_state;
1566 AcpiGedState *acpi_ged_state;
1567
1568 if (!vms->fw_cfg) {
1569 trace_virt_acpi_setup();
1570 return;
1571 }
1572
1573 if (!virt_is_acpi_enabled(vms)) {
1574 trace_virt_acpi_setup();
1575 return;
1576 }
1577
1578 build_state = g_malloc0(sizeof *build_state);
1579
1580 acpi_build_tables_init(&tables);
1581 virt_acpi_build(vms, &tables);
1582
1583 /* Now expose it all to Guest */
1584 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1585 build_state, tables.table_data,
1586 ACPI_BUILD_TABLE_FILE);
1587 assert(build_state->table_mr != NULL);
1588
1589 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1590 build_state,
1591 tables.linker->cmd_blob,
1592 ACPI_BUILD_LOADER_FILE);
1593
1594 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1595 acpi_data_len(tables.tcpalog));
1596
1597 if (vms->ras) {
1598 assert(vms->acpi_dev);
1599 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1600 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1601 vms->fw_cfg, tables.hardware_errors);
1602 }
1603
1604 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1605 build_state, tables.rsdp,
1606 ACPI_BUILD_RSDP_FILE);
1607
1608 qemu_register_reset(virt_acpi_build_reset, build_state);
1609 virt_acpi_build_reset(build_state);
1610 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1611
1612 /* Cleanup tables but don't free the memory: we track it
1613 * in build_state.
1614 */
1615 acpi_build_tables_cleanup(&tables, false);
1616 }