virt.c · samitouri/QOSamiQemu · siGit Code & Deploy

Code Commits Issues Pulls Sessions CI/CD

master

c 4,631 lines 170 KB

Raw

1	/*
2	* ARM mach-virt emulation
3	*
4	* Copyright (c) 2013 Linaro Limited
5	*
6	* This program is free software; you can redistribute it and/or modify it
7	* under the terms and conditions of the GNU General Public License,
8	* version 2 or later, as published by the Free Software Foundation.
9	*
10	* This program is distributed in the hope it will be useful, but WITHOUT
11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13	* more details.
14	*
15	* You should have received a copy of the GNU General Public License along with
16	* this program. If not, see <http://www.gnu.org/licenses/>.
17	*
18	* Emulate a virtual board which works by passing Linux all the information
19	* it needs about what devices are present via the device tree.
20	* There are some restrictions about what we can do here:
21	* + we can only present devices whose Linux drivers will work based
22	* purely on the device tree with no platform data at all
23	* + we want to present a very stripped-down minimalist platform,
24	* both because this reduces the security attack surface from the guest
25	* and also because it reduces our exposure to being broken when
26	* the kernel updates its device tree bindings and requires further
27	* information in a device binding that we aren't providing.
28	* This is essentially the same approach kvmtool uses.
29	*/
30
31	#include "qemu/osdep.h"
32	#include "qemu/datadir.h"
33	#include "qemu/units.h"
34	#include "qemu/option.h"
35	#include "qemu/target-info.h"
36	#include "monitor/qdev.h"
37	#include "hw/core/sysbus.h"
38	#include "hw/arm/boot.h"
39	#include "hw/arm/virt.h"
40	#include "hw/arm/machines-qom.h"
41	#include "hw/block/flash.h"
42	#include "hw/display/ramfb.h"
43	#include "net/net.h"
44	#include "system/device_tree.h"
45	#include "system/numa.h"
46	#include "system/runstate.h"
47	#include "system/tpm.h"
48	#include "system/tcg.h"
49	#include "system/kvm.h"
50	#include "system/hvf.h"
51	#include "system/whpx.h"
52	#include "system/qtest.h"
53	#include "system/system.h"
54	#include "hw/core/loader.h"
55	#include "qapi/error.h"
56	#include "qemu/bitops.h"
57	#include "qemu/cutils.h"
58	#include "qemu/error-report.h"
59	#include "qemu/module.h"
60	#include "hw/pci/pci_bus.h"
61	#include "hw/pci-host/gpex.h"
62	#include "hw/pci-bridge/pci_expander_bridge.h"
63	#include "hw/virtio/virtio-pci.h"
64	#include "hw/core/sysbus-fdt.h"
65	#include "hw/core/platform-bus.h"
66	#include "hw/core/qdev-properties.h"
67	#include "hw/arm/fdt.h"
68	#include "hw/intc/arm_gic.h"
69	#include "hw/intc/arm_gicv3_common.h"
70	#include "hw/intc/arm_gicv3_its_common.h"
71	#include "hw/intc/arm_gicv5_common.h"
72	#include "hw/core/irq.h"
73	#include "kvm_arm.h"
74	#include "whpx_arm.h"
75	#include "hw/firmware/smbios.h"
76	#include "qapi/visitor.h"
77	#include "qapi/qapi-visit-common.h"
78	#include "qobject/qlist.h"
79	#include "standard-headers/linux/input.h"
80	#include "hw/arm/smmuv3.h"
81	#include "hw/acpi/acpi.h"
82	#include "hw/acpi/pcihp.h"
83	#include "target/arm/cpu-qom.h"
84	#include "target/arm/internals.h"
85	#include "target/arm/multiprocessing.h"
86	#include "target/arm/gtimer.h"
87	#include "hw/mem/pc-dimm.h"
88	#include "hw/mem/nvdimm.h"
89	#include "hw/acpi/generic_event_device.h"
90	#include "hw/uefi/var-service-api.h"
91	#include "hw/virtio/virtio-md-pci.h"
92	#include "hw/virtio/virtio-iommu.h"
93	#include "hw/char/pl011.h"
94	#include "hw/core/cpu.h"
95	#include "hw/cxl/cxl.h"
96	#include "hw/cxl/cxl_host.h"
97	#include "qemu/guest-random.h"
98	#include "hw/watchdog/sbsa_gwdt.h"
99
100	static GlobalProperty arm_virt_compat_defaults[] = {
101	{ TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
102	};
103	static const size_t arm_virt_compat_defaults_len =
104	G_N_ELEMENTS(arm_virt_compat_defaults);
105
106	/*
107	* This cannot be called from the virt_machine_class_init() because
108	* TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
109	* only is called on virt non abstract class init.
110	*/
111	static void arm_virt_compat_default_set(MachineClass *mc)
112	{
113	compat_props_add(mc->compat_props, arm_virt_compat_defaults,
114	arm_virt_compat_defaults_len);
115	}
116
117	#define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
118	static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
119	ObjectClass *oc, \
120	const void *data) \
121	{ \
122	MachineClass *mc = MACHINE_CLASS(oc); \
123	arm_virt_compat_default_set(mc); \
124	MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
125	mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
126	MACHINE_VER_DEPRECATION(__VA_ARGS__); \
127	if (latest) { \
128	mc->alias = "virt"; \
129	} \
130	} \
131	static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
132	{ \
133	.name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
134	.parent = TYPE_VIRT_MACHINE, \
135	.class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
136	.interfaces = arm_aarch64_machine_interfaces, \
137	}; \
138	static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
139	{ \
140	MACHINE_VER_DELETION(__VA_ARGS__); \
141	type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
142	} \
143	type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
144
145	#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
146	DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
147	#define DEFINE_VIRT_MACHINE(major, minor) \
148	DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
149
150
151	/* Number of external interrupt lines to configure the GIC with */
152	#define NUM_IRQS 256
153
154	#define PLATFORM_BUS_NUM_IRQS 64
155
156	/* Legacy RAM limit in GB (< version 4.0) */
157	#define LEGACY_RAMLIMIT_GB 255
158	#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
159
160	/* MMIO region size for SMMUv3 */
161	#define SMMU_IO_LEN 0x20000
162
163	/* Addresses and sizes of our components.
164	* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
165	* 128MB..256MB is used for miscellaneous device I/O.
166	* 256MB..1GB is reserved for possible future PCI support (ie where the
167	* PCI memory window will go if we add a PCI host controller).
168	* 1GB and up is RAM (which may happily spill over into the
169	* high memory region beyond 4GB).
170	* This represents a compromise between how much RAM can be given to
171	* a 32 bit VM and leaving space for expansion and in particular for PCI.
172	* Note that devices should generally be placed at multiples of 0x10000,
173	* to accommodate guests using 64K pages.
174	*/
175	static const MemMapEntry base_memmap[] = {
176	/* Space up to 0x8000000 is reserved for a boot ROM */
177	[VIRT_FLASH] = { 0, 0x08000000 },
178	[VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
179	/* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
180	[VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
181	[VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
182	[VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
183	[VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
184	[VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
185	/* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
186	[VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
187	/* This redistributor space allows up to 264kB123 CPUs */
188	[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
189	/* The GICv5 uses this address range differently from GICv2/v3/v4 */
190	[VIRT_GICV5_IRS_S] = { 0x08000000, 0x00010000 },
191	[VIRT_GICV5_IRS_NS] = { 0x08010000, 0x00010000 },
192	[VIRT_GICV5_IRS_EL3] = { 0x08020000, 0x00010000 },
193	[VIRT_GICV5_IRS_REALM] = { 0x08030000, 0x00010000 },
194	[VIRT_GICV5_ITS_S] = { 0x08040000, 0x00010000 },
195	[VIRT_GICV5_ITS_NS] = { 0x08050000, 0x00010000 },
196	[VIRT_GICV5_ITS_EL3] = { 0x08060000, 0x00010000 },
197	[VIRT_GICV5_ITS_REALM] = { 0x08070000, 0x00010000 },
198	[VIRT_GICV5_ITS_TR_S] = { 0x08080000, 0x00010000 },
199	[VIRT_GICV5_ITS_TR_NS] = { 0x08090000, 0x00010000 },
200	[VIRT_GICV5_ITS_TR_EL3] = { 0x080A0000, 0x00010000 },
201	[VIRT_GICV5_ITS_TR_REALM] = { 0x080B0000, 0x00010000 },
202	[VIRT_UART0] = { 0x09000000, 0x00001000 },
203	[VIRT_RTC] = { 0x09010000, 0x00001000 },
204	[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
205	[VIRT_GPIO] = { 0x09030000, 0x00001000 },
206	[VIRT_UART1] = { 0x09040000, 0x00001000 },
207	[VIRT_SMMU] = { 0x09050000, SMMU_IO_LEN },
208	[VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
209	[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
210	[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
211	[VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
212	[VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
213	[VIRT_ACPI_PCIHP] = { 0x090c0000, ACPI_PCIHP_SIZE },
214	[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
215	/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
216	[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
217	[VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
218	[VIRT_GWDT_REFRESH] = { 0x0f000000, 0x00001000 },
219	[VIRT_GWDT_CONTROL] = { 0x0f001000, 0x00001000 },
220	[VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
221	[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
222	[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
223	/* Actual RAM size depends on initial RAM and device memory settings */
224	[VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
225	};
226
227	/* Update the docs for highmem-mmio-size when changing this default */
228	#define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512
229	#define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB)
230
231	/*
232	* Highmem IO Regions: This memory map is floating, located after the RAM.
233	* Each MemMapEntry base (GPA) will be dynamically computed, depending on the
234	* top of the RAM, so that its base get the same alignment as the size,
235	* ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
236	* less than 256GiB of RAM, the floating area starts at the 256GiB mark.
237	* Note the extended_memmap is sized so that it eventually also includes the
238	* base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
239	* index of base_memmap).
240	*
241	* The memory map for these Highmem IO Regions can be in legacy or compact
242	* layout, depending on 'compact-highmem' property. With legacy layout, the
243	* PA space for one specific region is always reserved, even if the region
244	* has been disabled or doesn't fit into the PA space. However, the PA space
245	* for the region won't be reserved in these circumstances with compact layout.
246	*
247	* Note that the highmem-mmio-size property will update the high PCIE MMIO size
248	* field in this array.
249	*/
250	static MemMapEntry extended_memmap[] = {
251	/* Additional 64 MB redist region (can contain up to 512 redistributors) */
252	[VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
253	[VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */
254	[VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
255	/* Second PCIe window */
256	[VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE },
257	/* Any CXL Fixed memory windows come here */
258	};
259
260	/* Counts SMMUv3 devices plugged; used to assign stable IORT identifiers */
261	static uint8_t smmuv3_dev_id;
262
263	static const int a15irqmap[] = {
264	[VIRT_UART0] = 1,
265	[VIRT_RTC] = 2,
266	[VIRT_PCIE] = 3, /* ... to 6 */
267	[VIRT_GPIO] = 7,
268	[VIRT_UART1] = 8,
269	[VIRT_ACPI_GED] = 9,
270	[VIRT_GWDT_WS0] = 10,
271	[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
272	[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
273	[VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
274	[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
275	};
276
277	static void create_randomness(MachineState ms, const char node)
278	{
279	struct {
280	uint64_t kaslr;
281	uint8_t rng[32];
282	} seed;
283
284	if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
285	return;
286	}
287	qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
288	qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
289	}
290
291	/*
292	* The CPU object always exposes the NS EL2 virt timer IRQ line,
293	* but we don't want to advertise it to the guest in the dtb or ACPI
294	* table unless it's really going to do something.
295	*/
296	static bool ns_el2_virt_timer_present(void)
297	{
298	ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
299	CPUARMState *env = &cpu->env;
300
301	return arm_feature(env, ARM_FEATURE_AARCH64) &&
302	arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
303	}
304
305	void set_cpu_cache(CPUCoreCaches *cpu_cache, enum CacheType cache_type,
306	int cache_level, bool is_i_cache0)
307	{
308	int bank_index = ((cache_level - 1) * 2) \| is_i_cache0;
309	ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
310	bool ccidx = cpu_isar_feature(any_ccidx, armcpu);
311
312	if (ccidx) {
313	*cpu_cache = (CPUCoreCaches){
314	.linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1,
315	CCIDX_LINESIZE) + 4),
316	.associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1,
317	CCIDX_ASSOCIATIVITY) + 1,
318	.sets = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1,
319	CCIDX_NUMSETS) + 1,
320	};
321	} else {
322	*cpu_cache = (CPUCoreCaches){
323	.linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1,
324	LINESIZE) + 4),
325	.associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1,
326	ASSOCIATIVITY) + 1,
327	.sets =
328	FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, NUMSETS) + 1,
329	};
330	}
331	cpu_cache->type = cache_type;
332	cpu_cache->level = cache_level;
333	cpu_cache->size = cpu_cache->associativity *
334	cpu_cache->sets *
335	cpu_cache->linesize;
336
337	return;
338	}
339
340	unsigned int virt_get_caches(const VirtMachineState vms, CPUCoreCaches caches)
341	{
342	int num_cache = 0;
343	ARMCPU armcpu = ARM_CPU(qemu_get_cpu(0)); / assume homogeneous CPUs */
344	ARMISARegisters *isar = &armcpu->isar;
345	uint32_t clidr = GET_IDREG(isar, CLIDR);
346
347	for (int cache_level = 1; cache_level <= CLIDR_CTYPE_MAX_CACHE_LEVEL;
348	cache_level++) {
349	uint8_t ctype =
350	(clidr >> (3 * (cache_level - 1))) & CLIDR_CTYPE_MAX_CACHE_LEVEL;
351
352	if (ctype == CLIDR_CTYPE_NO_CACHE) {
353	/*
354	* If a "No cache" cache type is found it means no manageable caches
355	* exist at further-out levels of hierarchy, so ignore them.
356	*/
357	break;
358	} else if (ctype == CLIDR_CTYPE_SEPARATE_I_D_CACHES) {
359	/*
360	* Create separate D and I caches. D-cache is stored first.
361	*/
362	enum CacheType cache_type;
363	for (cache_type = DATA_CACHE; cache_type <= INSTRUCTION_CACHE;
364	cache_type++) {
365	set_cpu_cache(&caches[num_cache++], cache_type, cache_level,
366	cache_type == INSTRUCTION_CACHE ? true : false);
367	}
368	} else if (ctype == CLIDR_CTYPE_UNIFIED_CACHE) {
369	set_cpu_cache(&caches[num_cache++], UNIFIED_CACHE, cache_level,
370	false);
371	} else if (ctype == CLIDR_CTYPE_D_CACHE) {
372	set_cpu_cache(&caches[num_cache++], DATA_CACHE, cache_level, false);
373	} else if (ctype == CLIDR_CTYPE_I_CACHE) {
374	set_cpu_cache(&caches[num_cache++], INSTRUCTION_CACHE, cache_level,
375	true);
376	} else {
377	error_setg(&error_abort, "Unrecognized cache type");
378	return 0;
379	}
380	}
381
382	return num_cache;
383	}
384
385	/*
386	* The correct value to use in a DTB "interrupts" property for an SPI
387	* depends on the GIC version.
388	*/
389	static int gic_fdt_irq_type_spi(const VirtMachineState *vms)
390	{
391	return vms->gic_version == VIRT_GIC_VERSION_5 ?
392	GICV5_SPI : GIC_FDT_IRQ_TYPE_SPI;
393	}
394
395	static void create_fdt(VirtMachineState *vms)
396	{
397	MachineState *ms = MACHINE(vms);
398	int nb_numa_nodes = ms->numa_state->num_nodes;
399	void *fdt = create_device_tree(&vms->fdt_size);
400
401	if (!fdt) {
402	error_report("create_device_tree() failed");
403	exit(1);
404	}
405
406	ms->fdt = fdt;
407
408	/* Header */
409	qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
410	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
411	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
412	qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
413
414	/*
415	* For QEMU, all DMA is coherent. Advertising this in the root node
416	* has two benefits:
417	*
418	* - It avoids potential bugs where we forget to mark a DMA
419	* capable device as being dma-coherent
420	* - It avoids spurious warnings from the Linux kernel about
421	* devices which can't do DMA at all
422	*/
423	qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
424
425	/* /chosen must exist for load_dtb to fill in necessary properties later */
426	qemu_fdt_add_subnode(fdt, "/chosen");
427	if (vms->dtb_randomness) {
428	create_randomness(ms, "/chosen");
429	}
430
431	if (vms->secure) {
432	qemu_fdt_add_subnode(fdt, "/secure-chosen");
433	if (vms->dtb_randomness) {
434	create_randomness(ms, "/secure-chosen");
435	}
436	}
437
438	qemu_fdt_add_subnode(fdt, "/aliases");
439
440	/* Clock node, for the benefit of the UART. The kernel device tree
441	* binding documentation claims the PL011 node clock properties are
442	* optional but in practice if you omit them the kernel refuses to
443	* probe for the device.
444	*/
445	vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
446	qemu_fdt_add_subnode(fdt, "/apb-pclk");
447	qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
448	qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
449	qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
450	qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
451	"clk24mhz");
452	qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
453
454	if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
455	int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
456	uint32_t *matrix = g_malloc0(size);
457	int idx, i, j;
458
459	for (i = 0; i < nb_numa_nodes; i++) {
460	for (j = 0; j < nb_numa_nodes; j++) {
461	idx = (i * nb_numa_nodes + j) * 3;
462	matrix[idx + 0] = cpu_to_be32(i);
463	matrix[idx + 1] = cpu_to_be32(j);
464	matrix[idx + 2] =
465	cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
466	}
467	}
468
469	qemu_fdt_add_subnode(fdt, "/distance-map");
470	qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
471	"numa-distance-map-v1");
472	qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
473	matrix, size);
474	g_free(matrix);
475	}
476	}
477
478	static void fdt_add_timer_nodes(const VirtMachineState *vms)
479	{
480	/* On real hardware these interrupts are level-triggered.
481	* On KVM they were edge-triggered before host kernel version 4.4,
482	* and level-triggered afterwards.
483	* On emulated QEMU they are level-triggered.
484	*
485	* Getting the DTB info about them wrong is awkward for some
486	* guest kernels:
487	* pre-4.8 ignore the DT and leave the interrupt configured
488	* with whatever the GIC reset value (or the bootloader) left it at
489	* 4.8 before rc6 honour the incorrect data by programming it back
490	* into the GIC, causing problems
491	* 4.8rc6 and later ignore the DT and always write "level triggered"
492	* into the GIC
493	*
494	* For backwards-compatibility, virt-2.8 and earlier will continue
495	* to say these are edge-triggered, but later machines will report
496	* the correct information.
497	*/
498	ARMCPU *armcpu;
499	uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
500	MachineState *ms = MACHINE(vms);
501
502	if (vms->gic_version == VIRT_GIC_VERSION_2) {
503	irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
504	GIC_FDT_IRQ_PPI_CPU_WIDTH,
505	(1 << MACHINE(vms)->smp.cpus) - 1);
506	}
507
508	qemu_fdt_add_subnode(ms->fdt, "/timer");
509
510	armcpu = ARM_CPU(qemu_get_cpu(0));
511	if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
512	const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
513	qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
514	compat, sizeof(compat));
515	} else {
516	qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
517	"arm,armv7-timer");
518	}
519	qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
520	if (vms->gic_version == VIRT_GIC_VERSION_5) {
521	/* The GICv5 architects the PPI numbers differently */
522	qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
523	GICV5_PPI, GICV5_PPI_CNTPS, irqflags,
524	GICV5_PPI, GICV5_PPI_CNTP, irqflags,
525	GICV5_PPI, GICV5_PPI_CNTV, irqflags,
526	GICV5_PPI, GICV5_PPI_CNTHP, irqflags,
527	GICV5_PPI, GICV5_PPI_CNTHV, irqflags);
528	} else if (vms->ns_el2_virt_timer_irq) {
529	qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
530	GIC_FDT_IRQ_TYPE_PPI,
531	INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
532	GIC_FDT_IRQ_TYPE_PPI,
533	INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
534	GIC_FDT_IRQ_TYPE_PPI,
535	INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
536	GIC_FDT_IRQ_TYPE_PPI,
537	INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
538	GIC_FDT_IRQ_TYPE_PPI,
539	INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
540	} else {
541	qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
542	GIC_FDT_IRQ_TYPE_PPI,
543	INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
544	GIC_FDT_IRQ_TYPE_PPI,
545	INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
546	GIC_FDT_IRQ_TYPE_PPI,
547	INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
548	GIC_FDT_IRQ_TYPE_PPI,
549	INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
550	}
551	}
552
553	static void add_cache_node(void fdt, char nodepath, CPUCoreCaches cache,
554	uint32_t *next_level)
555	{
556	/* Assume L2/3 are unified caches. */
557
558	uint32_t phandle;
559
560	qemu_fdt_add_path(fdt, nodepath);
561	phandle = qemu_fdt_alloc_phandle(fdt);
562	qemu_fdt_setprop_cell(fdt, nodepath, "phandle", phandle);
563	qemu_fdt_setprop_cell(fdt, nodepath, "cache-level", cache.level);
564	qemu_fdt_setprop_cell(fdt, nodepath, "cache-size", cache.size);
565	qemu_fdt_setprop_cell(fdt, nodepath, "cache-block-size", cache.linesize);
566	qemu_fdt_setprop_cell(fdt, nodepath, "cache-sets", cache.sets);
567	qemu_fdt_setprop(fdt, nodepath, "cache-unified", NULL, 0);
568	qemu_fdt_setprop_string(fdt, nodepath, "compatible", "cache");
569	if (cache.level != 3) {
570	/* top level cache doesn't have next-level-cache property */
571	qemu_fdt_setprop_cell(fdt, nodepath, "next-level-cache", *next_level);
572	}
573
574	*next_level = phandle;
575	}
576
577	static bool add_cpu_cache_hierarchy(void fdt, CPUCoreCaches cache,
578	uint32_t cache_cnt,
579	uint32_t top_level,
580	uint32_t bottom_level,
581	uint32_t cpu_id,
582	uint32_t *next_level) {
583	bool found_cache = false;
584
585	for (int level = top_level; level >= bottom_level; level--) {
586	for (int i = 0; i < cache_cnt; i++) {
587	char *nodepath;
588
589	if (i != level) {
590	continue;
591	}
592
593	nodepath = g_strdup_printf("/cpus/cpu@%d/l%d-cache",
594	cpu_id, level);
595	add_cache_node(fdt, nodepath, cache[i], next_level);
596	found_cache = true;
597	g_free(nodepath);
598
599	}
600	}
601
602	return found_cache;
603	}
604
605	static void set_cache_properties(void fdt, const char nodename,
606	const char *prefix, CPUCoreCaches cache)
607	{
608	char prop_name[64];
609
610	snprintf(prop_name, sizeof(prop_name), "%s-block-size", prefix);
611	qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.linesize);
612
613	snprintf(prop_name, sizeof(prop_name), "%s-size", prefix);
614	qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.size);
615
616	snprintf(prop_name, sizeof(prop_name), "%s-sets", prefix);
617	qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.sets);
618	}
619
620	static bool partial_cache_description(const MachineState *ms, int num_caches)
621	{
622	assert(num_caches - 1 < CACHE_LEVEL_AND_TYPE__MAX);
623	enum CpuTopologyLevel topo_level;
624	enum CacheLevelAndType cache_level;
625
626	for (cache_level = 0; cache_level < num_caches; cache_level++) {
627	topo_level = machine_get_cache_topo_level(ms, cache_level);
628	if (topo_level == CPU_TOPOLOGY_LEVEL_DEFAULT) {
629	/* No topology level described for this cache level. */
630	return true;
631	}
632	}
633
634	return false;
635	}
636
637	static void fdt_add_cpu_nodes(VirtMachineState *vms)
638	{
639	int cpu;
640	int addr_cells = 1;
641	const MachineState *ms = MACHINE(vms);
642	const MachineClass *mc = MACHINE_GET_CLASS(ms);
643	const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
644	unsigned int smp_cpus = ms->smp.cpus;
645	int socket_id, cluster_id, core_id;
646	uint32_t next_level = 0;
647	uint32_t socket_offset = 0;
648	uint32_t cluster_offset = 0;
649	uint32_t core_offset = 0;
650	int last_socket = -1;
651	int last_cluster = -1;
652	int last_core = -1;
653	int top_node = 3;
654	int top_cluster = 3;
655	int top_core = 3;
656	int bottom_node = 3;
657	int bottom_cluster = 3;
658	int bottom_core = 3;
659	unsigned int num_cache;
660	CPUCoreCaches caches[CPU_MAX_CACHES];
661	bool cache_created = false;
662	bool cache_at_topo_level;
663
664	num_cache = virt_get_caches(vms, caches);
665
666	if (mc->smp_props.has_caches &&
667	partial_cache_description(ms, num_cache)) {
668	error_setg(&error_fatal, "Missing cache description");
669	return;
670	}
671
672	/*
673	* See Linux Documentation/devicetree/bindings/arm/cpus.yaml
674	* On ARM v8 64-bit systems value should be set to 2,
675	* that corresponds to the MPIDR_EL1 register size.
676	* If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
677	* in the system, #address-cells can be set to 1, since
678	* MPIDR_EL1[63:32] bits are not used for CPUs
679	* identification.
680	*
681	* Here we actually don't know whether our system is 32- or 64-bit one.
682	* The simplest way to go is to examine affinity IDs of all our CPUs. If
683	* at least one of them has Aff3 populated, we set #address-cells to 2.
684	*/
685	for (cpu = 0; cpu < smp_cpus; cpu++) {
686	ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
687
688	if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
689	addr_cells = 2;
690	break;
691	}
692	}
693
694	qemu_fdt_add_subnode(ms->fdt, "/cpus");
695	qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
696	qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
697
698	vms->cpu_phandles = g_new0(uint32_t, smp_cpus);
699
700	for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
701	socket_id = cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
702	cluster_id = cpu / (ms->smp.cores * ms->smp.threads) % ms->smp.clusters;
703	core_id = cpu / ms->smp.threads % ms->smp.cores;
704
705	char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
706	ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
707	CPUState *cs = CPU(armcpu);
708	const char *prefix = NULL;
709	uint32_t phandle;
710
711	qemu_fdt_add_subnode(ms->fdt, nodename);
712	qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
713	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
714	armcpu->dtb_compatible);
715
716	if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
717	qemu_fdt_setprop_string(ms->fdt, nodename,
718	"enable-method", "psci");
719	}
720
721	if (addr_cells == 2) {
722	qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
723	arm_cpu_mp_affinity(armcpu));
724	} else {
725	qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
726	arm_cpu_mp_affinity(armcpu));
727	}
728
729	if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
730	qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
731	ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
732	}
733
734	phandle = qemu_fdt_alloc_phandle(ms->fdt);
735	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
736	vms->cpu_phandles[cpu] = phandle;
737
738	if (!vmc->no_cpu_topology && num_cache) {
739	for (uint8_t i = 0; i < num_cache; i++) {
740	/* Only level 1 in the CPU entry. */
741	if (caches[i].level > 1) {
742	continue;
743	}
744
745	if (caches[i].type == INSTRUCTION_CACHE) {
746	prefix = "i-cache";
747	} else if (caches[i].type == DATA_CACHE) {
748	prefix = "d-cache";
749	} else if (caches[i].type == UNIFIED_CACHE) {
750	error_setg(&error_fatal,
751	"Unified type is not implemented at level %d",
752	caches[i].level);
753	return;
754	} else {
755	error_setg(&error_fatal, "Undefined cache type");
756	return;
757	}
758
759	set_cache_properties(ms->fdt, nodename, prefix, caches[i]);
760	}
761	}
762
763	if (socket_id != last_socket) {
764	bottom_node = top_node;
765	/* This assumes socket as the highest topological level. */
766	socket_offset = 0;
767	cluster_offset = 0;
768	cache_at_topo_level =
769	machine_find_lowest_level_cache_at_topo_level(ms,
770	&bottom_node,
771	CPU_TOPOLOGY_LEVEL_SOCKET);
772	if (cache_at_topo_level) {
773	if (bottom_node == 1 && !virt_is_acpi_enabled(vms))
774	error_setg(
775	&error_fatal,
776	"Cannot share L1 at socket_id %d."
777	"DT limitation on sharing at cache level = 1",
778	socket_id);
779
780	cache_created = add_cpu_cache_hierarchy(ms->fdt, caches,
781	num_cache,
782	top_node,
783	bottom_node, cpu,
784	&socket_offset);
785
786	if (!cache_created) {
787	error_setg(&error_fatal,
788	"Socket: No caches at levels %d-%d",
789	top_node, bottom_node);
790	return;
791	}
792
793	top_cluster = bottom_node - 1;
794	}
795
796	last_socket = socket_id;
797	}
798
799	if (cluster_id != last_cluster) {
800	bottom_cluster = top_cluster;
801	cluster_offset = socket_offset;
802	core_offset = 0;
803	cache_at_topo_level =
804	machine_find_lowest_level_cache_at_topo_level(ms,
805	&bottom_cluster,
806	CPU_TOPOLOGY_LEVEL_CLUSTER);
807	if (cache_at_topo_level) {
808	cache_created = add_cpu_cache_hierarchy(ms->fdt, caches,
809	num_cache,
810	top_cluster,
811	bottom_cluster, cpu,
812	&cluster_offset);
813	if (bottom_cluster == 1 && !virt_is_acpi_enabled(vms)) {
814	error_setg(&error_fatal,
815	"Cannot share L1 at socket_id %d, cluster_id %d. "
816	"DT limitation on sharing at cache level = 1.",
817	socket_id, cluster_id);
818	}
819
820	if (!cache_created) {
821	error_setg(&error_fatal,
822	"Cluster: No caches at levels %d-%d.",
823	top_cluster, bottom_cluster);
824	return;
825	}
826
827	top_core = bottom_cluster - 1;
828	} else if (top_cluster == bottom_node - 1) {
829	top_core = bottom_node - 1;
830	}
831
832	last_cluster = cluster_id;
833	}
834
835	if (core_id != last_core) {
836	bottom_core = top_core;
837	core_offset = cluster_offset;
838	cache_at_topo_level =
839	machine_find_lowest_level_cache_at_topo_level(ms,
840	&bottom_core,
841	CPU_TOPOLOGY_LEVEL_CORE);
842	if (cache_at_topo_level) {
843	if (bottom_core == 1 && top_core > 1) {
844	bottom_core++;
845	cache_created = add_cpu_cache_hierarchy(ms->fdt,
846	caches,
847	num_cache,
848	top_core,
849	bottom_core, cpu,
850	&core_offset);
851
852	if (!cache_created) {
853	error_setg(&error_fatal,
854	"Core: No caches at levels %d-%d",
855	top_core, bottom_core);
856	return;
857	}
858	}
859	}
860
861	last_core = core_id;
862	}
863
864	next_level = core_offset;
865	qemu_fdt_setprop_cell(ms->fdt, nodename, "next-level-cache",
866	next_level);
867
868	g_free(nodename);
869	}
870
871	if (!vmc->no_cpu_topology) {
872	/*
873	* Add vCPU topology description through fdt node cpu-map.
874	*
875	* See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
876	* In a SMP system, the hierarchy of CPUs can be defined through
877	* four entities that are used to describe the layout of CPUs in
878	* the system: socket/cluster/core/thread.
879	*
880	* A socket node represents the boundary of system physical package
881	* and its child nodes must be one or more cluster nodes. A system
882	* can contain several layers of clustering within a single physical
883	* package and cluster nodes can be contained in parent cluster nodes.
884	*
885	* Note: currently we only support one layer of clustering within
886	* each physical package.
887	*/
888	qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
889
890	for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
891	char *map_path;
892
893	if (ms->smp.threads > 1) {
894	map_path = g_strdup_printf(
895	"/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
896	cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
897	(cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
898	(cpu / ms->smp.threads) % ms->smp.cores,
899	cpu % ms->smp.threads);
900	} else {
901	map_path = g_strdup_printf(
902	"/cpus/cpu-map/socket%d/cluster%d/core%d",
903	cpu / (ms->smp.clusters * ms->smp.cores),
904	(cpu / ms->smp.cores) % ms->smp.clusters,
905	cpu % ms->smp.cores);
906	}
907	qemu_fdt_add_path(ms->fdt, map_path);
908	qemu_fdt_setprop_cell(ms->fdt, map_path, "cpu",
909	vms->cpu_phandles[cpu]);
910
911	g_free(map_path);
912	}
913	}
914	}
915
916	static void fdt_add_its_gic_node(VirtMachineState *vms)
917	{
918	char *nodename;
919	MachineState *ms = MACHINE(vms);
920
921	vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
922	nodename = g_strdup_printf("/intc/its@%" PRIx64,
923	vms->memmap[VIRT_GIC_ITS].base);
924	qemu_fdt_add_subnode(ms->fdt, nodename);
925	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
926	"arm,gic-v3-its");
927	qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
928	qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
929	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
930	2, vms->memmap[VIRT_GIC_ITS].base,
931	2, vms->memmap[VIRT_GIC_ITS].size);
932	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
933	g_free(nodename);
934	}
935
936	static void fdt_add_v2m_gic_node(VirtMachineState *vms)
937	{
938	MachineState *ms = MACHINE(vms);
939	char *nodename;
940
941	nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
942	vms->memmap[VIRT_GIC_V2M].base);
943	vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
944	qemu_fdt_add_subnode(ms->fdt, nodename);
945	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
946	"arm,gic-v2m-frame");
947	qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
948	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
949	2, vms->memmap[VIRT_GIC_V2M].base,
950	2, vms->memmap[VIRT_GIC_V2M].size);
951	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
952	g_free(nodename);
953	}
954
955	static void fdt_add_gic_node(VirtMachineState *vms)
956	{
957	MachineState *ms = MACHINE(vms);
958	char *nodename;
959
960	vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
961	qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
962
963	nodename = g_strdup_printf("/intc@%" PRIx64,
964	vms->memmap[VIRT_GIC_DIST].base);
965	qemu_fdt_add_subnode(ms->fdt, nodename);
966	qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
967	qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
968	qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
969	qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
970	qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
971	if (vms->gic_version != VIRT_GIC_VERSION_2) {
972	int nb_redist_regions = virt_gicv3_redist_region_count(vms);
973
974	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
975	"arm,gic-v3");
976
977	qemu_fdt_setprop_cell(ms->fdt, nodename,
978	"#redistributor-regions", nb_redist_regions);
979
980	if (nb_redist_regions == 1) {
981	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
982	2, vms->memmap[VIRT_GIC_DIST].base,
983	2, vms->memmap[VIRT_GIC_DIST].size,
984	2, vms->memmap[VIRT_GIC_REDIST].base,
985	2, vms->memmap[VIRT_GIC_REDIST].size);
986	} else {
987	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
988	2, vms->memmap[VIRT_GIC_DIST].base,
989	2, vms->memmap[VIRT_GIC_DIST].size,
990	2, vms->memmap[VIRT_GIC_REDIST].base,
991	2, vms->memmap[VIRT_GIC_REDIST].size,
992	2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
993	2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
994	}
995
996	if (vms->virt) {
997	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
998	GIC_FDT_IRQ_TYPE_PPI,
999	INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
1000	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1001	}
1002	} else {
1003	/* 'cortex-a15-gic' means 'GIC v2' */
1004	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
1005	"arm,cortex-a15-gic");
1006	if (!vms->virt) {
1007	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1008	2, vms->memmap[VIRT_GIC_DIST].base,
1009	2, vms->memmap[VIRT_GIC_DIST].size,
1010	2, vms->memmap[VIRT_GIC_CPU].base,
1011	2, vms->memmap[VIRT_GIC_CPU].size);
1012	} else {
1013	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1014	2, vms->memmap[VIRT_GIC_DIST].base,
1015	2, vms->memmap[VIRT_GIC_DIST].size,
1016	2, vms->memmap[VIRT_GIC_CPU].base,
1017	2, vms->memmap[VIRT_GIC_CPU].size,
1018	2, vms->memmap[VIRT_GIC_HYP].base,
1019	2, vms->memmap[VIRT_GIC_HYP].size,
1020	2, vms->memmap[VIRT_GIC_VCPU].base,
1021	2, vms->memmap[VIRT_GIC_VCPU].size);
1022	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1023	GIC_FDT_IRQ_TYPE_PPI,
1024	INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
1025	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1026	}
1027	}
1028
1029	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
1030	g_free(nodename);
1031	}
1032
1033	static void fdt_add_pmu_nodes(const VirtMachineState *vms)
1034	{
1035	ARMCPU *armcpu = ARM_CPU(first_cpu);
1036	uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1037	MachineState *ms = MACHINE(vms);
1038
1039	if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
1040	assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
1041	return;
1042	}
1043
1044	if (vms->gic_version == VIRT_GIC_VERSION_2) {
1045	irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
1046	GIC_FDT_IRQ_PPI_CPU_WIDTH,
1047	(1 << MACHINE(vms)->smp.cpus) - 1);
1048	}
1049
1050	qemu_fdt_add_subnode(ms->fdt, "/pmu");
1051	if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
1052	const char compat[] = "arm,armv8-pmuv3";
1053
1054	qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
1055	compat, sizeof(compat));
1056	if (vms->gic_version == VIRT_GIC_VERSION_5) {
1057	qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
1058	GICV5_PPI, GICV5_PPI_PMUIRQ, irqflags);
1059	} else {
1060	qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
1061	GIC_FDT_IRQ_TYPE_PPI,
1062	INTID_TO_PPI(VIRTUAL_PMU_IRQ),
1063	irqflags);
1064	}
1065	}
1066	}
1067
1068	static inline DeviceState create_acpi_ged(VirtMachineState vms)
1069	{
1070	DeviceState *dev;
1071	MachineState *ms = MACHINE(vms);
1072	SysBusDevice *sbdev;
1073	int irq = vms->irqmap[VIRT_ACPI_GED];
1074	uint32_t event = ACPI_GED_PWR_DOWN_EVT \| ACPI_GED_ERROR_EVT;
1075	bool acpi_pcihp;
1076
1077	if (ms->ram_slots) {
1078	event \|= ACPI_GED_MEM_HOTPLUG_EVT;
1079	}
1080
1081	if (ms->nvdimms_state->is_enabled) {
1082	event \|= ACPI_GED_NVDIMM_HOTPLUG_EVT;
1083	}
1084
1085	dev = qdev_new(TYPE_ACPI_GED);
1086	qdev_prop_set_uint32(dev, "ged-event", event);
1087	object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort);
1088	sbdev = SYS_BUS_DEVICE(dev);
1089	sysbus_realize_and_unref(sbdev, &error_fatal);
1090
1091	sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].base);
1092	sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME,
1093	vms->memmap[VIRT_PCDIMM_ACPI].base);
1094
1095	acpi_pcihp = object_property_get_bool(OBJECT(dev),
1096	ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, NULL);
1097
1098	if (acpi_pcihp) {
1099	int pcihp_region_index;
1100
1101	pcihp_region_index = sysbus_mmio_map_name(sbdev, ACPI_PCIHP_REGION_NAME,
1102	vms->memmap[VIRT_ACPI_PCIHP].base);
1103	assert(pcihp_region_index >= 0);
1104	}
1105
1106	sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq));
1107
1108	return dev;
1109	}
1110
1111	static void create_its(VirtMachineState *vms)
1112	{
1113	DeviceState *dev;
1114
1115	if (!kvm_irqchip_in_kernel() && !vms->tcg_its) {
1116	/*
1117	* Do nothing if ITS is neither supported by the host nor emulated by
1118	* the machine.
1119	*/
1120	return;
1121	}
1122
1123	dev = qdev_new(its_class_name());
1124
1125	object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
1126	&error_abort);
1127	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1128	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
1129
1130	fdt_add_its_gic_node(vms);
1131	vms->msi_controller = VIRT_MSI_CTRL_ITS;
1132	}
1133
1134	static void create_v2m(VirtMachineState *vms)
1135	{
1136	int i;
1137	int irq = vms->irqmap[VIRT_GIC_V2M];
1138	DeviceState *dev;
1139
1140	dev = qdev_new("arm-gicv2m");
1141	qdev_prop_set_uint32(dev, "base-spi", irq);
1142	qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
1143	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1144	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
1145
1146	for (i = 0; i < NUM_GICV2M_SPIS; i++) {
1147	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1148	qdev_get_gpio_in(vms->gic, irq + i));
1149	}
1150
1151	fdt_add_v2m_gic_node(vms);
1152	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
1153	}
1154
1155	static void fdt_add_gicv5_node(VirtMachineState *vms)
1156	{
1157	MachineState *ms = MACHINE(vms);
1158	const char *nodename = "/intc";
1159	g_autofree char *irsnodename = NULL;
1160	g_autofree uint32_t *cpu_phandles = g_new(uint32_t, ms->smp.cpus);
1161	g_autofree uint16_t *iaffids = g_new(uint16_t, ms->smp.cpus);
1162
1163	vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1164	qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
1165
1166	qemu_fdt_add_subnode(ms->fdt, nodename);
1167	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
1168	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "arm,gic-v5");
1169	qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
1170	qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
1171	qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
1172	qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
1173	qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
1174
1175	/* The IRS node is a child of the top level /intc node */
1176	irsnodename = g_strdup_printf("%s/irs@%" PRIx64,
1177	nodename,
1178	vms->memmap[VIRT_GICV5_IRS_NS].base);
1179	qemu_fdt_add_subnode(ms->fdt, irsnodename);
1180	qemu_fdt_setprop_string(ms->fdt, irsnodename, "compatible",
1181	"arm,gic-v5-irs");
1182	/*
1183	* "reg-names" describes the frames whose address/size is in "reg";
1184	* at the moment we have only the NS config register frame.
1185	*/
1186	qemu_fdt_setprop_string(ms->fdt, irsnodename, "reg-names", "ns-config");
1187	qemu_fdt_setprop_sized_cells(ms->fdt, irsnodename, "reg",
1188	2, vms->memmap[VIRT_GICV5_IRS_NS].base,
1189	2, vms->memmap[VIRT_GICV5_IRS_NS].size);
1190	qemu_fdt_setprop_cell(ms->fdt, irsnodename, "#address-cells", 0x2);
1191	qemu_fdt_setprop_cell(ms->fdt, irsnodename, "#size-cells", 0x2);
1192	qemu_fdt_setprop(ms->fdt, irsnodename, "ranges", NULL, 0);
1193
1194	/*
1195	* The "cpus" property is an array of phandles to the CPUs, and
1196	* "iaffids" is an array of uint16 IAFFIDs. For virt, our IAFFIDs
1197	* are the CPU indexes. This function is called after
1198	* fdt_add_cpu_nodes(), which allocates the cpu_phandles array.
1199	*/
1200	assert(vms->cpu_phandles);
1201	for (int i = 0; i < ms->smp.cpus; i++) {
1202	/*
1203	* We have to byteswap each element here because we're setting the
1204	* whole property value at once as a lump of raw data, not via a
1205	* helper like qemu_fdt_setprop_cell() that does the swapping for us.
1206	*/
1207	cpu_phandles[i] = cpu_to_be32(vms->cpu_phandles[i]);
1208	iaffids[i] = cpu_to_be16(i);
1209	}
1210	qemu_fdt_setprop(ms->fdt, irsnodename, "cpus", cpu_phandles,
1211	ms->smp.cpus * sizeof(*cpu_phandles));
1212	qemu_fdt_setprop(ms->fdt, irsnodename, "arm,iaffids", iaffids,
1213	ms->smp.cpus * sizeof(*iaffids));
1214
1215	/*
1216	* When we implement the GICv5 IRS, it gets a DTB node which is a
1217	* child of the IRS node.
1218	*/
1219	}
1220
1221	static void create_gicv5(VirtMachineState vms, MemoryRegion mem)
1222	{
1223	MachineState *ms = MACHINE(vms);
1224	SysBusDevice *gicbusdev;
1225	const char *gictype = gicv5_class_name();
1226	QList cpulist = qlist_new(), iaffidlist = qlist_new();
1227
1228	vms->gic = qdev_new(gictype);
1229	qdev_prop_set_uint32(vms->gic, "spi-range", NUM_IRQS);
1230
1231	object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem),
1232	&error_fatal);
1233
1234	for (int i = 0; i < ms->smp.cpus; i++) {
1235	qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i)));
1236	/*
1237	* GICv5 IAFFIDs must be system-wide unique across all GICs.
1238	* For virt we make them the same as the CPU index.
1239	*/
1240	qlist_append_int(iaffidlist, i);
1241	}
1242	qdev_prop_set_array(vms->gic, "cpus", cpulist);
1243	qdev_prop_set_array(vms->gic, "cpu-iaffids", iaffidlist);
1244
1245	gicbusdev = SYS_BUS_DEVICE(vms->gic);
1246	sysbus_realize_and_unref(gicbusdev, &error_fatal);
1247
1248	/*
1249	* Map the IRS config frames for the interrupt domains.
1250	* At the moment we implement only the NS domain, so this is simple.
1251	*/
1252	sysbus_mmio_map(gicbusdev, GICV5_ID_NS,
1253	vms->memmap[VIRT_GICV5_IRS_NS].base);
1254
1255	/*
1256	* The GICv5 does not need to wire up CPU timer IRQ outputs to the GIC
1257	* because for the GICv5 those PPIs are entirely internal to the CPU.
1258	* Nor do we need to wire up GIC IRQ/FIQ signals to the CPUs, because
1259	* that information is communicated directly between a GICv5 IRS and
1260	* the GICv5 CPU interface via our equivalent of the stream protocol.
1261	*/
1262
1263	fdt_add_gicv5_node(vms);
1264	}
1265
1266	/*
1267	* If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
1268	* It's permitted to have a configuration with NMI in the CPU (and thus the
1269	* GICv3 CPU interface) but not in the distributor/redistributors, but it's
1270	* not very useful.
1271	*/
1272	static bool gicv3_nmi_present(VirtMachineState *vms)
1273	{
1274	ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
1275
1276	return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
1277	(vms->gic_version != VIRT_GIC_VERSION_2);
1278	}
1279
1280	static void gic_connect_ppis(VirtMachineState *vms)
1281	{
1282	/*
1283	* Wire the outputs from each CPU's generic timer and the GICv3
1284	* maintenance interrupt signal to the appropriate GIC PPI inputs,
1285	* and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
1286	* CPU's inputs.
1287	*/
1288	MachineState *ms = MACHINE(vms);
1289	unsigned int smp_cpus = ms->smp.cpus;
1290	SysBusDevice *gicbusdev = SYS_BUS_DEVICE(vms->gic);
1291
1292	for (int i = 0; i < smp_cpus; i++) {
1293	DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
1294	int intidbase = NUM_IRQS + i * GIC_INTERNAL;
1295	/*
1296	* Mapping from the output timer irq lines from the CPU to the
1297	* GIC PPI inputs we use for the virt board.
1298	*/
1299	const int timer_irq[] = {
1300	[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
1301	[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
1302	[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
1303	[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
1304	[GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
1305	[GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
1306	[GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
1307	};
1308
1309	for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
1310	qdev_connect_gpio_out(cpudev, irq,
1311	qdev_get_gpio_in(vms->gic,
1312	intidbase + timer_irq[irq]));
1313	}
1314
1315	if (vms->gic_version != VIRT_GIC_VERSION_2) {
1316	qemu_irq irq = qdev_get_gpio_in(vms->gic,
1317	intidbase + ARCH_GIC_MAINT_IRQ);
1318	qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
1319	0, irq);
1320	} else if (vms->virt) {
1321	qemu_irq irq = qdev_get_gpio_in(vms->gic,
1322	intidbase + ARCH_GIC_MAINT_IRQ);
1323	sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
1324	}
1325
1326	qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
1327	qdev_get_gpio_in(vms->gic, intidbase
1328	+ VIRTUAL_PMU_IRQ));
1329
1330	sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
1331	sysbus_connect_irq(gicbusdev, i + smp_cpus,
1332	qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
1333	sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
1334	qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
1335	sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
1336	qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
1337
1338	if (vms->gic_version != VIRT_GIC_VERSION_2) {
1339	sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
1340	qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
1341	sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
1342	qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
1343	}
1344	}
1345	}
1346
1347	static void create_gicv2(VirtMachineState vms, MemoryRegion mem)
1348	{
1349	MachineState *ms = MACHINE(vms);
1350	/* We create a standalone GIC */
1351	SysBusDevice *gicbusdev;
1352	unsigned int smp_cpus = ms->smp.cpus;
1353
1354	if (kvm_enabled() && vms->virt) {
1355	error_report("KVM EL2 is only supported with in-kernel GICv3");
1356	exit(1);
1357	}
1358
1359	vms->gic = qdev_new(gic_class_name());
1360	qdev_prop_set_uint32(vms->gic, "revision", 2);
1361	qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
1362	/*
1363	* Note that the num-irq property counts both internal and external
1364	* interrupts; there are always 32 of the former (mandated by GIC spec).
1365	*/
1366	qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
1367	if (!kvm_irqchip_in_kernel()) {
1368	qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
1369	qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt);
1370	}
1371
1372	gicbusdev = SYS_BUS_DEVICE(vms->gic);
1373	sysbus_realize_and_unref(gicbusdev, &error_fatal);
1374	sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
1375	sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
1376	if (vms->virt) {
1377	sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
1378	sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
1379	}
1380
1381	gic_connect_ppis(vms);
1382
1383	fdt_add_gic_node(vms);
1384	}
1385
1386	static void create_gicv3(VirtMachineState vms, MemoryRegion mem)
1387	{
1388	MachineState *ms = MACHINE(vms);
1389	/* We create a standalone GIC */
1390	SysBusDevice *gicbusdev;
1391	unsigned int smp_cpus = ms->smp.cpus;
1392	uint32_t nb_redist_regions;
1393	int revision;
1394	QList *redist_region_count;
1395	uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
1396	uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
1397
1398	switch (vms->gic_version) {
1399	case VIRT_GIC_VERSION_3:
1400	revision = 3;
1401	break;
1402	case VIRT_GIC_VERSION_4:
1403	revision = 4;
1404	break;
1405	default:
1406	g_assert_not_reached();
1407	}
1408
1409	if (kvm_enabled() && vms->virt &&
1410	(revision != 3 \|\| !kvm_irqchip_in_kernel())) {
1411	error_report("KVM EL2 is only supported with in-kernel GICv3");
1412	exit(1);
1413	}
1414
1415	vms->gic = qdev_new(gicv3_class_name());
1416	qdev_prop_set_uint32(vms->gic, "revision", revision);
1417	qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
1418	/*
1419	* Note that the num-irq property counts both internal and external
1420	* interrupts; there are always 32 of the former (mandated by GIC spec).
1421	*/
1422	qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
1423	if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) {
1424	qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
1425	}
1426
1427	nb_redist_regions = virt_gicv3_redist_region_count(vms);
1428
1429	redist_region_count = qlist_new();
1430	qlist_append_int(redist_region_count, redist0_count);
1431	if (nb_redist_regions == 2) {
1432	uint32_t redist1_capacity =
1433	virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
1434
1435	qlist_append_int(redist_region_count,
1436	MIN(smp_cpus - redist0_count, redist1_capacity));
1437	}
1438	qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count);
1439
1440	if (!kvm_irqchip_in_kernel() &&
1441	!(hvf_enabled() && hvf_irqchip_in_kernel())) {
1442	if (vms->tcg_its) {
1443	object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem),
1444	&error_fatal);
1445	qdev_prop_set_bit(vms->gic, "has-lpi", true);
1446	}
1447	} else if (vms->virt) {
1448	qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id",
1449	ARCH_GIC_MAINT_IRQ);
1450	}
1451
1452	if (gicv3_nmi_present(vms)) {
1453	qdev_prop_set_bit(vms->gic, "has-nmi", true);
1454	}
1455
1456	gicbusdev = SYS_BUS_DEVICE(vms->gic);
1457	sysbus_realize_and_unref(gicbusdev, &error_fatal);
1458	sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
1459	sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
1460	if (nb_redist_regions == 2) {
1461	sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
1462	}
1463
1464	gic_connect_ppis(vms);
1465
1466	fdt_add_gic_node(vms);
1467	}
1468
1469	static void create_gic(VirtMachineState vms, MemoryRegion mem)
1470	{
1471	switch (vms->gic_version) {
1472	case VIRT_GIC_VERSION_2:
1473	create_gicv2(vms, mem);
1474	break;
1475	case VIRT_GIC_VERSION_3:
1476	case VIRT_GIC_VERSION_4:
1477	create_gicv3(vms, mem);
1478	break;
1479	case VIRT_GIC_VERSION_5:
1480	create_gicv5(vms, mem);
1481	break;
1482	default:
1483	g_assert_not_reached();
1484	}
1485	}
1486
1487	static void create_msi_controller(VirtMachineState *vms)
1488	{
1489	switch (vms->msi_controller) {
1490	case VIRT_MSI_CTRL_ITS:
1491	create_its(vms);
1492	break;
1493	case VIRT_MSI_CTRL_GICV2M:
1494	create_v2m(vms);
1495	break;
1496	case VIRT_MSI_CTRL_NONE:
1497	break;
1498	default:
1499	g_assert_not_reached();
1500	}
1501	}
1502
1503	static void create_uart(const VirtMachineState *vms, int uart,
1504	MemoryRegion mem, Chardev chr, bool secure)
1505	{
1506	char *nodename;
1507	hwaddr base = vms->memmap[uart].base;
1508	hwaddr size = vms->memmap[uart].size;
1509	int irq = vms->irqmap[uart];
1510	const char compat[] = "arm,pl011\0arm,primecell";
1511	const char clocknames[] = "uartclk\0apb_pclk";
1512	DeviceState *dev = qdev_new(TYPE_PL011);
1513	SysBusDevice *s = SYS_BUS_DEVICE(dev);
1514	MachineState *ms = MACHINE(vms);
1515
1516	qdev_prop_set_chr(dev, "chardev", chr);
1517	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1518	memory_region_add_subregion(mem, base,
1519	sysbus_mmio_get_region(s, 0));
1520	sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1521
1522	nodename = g_strdup_printf("/pl011@%" PRIx64, base);
1523	qemu_fdt_add_subnode(ms->fdt, nodename);
1524	/* Note that we can't use setprop_string because of the embedded NUL */
1525	qemu_fdt_setprop(ms->fdt, nodename, "compatible",
1526	compat, sizeof(compat));
1527	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1528	2, base, 2, size);
1529	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1530	gic_fdt_irq_type_spi(vms), irq,
1531	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1532	qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
1533	vms->clock_phandle, vms->clock_phandle);
1534	qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
1535	clocknames, sizeof(clocknames));
1536
1537	if (uart == VIRT_UART0) {
1538	qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
1539	qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
1540	} else {
1541	qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
1542	}
1543	if (secure) {
1544	/* Mark as not usable by the normal world */
1545	qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1546	qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1547
1548	qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
1549	nodename);
1550	}
1551
1552	g_free(nodename);
1553	}
1554
1555	static void create_rtc(const VirtMachineState *vms)
1556	{
1557	char *nodename;
1558	hwaddr base = vms->memmap[VIRT_RTC].base;
1559	hwaddr size = vms->memmap[VIRT_RTC].size;
1560	int irq = vms->irqmap[VIRT_RTC];
1561	const char compat[] = "arm,pl031\0arm,primecell";
1562	MachineState *ms = MACHINE(vms);
1563
1564	sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
1565
1566	nodename = g_strdup_printf("/pl031@%" PRIx64, base);
1567	qemu_fdt_add_subnode(ms->fdt, nodename);
1568	qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1569	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1570	2, base, 2, size);
1571	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1572	gic_fdt_irq_type_spi(vms), irq,
1573	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1574	qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1575	qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1576	g_free(nodename);
1577	}
1578
1579	static DeviceState *gpio_key_dev;
1580	static void virt_powerdown_req(Notifier n, void opaque)
1581	{
1582	VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1583
1584	if (s->acpi_dev) {
1585	acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1586	} else {
1587	/* use gpio Pin for power button event */
1588	qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1589	}
1590	}
1591
1592	static void virt_generic_error_req(Notifier n, void opaque)
1593	{
1594	uint16_t *source_id = opaque;
1595
1596	/* Currently, only QMP source ID is async */
1597	if (*source_id != ACPI_HEST_SRC_ID_QMP) {
1598	return;
1599	}
1600
1601	VirtMachineState *s = container_of(n, VirtMachineState, generic_error_notifier);
1602
1603	acpi_send_event(s->acpi_dev, ACPI_GENERIC_ERROR);
1604	}
1605
1606	static void create_gpio_keys(char fdt, DeviceState pl061_dev,
1607	uint32_t phandle)
1608	{
1609	gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1610	qdev_get_gpio_in(pl061_dev,
1611	GPIO_PIN_POWER_BUTTON));
1612
1613	qemu_fdt_add_subnode(fdt, "/gpio-keys");
1614	qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1615
1616	qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1617	qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1618	"label", "GPIO Key Poweroff");
1619	qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1620	KEY_POWER);
1621	qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1622	"gpios", phandle, GPIO_PIN_POWER_BUTTON, 0);
1623	}
1624
1625	#define SECURE_GPIO_POWEROFF 0
1626	#define SECURE_GPIO_RESET 1
1627
1628	static void create_secure_gpio_pwr(char fdt, DeviceState pl061_dev,
1629	uint32_t phandle)
1630	{
1631	DeviceState *gpio_pwr_dev;
1632
1633	/* gpio-pwr */
1634	gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1635
1636	/* connect secure pl061 to gpio-pwr */
1637	qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1638	qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1639	qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1640	qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1641
1642	qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1643	qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1644	"gpio-poweroff");
1645	qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1646	"gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1647	qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1648	qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1649	"okay");
1650
1651	qemu_fdt_add_subnode(fdt, "/gpio-restart");
1652	qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1653	"gpio-restart");
1654	qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1655	"gpios", phandle, SECURE_GPIO_RESET, 0);
1656	qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1657	qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1658	"okay");
1659	}
1660
1661	static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1662	MemoryRegion *mem)
1663	{
1664	char *nodename;
1665	DeviceState *pl061_dev;
1666	hwaddr base = vms->memmap[gpio].base;
1667	hwaddr size = vms->memmap[gpio].size;
1668	int irq = vms->irqmap[gpio];
1669	const char compat[] = "arm,pl061\0arm,primecell";
1670	SysBusDevice *s;
1671	MachineState *ms = MACHINE(vms);
1672
1673	pl061_dev = qdev_new("pl061");
1674	/* Pull lines down to 0 if not driven by the PL061 */
1675	qdev_prop_set_uint8(pl061_dev, "pullups", 0);
1676	qdev_prop_set_uint8(pl061_dev, "pulldowns", 0xff);
1677	s = SYS_BUS_DEVICE(pl061_dev);
1678	sysbus_realize_and_unref(s, &error_fatal);
1679	memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1680	sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1681
1682	uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1683	nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1684	qemu_fdt_add_subnode(ms->fdt, nodename);
1685	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1686	2, base, 2, size);
1687	qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1688	qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1689	qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1690	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1691	gic_fdt_irq_type_spi(vms), irq,
1692	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1693	qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1694	qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1695	qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1696
1697	if (gpio != VIRT_GPIO) {
1698	/* Mark as not usable by the normal world */
1699	qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1700	qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1701	}
1702	g_free(nodename);
1703
1704	/* Child gpio devices */
1705	if (gpio == VIRT_GPIO) {
1706	create_gpio_keys(ms->fdt, pl061_dev, phandle);
1707	} else {
1708	create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1709	}
1710	}
1711
1712	static void create_virtio_devices(const VirtMachineState *vms)
1713	{
1714	int i;
1715	hwaddr size = vms->memmap[VIRT_MMIO].size;
1716	MachineState *ms = MACHINE(vms);
1717
1718	/* We create the transports in forwards order. Since qbus_realize()
1719	* prepends (not appends) new child buses, the incrementing loop below will
1720	* create a list of virtio-mmio buses with decreasing base addresses.
1721	*
1722	* When a -device option is processed from the command line,
1723	* qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1724	* order. The upshot is that -device options in increasing command line
1725	* order are mapped to virtio-mmio buses with decreasing base addresses.
1726	*
1727	* When this code was originally written, that arrangement ensured that the
1728	* guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1729	* the first -device on the command line. (The end-to-end order is a
1730	* function of this loop, qbus_realize(), qbus_find_recursive(), and the
1731	* guest kernel's name-to-address assignment strategy.)
1732	*
1733	* Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1734	* the message, if not necessarily the code, of commit 70161ff336.
1735	* Therefore the loop now establishes the inverse of the original intent.
1736	*
1737	* Unfortunately, we can't counteract the kernel change by reversing the
1738	* loop; it would break existing command lines.
1739	*
1740	* In any case, the kernel makes no guarantee about the stability of
1741	* enumeration order of virtio devices (as demonstrated by it changing
1742	* between kernel versions). For reliable and stable identification
1743	* of disks users must use UUIDs or similar mechanisms.
1744	*/
1745	for (i = 0; i < vms->virtio_transports; i++) {
1746	int irq = vms->irqmap[VIRT_MMIO] + i;
1747	hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1748
1749	sysbus_create_simple("virtio-mmio", base,
1750	qdev_get_gpio_in(vms->gic, irq));
1751	}
1752
1753	/* We add dtb nodes in reverse order so that they appear in the finished
1754	* device tree lowest address first.
1755	*
1756	* Note that this mapping is independent of the loop above. The previous
1757	* loop influences virtio device to virtio transport assignment, whereas
1758	* this loop controls how virtio transports are laid out in the dtb.
1759	*/
1760	for (i = vms->virtio_transports - 1; i >= 0; i--) {
1761	char *nodename;
1762	int irq = vms->irqmap[VIRT_MMIO] + i;
1763	hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1764
1765	nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1766	qemu_fdt_add_subnode(ms->fdt, nodename);
1767	qemu_fdt_setprop_string(ms->fdt, nodename,
1768	"compatible", "virtio,mmio");
1769	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1770	2, base, 2, size);
1771	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1772	gic_fdt_irq_type_spi(vms), irq,
1773	GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1774	qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1775	g_free(nodename);
1776	}
1777	}
1778
1779	#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1780
1781	static PFlashCFI01 virt_flash_create1(VirtMachineState vms,
1782	const char *name,
1783	const char *alias_prop_name)
1784	{
1785	/*
1786	* Create a single flash device. We use the same parameters as
1787	* the flash devices on the Versatile Express board.
1788	*/
1789	DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1790
1791	qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1792	qdev_prop_set_uint8(dev, "width", 4);
1793	qdev_prop_set_uint8(dev, "device-width", 2);
1794	qdev_prop_set_bit(dev, "big-endian", false);
1795	qdev_prop_set_uint16(dev, "id0", 0x89);
1796	qdev_prop_set_uint16(dev, "id1", 0x18);
1797	qdev_prop_set_uint16(dev, "id2", 0x00);
1798	qdev_prop_set_uint16(dev, "id3", 0x00);
1799	qdev_prop_set_string(dev, "name", name);
1800	object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1801	object_property_add_alias(OBJECT(vms), alias_prop_name,
1802	OBJECT(dev), "drive");
1803	return PFLASH_CFI01(dev);
1804	}
1805
1806	static void virt_flash_create(VirtMachineState *vms)
1807	{
1808	vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1809	vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1810	}
1811
1812	static void virt_flash_map1(PFlashCFI01 *flash,
1813	hwaddr base, hwaddr size,
1814	MemoryRegion *sysmem)
1815	{
1816	DeviceState *dev = DEVICE(flash);
1817
1818	assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1819	assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1820	qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1821	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1822
1823	memory_region_add_subregion(sysmem, base,
1824	sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1825	0));
1826	}
1827
1828	static void virt_flash_map(VirtMachineState *vms,
1829	MemoryRegion *sysmem,
1830	MemoryRegion *secure_sysmem)
1831	{
1832	/*
1833	* Map two flash devices to fill the VIRT_FLASH space in the memmap.
1834	* sysmem is the system memory space. secure_sysmem is the secure view
1835	* of the system, and the first flash device should be made visible only
1836	* there. The second flash device is visible to both secure and nonsecure.
1837	* If sysmem == secure_sysmem this means there is no separate Secure
1838	* address space and both flash devices are generally visible.
1839	*/
1840	hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1841	hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1842
1843	virt_flash_map1(vms->flash[0], flashbase, flashsize,
1844	secure_sysmem);
1845	virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1846	sysmem);
1847	}
1848
1849	static void virt_flash_fdt(VirtMachineState *vms,
1850	MemoryRegion *sysmem,
1851	MemoryRegion *secure_sysmem)
1852	{
1853	hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1854	hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1855	MachineState *ms = MACHINE(vms);
1856	char *nodename;
1857
1858	if (sysmem == secure_sysmem) {
1859	/* Report both flash devices as a single node in the DT */
1860	nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1861	qemu_fdt_add_subnode(ms->fdt, nodename);
1862	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1863	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1864	2, flashbase, 2, flashsize,
1865	2, flashbase + flashsize, 2, flashsize);
1866	qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1867	g_free(nodename);
1868	} else {
1869	/*
1870	* Report the devices as separate nodes so we can mark one as
1871	* only visible to the secure world.
1872	*/
1873	nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1874	qemu_fdt_add_subnode(ms->fdt, nodename);
1875	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1876	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1877	2, flashbase, 2, flashsize);
1878	qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1879	qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1880	qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1881	g_free(nodename);
1882
1883	nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1884	qemu_fdt_add_subnode(ms->fdt, nodename);
1885	qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1886	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1887	2, flashbase + flashsize, 2, flashsize);
1888	qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1889	g_free(nodename);
1890	}
1891	}
1892
1893	static bool virt_firmware_init(VirtMachineState *vms,
1894	MemoryRegion *sysmem,
1895	MemoryRegion *secure_sysmem)
1896	{
1897	int i;
1898	const char *bios_name;
1899	BlockBackend *pflash_blk0;
1900
1901	/* Map legacy -drive if=pflash to machine properties */
1902	for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1903	pflash_cfi01_legacy_drive(vms->flash[i],
1904	drive_get(IF_PFLASH, 0, i));
1905	}
1906
1907	virt_flash_map(vms, sysmem, secure_sysmem);
1908
1909	pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1910
1911	bios_name = MACHINE(vms)->firmware;
1912	if (bios_name) {
1913	char *fname;
1914	MemoryRegion *mr;
1915	int image_size;
1916
1917	if (pflash_blk0) {
1918	error_report("The contents of the first flash device may be "
1919	"specified with -bios or with -drive if=pflash... "
1920	"but you cannot use both options at once");
1921	exit(1);
1922	}
1923
1924	/* Fall back to -bios */
1925
1926	fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1927	if (!fname) {
1928	error_report("Could not find ROM image '%s'", bios_name);
1929	exit(1);
1930	}
1931	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1932	image_size = load_image_mr(fname, mr);
1933	g_free(fname);
1934	if (image_size < 0) {
1935	error_report("Could not load ROM image '%s'", bios_name);
1936	exit(1);
1937	}
1938	}
1939
1940	return pflash_blk0 \|\| bios_name;
1941	}
1942
1943	static FWCfgState create_fw_cfg(const VirtMachineState vms, AddressSpace *as)
1944	{
1945	MachineState *ms = MACHINE(vms);
1946	hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1947	hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1948	FWCfgState *fw_cfg;
1949	char *nodename;
1950
1951	fw_cfg = fw_cfg_init_mem_dma(base, as);
1952	fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1953
1954	nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1955	qemu_fdt_add_subnode(ms->fdt, nodename);
1956	qemu_fdt_setprop_string(ms->fdt, nodename,
1957	"compatible", "qemu,fw-cfg-mmio");
1958	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1959	2, base, 2, size);
1960	qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1961	g_free(nodename);
1962	return fw_cfg;
1963	}
1964
1965	static void create_pcie_irq_map(const MachineState *ms,
1966	uint32_t gic_phandle,
1967	int first_irq, const char *nodename)
1968	{
1969	int devfn, pin;
1970	uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1971	uint32_t *irq_map = full_irq_map;
1972	const VirtMachineState *vms = VIRT_MACHINE(ms);
1973
1974	for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1975	for (pin = 0; pin < 4; pin++) {
1976	int irq_type = gic_fdt_irq_type_spi(vms);
1977	int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1978	int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1979	int i;
1980
1981	uint32_t map[] = {
1982	devfn << 8, 0, 0, /* devfn */
1983	pin + 1, /* PCI pin */
1984	gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1985
1986	/* Convert map to big endian */
1987	for (i = 0; i < 10; i++) {
1988	irq_map[i] = cpu_to_be32(map[i]);
1989	}
1990	irq_map += 10;
1991	}
1992	}
1993
1994	qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1995	full_irq_map, sizeof(full_irq_map));
1996
1997	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1998	cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1999	0, 0,
2000	0x7 /* PCI irq */);
2001	}
2002
2003	static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr base,
2004	hwaddr size, int irq)
2005	{
2006	char *node;
2007	const char compat[] = "arm,smmu-v3";
2008	const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
2009	MachineState *ms = MACHINE(vms);
2010
2011	node = g_strdup_printf("/smmuv3@%" PRIx64, base);
2012	qemu_fdt_add_subnode(ms->fdt, node);
2013	qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
2014	qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
2015
2016	qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
2017	gic_fdt_irq_type_spi(vms), irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
2018	gic_fdt_irq_type_spi(vms), irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
2019	gic_fdt_irq_type_spi(vms), irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
2020	gic_fdt_irq_type_spi(vms), irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
2021
2022	qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
2023	sizeof(irq_names));
2024
2025	qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
2026	qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
2027	qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
2028	g_free(node);
2029	}
2030
2031	static void create_smmuv3_dev_dtb(VirtMachineState vms, DeviceState dev,
2032	PCIBus bus, Error *errp)
2033	{
2034	PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
2035	SysBusDevice *sbdev = SYS_BUS_DEVICE(dev);
2036	int irq = platform_bus_get_irqn(pbus, sbdev, 0);
2037	hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
2038	MachineState *ms = MACHINE(vms);
2039
2040	if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))) {
2041	if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) {
2042	error_setg(errp, "SMMUv3 with accel=on not supported for DT");
2043	return;
2044	}
2045	if (strcmp("pcie.0", bus->qbus.name)) {
2046	warn_report("SMMUv3 device only supported with pcie.0 for DT");
2047	return;
2048	}
2049	}
2050	base += vms->memmap[VIRT_PLATFORM_BUS].base;
2051	irq += vms->irqmap[VIRT_PLATFORM_BUS];
2052
2053	vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
2054	create_smmuv3_dt_bindings(vms, base, SMMU_IO_LEN, irq);
2055	qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
2056	0x0, vms->iommu_phandle, 0x0, 0x10000);
2057	}
2058
2059	static void create_smmu(const VirtMachineState vms, PCIBus bus)
2060	{
2061	VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2062	int irq = vms->irqmap[VIRT_SMMU];
2063	int i;
2064	hwaddr base = vms->memmap[VIRT_SMMU].base;
2065	hwaddr size = vms->memmap[VIRT_SMMU].size;
2066	DeviceState *dev;
2067
2068	if (vms->iommu != VIRT_IOMMU_SMMUV3 \|\| !vms->iommu_phandle) {
2069	return;
2070	}
2071
2072	dev = qdev_new(TYPE_ARM_SMMUV3);
2073
2074	if (!vmc->no_nested_smmu) {
2075	object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
2076	}
2077	object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
2078	&error_abort);
2079	object_property_set_link(OBJECT(dev), "memory", OBJECT(vms->sysmem),
2080	&error_abort);
2081	object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem),
2082	&error_abort);
2083	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2084	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
2085	for (i = 0; i < NUM_SMMU_IRQS; i++) {
2086	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
2087	qdev_get_gpio_in(vms->gic, irq + i));
2088	}
2089	create_smmuv3_dt_bindings(vms, base, size, irq);
2090	}
2091
2092	static void create_gwdt_dt_bindings(VirtMachineState *vms)
2093	{
2094	MachineState *ms = MACHINE(vms);
2095	hwaddr rbase = vms->memmap[VIRT_GWDT_REFRESH].base;
2096	hwaddr cbase = vms->memmap[VIRT_GWDT_CONTROL].base;
2097	int irq = vms->irqmap[VIRT_GWDT_WS0];
2098	char *nodename = g_strdup_printf("/watchdog@%" PRIx64, cbase);
2099
2100	qemu_fdt_add_subnode(ms->fdt, nodename);
2101	qemu_fdt_setprop_string(ms->fdt, nodename,
2102	"compatible", "arm,sbsa-gwdt");
2103	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2104	2, cbase, 2, SBSA_GWDT_CMMIO_SIZE,
2105	2, rbase, 2, SBSA_GWDT_RMMIO_SIZE);
2106	qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
2107	GIC_FDT_IRQ_TYPE_SPI, irq,
2108	GIC_FDT_IRQ_FLAGS_LEVEL_HI);
2109	qemu_fdt_setprop_cell(ms->fdt, nodename, "timeout-sec", 30);
2110	g_free(nodename);
2111	}
2112
2113	static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
2114	{
2115	const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
2116	uint16_t bdf = vms->virtio_iommu_bdf;
2117	MachineState *ms = MACHINE(vms);
2118	char *node;
2119
2120	vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
2121
2122	node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
2123	PCI_SLOT(bdf), PCI_FUNC(bdf));
2124	qemu_fdt_add_subnode(ms->fdt, node);
2125	qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
2126	qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
2127	1, bdf << 8, 1, 0, 1, 0,
2128	1, 0, 1, 0);
2129
2130	qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
2131	qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
2132	g_free(node);
2133
2134	if (!vms->default_bus_bypass_iommu) {
2135	qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
2136	0x0, vms->iommu_phandle, 0x0, bdf,
2137	bdf + 1, vms->iommu_phandle, bdf + 1,
2138	0xffff - bdf);
2139	}
2140	}
2141
2142	static void create_pcie(VirtMachineState *vms)
2143	{
2144	hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
2145	hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
2146	hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
2147	hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
2148	hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
2149	hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
2150	hwaddr base_ecam, size_ecam;
2151	hwaddr base = base_mmio;
2152	int nr_pcie_buses;
2153	int irq = vms->irqmap[VIRT_PCIE];
2154	MemoryRegion *mmio_alias;
2155	MemoryRegion *mmio_reg;
2156	MemoryRegion *ecam_alias;
2157	MemoryRegion *ecam_reg;
2158	DeviceState *dev;
2159	char *nodename;
2160	int i, ecam_id;
2161	PCIHostState *pci;
2162	MachineState *ms = MACHINE(vms);
2163	MachineClass *mc = MACHINE_GET_CLASS(ms);
2164
2165	dev = qdev_new(TYPE_GPEX_HOST);
2166	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2167
2168	ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
2169	base_ecam = vms->memmap[ecam_id].base;
2170	size_ecam = vms->memmap[ecam_id].size;
2171	nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
2172	/* Map only the first size_ecam bytes of ECAM space */
2173	ecam_alias = g_new0(MemoryRegion, 1);
2174	ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
2175	memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
2176	ecam_reg, 0, size_ecam);
2177	memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
2178	vms->sysmem = get_system_memory();
2179
2180	/* Map the MMIO window into system address space so as to expose
2181	* the section of PCI MMIO space which starts at the same base address
2182	* (ie 1:1 mapping for that part of PCI MMIO space visible through
2183	* the window).
2184	*/
2185	mmio_alias = g_new0(MemoryRegion, 1);
2186	mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
2187	memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
2188	mmio_reg, base_mmio, size_mmio);
2189	memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
2190
2191	if (vms->highmem_mmio) {
2192	/* Map high MMIO space */
2193	MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
2194
2195	memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
2196	mmio_reg, base_mmio_high, size_mmio_high);
2197	memory_region_add_subregion(get_system_memory(), base_mmio_high,
2198	high_mmio_alias);
2199	}
2200
2201	/* Map IO port space */
2202	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
2203
2204	for (i = 0; i < PCI_NUM_PINS; i++) {
2205	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
2206	qdev_get_gpio_in(vms->gic, irq + i));
2207	gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
2208	}
2209
2210	pci = PCI_HOST_BRIDGE(dev);
2211	pci->bypass_iommu = vms->default_bus_bypass_iommu;
2212	vms->bus = pci->bus;
2213	if (vms->bus) {
2214	pci_init_nic_devices(pci->bus, mc->default_nic);
2215	}
2216
2217	nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
2218	qemu_fdt_add_subnode(ms->fdt, nodename);
2219	qemu_fdt_setprop_string(ms->fdt, nodename,
2220	"compatible", "pci-host-ecam-generic");
2221	qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
2222	qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
2223	qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
2224	qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
2225	qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
2226	nr_pcie_buses - 1);
2227	qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
2228
2229	if (vms->msi_phandle) {
2230	qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
2231	0, vms->msi_phandle, 0, 0x10000);
2232	}
2233
2234	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2235	2, base_ecam, 2, size_ecam);
2236
2237	if (vms->highmem_mmio) {
2238	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
2239	1, FDT_PCI_RANGE_IOPORT, 2, 0,
2240	2, base_pio, 2, size_pio,
2241	1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
2242	2, base_mmio, 2, size_mmio,
2243	1, FDT_PCI_RANGE_MMIO_64BIT,
2244	2, base_mmio_high,
2245	2, base_mmio_high, 2, size_mmio_high);
2246	} else {
2247	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
2248	1, FDT_PCI_RANGE_IOPORT, 2, 0,
2249	2, base_pio, 2, size_pio,
2250	1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
2251	2, base_mmio, 2, size_mmio);
2252	}
2253
2254	qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
2255	create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
2256
2257	if (vms->iommu) {
2258	vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
2259
2260	switch (vms->iommu) {
2261	case VIRT_IOMMU_SMMUV3:
2262	create_smmu(vms, vms->bus);
2263	if (!vms->default_bus_bypass_iommu) {
2264	qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
2265	0x0, vms->iommu_phandle, 0x0, 0x10000);
2266	}
2267	vms->legacy_smmuv3_present = true;
2268	break;
2269	default:
2270	g_assert_not_reached();
2271	}
2272	}
2273	}
2274
2275	static void create_cxl_host_reg_region(VirtMachineState *vms)
2276	{
2277	MemoryRegion *sysmem = get_system_memory();
2278	MemoryRegion *mr = &vms->cxl_devices_state.host_mr;
2279
2280	memory_region_init(mr, OBJECT(vms), "cxl_host_reg",
2281	vms->memmap[VIRT_CXL_HOST].size);
2282	memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr);
2283	vms->highmem_cxl = true;
2284	}
2285
2286	static void create_platform_bus(VirtMachineState *vms)
2287	{
2288	DeviceState *dev;
2289	SysBusDevice *s;
2290	int i;
2291	MemoryRegion *sysmem = get_system_memory();
2292
2293	dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
2294	dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
2295	qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
2296	qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
2297	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2298	vms->platform_bus_dev = dev;
2299
2300	s = SYS_BUS_DEVICE(dev);
2301	for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
2302	int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
2303	sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
2304	}
2305
2306	memory_region_add_subregion(sysmem,
2307	vms->memmap[VIRT_PLATFORM_BUS].base,
2308	sysbus_mmio_get_region(s, 0));
2309	}
2310
2311	static void create_tag_ram(MemoryRegion *tag_sysmem,
2312	hwaddr base, hwaddr size,
2313	const char *name)
2314	{
2315	MemoryRegion *tagram = g_new(MemoryRegion, 1);
2316
2317	memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
2318	memory_region_add_subregion(tag_sysmem, base / 32, tagram);
2319	}
2320
2321	static void create_secure_ram(VirtMachineState *vms,
2322	MemoryRegion *secure_sysmem,
2323	MemoryRegion *secure_tag_sysmem)
2324	{
2325	MemoryRegion *secram = g_new(MemoryRegion, 1);
2326	char *nodename;
2327	hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
2328	hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
2329	MachineState *ms = MACHINE(vms);
2330
2331	memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
2332	&error_fatal);
2333	memory_region_add_subregion(secure_sysmem, base, secram);
2334
2335	nodename = g_strdup_printf("/secram@%" PRIx64, base);
2336	qemu_fdt_add_subnode(ms->fdt, nodename);
2337	qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
2338	qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
2339	qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
2340	qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
2341
2342	if (secure_tag_sysmem) {
2343	create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
2344	}
2345
2346	g_free(nodename);
2347	}
2348
2349	static void machvirt_dtb(const struct arm_boot_info binfo, int *fdt_size)
2350	{
2351	const VirtMachineState *board = container_of(binfo, VirtMachineState,
2352	bootinfo);
2353	MachineState *ms = MACHINE(board);
2354
2355
2356	*fdt_size = board->fdt_size;
2357	return ms->fdt;
2358	}
2359
2360	static void virt_build_smbios(VirtMachineState *vms)
2361	{
2362	MachineClass *mc = MACHINE_GET_CLASS(vms);
2363	MachineState *ms = MACHINE(vms);
2364	uint8_t smbios_tables, smbios_anchor;
2365	size_t smbios_tables_len, smbios_anchor_len;
2366	struct smbios_phys_mem_area mem_array;
2367	const char *product = "QEMU Virtual Machine";
2368
2369	if (kvm_enabled()) {
2370	product = "KVM Virtual Machine";
2371	}
2372
2373	smbios_set_defaults("QEMU", product, mc->name);
2374
2375	/* build the array of physical mem area from base_memmap */
2376	mem_array.address = vms->memmap[VIRT_MEM].base;
2377	mem_array.length = ms->ram_size;
2378
2379	smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
2380	&smbios_tables, &smbios_tables_len,
2381	&smbios_anchor, &smbios_anchor_len,
2382	&error_fatal);
2383
2384	if (smbios_anchor) {
2385	fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
2386	smbios_tables, smbios_tables_len);
2387	fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
2388	smbios_anchor, smbios_anchor_len);
2389	}
2390	}
2391
2392	/*
2393	* SMMUv3 devices with acceleration may enable CMDQV extensions
2394	* after device realize. In that case, additional MMIO regions and
2395	* IRQ lines may be registered but not yet mapped to the platform bus.
2396	*
2397	* Ensure all resources are linked to the platform bus before final
2398	* machine setup.
2399	*/
2400
2401	static void virt_smmuv3_dev_link_cmdqv(VirtMachineState *vms)
2402	{
2403	for (int i = 0; i < vms->smmuv3_devices->len; i++) {
2404	DeviceState *dev = g_ptr_array_index(vms->smmuv3_devices, i);
2405
2406	platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2407	SYS_BUS_DEVICE(dev));
2408	}
2409	}
2410
2411	static
2412	void virt_machine_done(Notifier notifier, void data)
2413	{
2414	VirtMachineState *vms = container_of(notifier, VirtMachineState,
2415	machine_done);
2416	MachineState *ms = MACHINE(vms);
2417	ARMCPU *cpu = ARM_CPU(first_cpu);
2418	struct arm_boot_info *info = &vms->bootinfo;
2419	AddressSpace *as = arm_boot_address_space(cpu, info);
2420
2421	cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state,
2422	&error_fatal);
2423
2424	if (vms->cxl_devices_state.is_enabled) {
2425	cxl_fmws_link_targets(&error_fatal);
2426	}
2427
2428	virt_smmuv3_dev_link_cmdqv(vms);
2429
2430	/*
2431	* If the user provided a dtb, we assume the dynamic sysbus nodes
2432	* already are integrated there. This corresponds to a use case where
2433	* the dynamic sysbus nodes are complex and their generation is not yet
2434	* supported. In that case the user can take charge of the guest dt
2435	* while qemu takes charge of the qom stuff.
2436	*/
2437	if (info->dtb_filename == NULL) {
2438	platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
2439	vms->memmap[VIRT_PLATFORM_BUS].base,
2440	vms->memmap[VIRT_PLATFORM_BUS].size,
2441	vms->irqmap[VIRT_PLATFORM_BUS]);
2442	}
2443	if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
2444	exit(1);
2445	}
2446
2447	pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,
2448	&error_abort);
2449
2450	virt_acpi_setup(vms);
2451	virt_build_smbios(vms);
2452	}
2453
2454	static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
2455	{
2456	uint8_t clustersz;
2457
2458	/*
2459	* Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)
2460	* and to improve SGI efficiency.
2461	* - GICv2 only supports 8 CPUs anyway
2462	* - GICv3 wants 16 CPUs per Aff0 because of an ICC_SGIxR
2463	* register limitation
2464	* - GICv5 has no restrictions, so we retain the GICv3 16-per-Aff0
2465	* layout because that's what KVM does
2466	*/
2467	if (vms->gic_version == VIRT_GIC_VERSION_2) {
2468	clustersz = GIC_TARGETLIST_BITS;
2469	} else {
2470	clustersz = GICV3_TARGETLIST_BITS;
2471	}
2472
2473	return arm_build_mp_affinity(idx, clustersz);
2474	}
2475
2476	static inline bool virt_get_high_memmap_enabled(VirtMachineState vms,
2477	int index)
2478	{
2479	bool *enabled_array[] = {
2480	&vms->highmem_redists,
2481	&vms->highmem_cxl,
2482	&vms->highmem_ecam,
2483	&vms->highmem_mmio,
2484	};
2485
2486	assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
2487	ARRAY_SIZE(enabled_array));
2488	assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
2489
2490	return enabled_array[index - VIRT_LOWMEMMAP_LAST];
2491	}
2492
2493	static void virt_set_high_memmap(VirtMachineState *vms,
2494	hwaddr base, int pa_bits)
2495	{
2496	hwaddr region_base, region_size;
2497	bool *region_enabled, fits;
2498	int i;
2499
2500	for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
2501	region_enabled = virt_get_high_memmap_enabled(vms, i);
2502	region_base = ROUND_UP(base, extended_memmap[i].size);
2503	region_size = extended_memmap[i].size;
2504
2505	vms->memmap[i].base = region_base;
2506	vms->memmap[i].size = region_size;
2507
2508	/*
2509	* Check each device to see if it fits in the PA space,
2510	* moving highest_gpa as we go. For compatibility, move
2511	* highest_gpa for disabled fitting devices as well, if
2512	* the compact layout has been disabled.
2513	*
2514	* For each device that doesn't fit, disable it.
2515	*/
2516	fits = (region_base + region_size) <= BIT_ULL(pa_bits);
2517	*region_enabled &= fits;
2518	if (vms->highmem_compact && !*region_enabled) {
2519	continue;
2520	}
2521
2522	base = region_base + region_size;
2523	if (fits) {
2524	vms->highest_gpa = base - 1;
2525	}
2526	}
2527	}
2528
2529	static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
2530	{
2531	MachineState *ms = MACHINE(vms);
2532	hwaddr base, device_memory_base, device_memory_size, memtop;
2533	int i;
2534
2535	vms->memmap = extended_memmap;
2536
2537	for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
2538	vms->memmap[i] = base_memmap[i];
2539	}
2540
2541	if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
2542	error_report("unsupported number of memory slots: %"PRIu64,
2543	ms->ram_slots);
2544	exit(EXIT_FAILURE);
2545	}
2546
2547	/*
2548	* !highmem is exactly the same as limiting the PA space to 32bit,
2549	* irrespective of the underlying capabilities of the HW.
2550	*/
2551	if (!vms->highmem) {
2552	pa_bits = 32;
2553	}
2554
2555	/*
2556	* We compute the base of the high IO region depending on the
2557	* amount of initial and device memory. The device memory start/size
2558	* is aligned on 1GiB. We never put the high IO region below 256GiB
2559	* so that if maxram_size is < 255GiB we keep the legacy memory map.
2560	* The device region size assumes 1GiB page max alignment per slot.
2561	*/
2562	device_memory_base =
2563	ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
2564	device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
2565
2566	/* Base address of the high IO region */
2567	memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
2568	if (memtop > BIT_ULL(pa_bits)) {
2569	error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
2570	pa_bits, memtop - BIT_ULL(pa_bits));
2571	exit(EXIT_FAILURE);
2572	}
2573	if (base < device_memory_base) {
2574	error_report("maxmem/slots too huge");
2575	exit(EXIT_FAILURE);
2576	}
2577	if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
2578	base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
2579	}
2580
2581	/* We know for sure that at least the memory fits in the PA space */
2582	vms->highest_gpa = memtop - 1;
2583
2584	virt_set_high_memmap(vms, base, pa_bits);
2585
2586	if (device_memory_size > 0) {
2587	machine_memory_devices_init(ms, device_memory_base, device_memory_size);
2588	}
2589	vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1,
2590	256 * MiB),
2591	BIT_ULL(pa_bits)) - 1;
2592	}
2593
2594	static VirtGICType finalize_gic_version_do(const char *accel_name,
2595	VirtGICType gic_version,
2596	int gics_supported,
2597	unsigned int max_cpus)
2598	{
2599	/* Convert host/max/nosel to GIC version number */
2600	switch (gic_version) {
2601	case VIRT_GIC_VERSION_HOST:
2602	if (!kvm_enabled()) {
2603	error_report("gic-version=host requires KVM");
2604	exit(1);
2605	}
2606
2607	/* For KVM, gic-version=host means gic-version=max */
2608	return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
2609	gics_supported, max_cpus);
2610	case VIRT_GIC_VERSION_MAX:
2611	/*
2612	* We don't (currently) make 'max' select GICv5 as it is not
2613	* backwards compatible for system software with GICv3/v4 and
2614	* at time of writing not widely supported in guest kernels.
2615	*/
2616	if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
2617	gic_version = VIRT_GIC_VERSION_4;
2618	} else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
2619	gic_version = VIRT_GIC_VERSION_3;
2620	} else {
2621	gic_version = VIRT_GIC_VERSION_2;
2622	}
2623	break;
2624	case VIRT_GIC_VERSION_NOSEL:
2625	if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
2626	max_cpus <= GIC_NCPU) {
2627	gic_version = VIRT_GIC_VERSION_2;
2628	} else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
2629	/*
2630	* in case the host does not support v2 emulation or
2631	* the end-user requested more than 8 VCPUs we now default
2632	* to v3. In any case defaulting to v2 would be broken.
2633	*/
2634	gic_version = VIRT_GIC_VERSION_3;
2635	} else if (max_cpus > GIC_NCPU) {
2636	error_report("%s only supports GICv2 emulation but more than 8 "
2637	"vcpus are requested", accel_name);
2638	exit(1);
2639	}
2640	break;
2641	case VIRT_GIC_VERSION_2:
2642	case VIRT_GIC_VERSION_3:
2643	case VIRT_GIC_VERSION_4:
2644	case VIRT_GIC_VERSION_5:
2645	break;
2646	}
2647
2648	/* Check chosen version is effectively supported */
2649	switch (gic_version) {
2650	case VIRT_GIC_VERSION_2:
2651	if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
2652	error_report("%s does not support GICv2 emulation", accel_name);
2653	exit(1);
2654	}
2655	break;
2656	case VIRT_GIC_VERSION_3:
2657	if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
2658	error_report("%s does not support GICv3 emulation", accel_name);
2659	exit(1);
2660	}
2661	break;
2662	case VIRT_GIC_VERSION_4:
2663	if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
2664	error_report("%s does not support GICv4 emulation, is virtualization=on?",
2665	accel_name);
2666	exit(1);
2667	}
2668	break;
2669	case VIRT_GIC_VERSION_5:
2670	if (!(gics_supported & VIRT_GIC_VERSION_5_MASK)) {
2671	error_report("%s does not support GICv5 emulation", accel_name);
2672	exit(1);
2673	}
2674	break;
2675	default:
2676	error_report("logic error in finalize_gic_version");
2677	exit(1);
2678	break;
2679	}
2680
2681	return gic_version;
2682	}
2683
2684	/*
2685	* finalize_gic_version - Determines the final gic_version
2686	* according to the gic-version property
2687	*
2688	* Default GIC type is v2
2689	*/
2690	static void finalize_gic_version(VirtMachineState *vms)
2691	{
2692	const char *accel_name = current_accel_name();
2693	unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
2694	int gics_supported = 0;
2695
2696	/* Determine which GIC versions the current environment supports */
2697	if (kvm_enabled() && kvm_irqchip_in_kernel()) {
2698	int probe_bitmap = kvm_arm_vgic_probe();
2699
2700	if (!probe_bitmap) {
2701	error_report("Unable to determine GIC version supported by host");
2702	exit(1);
2703	}
2704
2705	if (probe_bitmap & KVM_ARM_VGIC_V2) {
2706	gics_supported \|= VIRT_GIC_VERSION_2_MASK;
2707	}
2708	if (probe_bitmap & KVM_ARM_VGIC_V3) {
2709	gics_supported \|= VIRT_GIC_VERSION_3_MASK;
2710	}
2711	} else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
2712	/* KVM w/o kernel irqchip can only deal with GICv2 */
2713	gics_supported \|= VIRT_GIC_VERSION_2_MASK;
2714	accel_name = "KVM with kernel-irqchip=off";
2715	} else if (whpx_enabled()) {
2716	gics_supported \|= VIRT_GIC_VERSION_3_MASK;
2717	} else if (hvf_enabled()) {
2718	if (!hvf_irqchip_in_kernel()) {
2719	gics_supported \|= VIRT_GIC_VERSION_2_MASK;
2720	}
2721	/* Hypervisor.framework doesn't expose EL2<->1 transition notifiers */
2722	if (!(!hvf_irqchip_in_kernel() && vms->virt)) {
2723	gics_supported \|= VIRT_GIC_VERSION_3_MASK;
2724	}
2725	} else if (tcg_enabled() \|\| qtest_enabled()) {
2726	gics_supported \|= VIRT_GIC_VERSION_2_MASK;
2727	if (module_object_class_by_name("arm-gicv3")) {
2728	gics_supported \|= VIRT_GIC_VERSION_3_MASK;
2729	if (vms->virt) {
2730	/* GICv4 only makes sense if CPU has EL2 */
2731	gics_supported \|= VIRT_GIC_VERSION_4_MASK;
2732	}
2733	}
2734	if (!hvf_enabled() && module_object_class_by_name("arm-gicv5")) {
2735	/* HVF doesn't have GICv5 support */
2736	gics_supported \|= VIRT_GIC_VERSION_5_MASK;
2737	}
2738	} else {
2739	error_report("Unsupported accelerator, can not determine GIC support");
2740	exit(1);
2741	}
2742
2743	/*
2744	* Then convert helpers like host/max to concrete GIC versions and ensure
2745	* the desired version is supported
2746	*/
2747	vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2748	gics_supported, max_cpus);
2749	}
2750
2751	static void finalize_msi_controller(VirtMachineState *vms)
2752	{
2753	/*
2754	* VIRT_MSI_LEGACY_OPT_ITS_OFF is an option to replicate
2755	* behavior of its=off when running with a GICv2, where a
2756	* GICv2m is still present. Otherwise, it behaves the same
2757	* as msi=off.
2758	*/
2759	if (vms->msi_controller == VIRT_MSI_LEGACY_OPT_ITS_OFF) {
2760	if (vms->gic_version == 2) {
2761	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
2762	} else {
2763	vms->msi_controller = VIRT_MSI_CTRL_NONE;
2764	}
2765	}
2766	if (vms->msi_controller == VIRT_MSI_CTRL_AUTO) {
2767	if (vms->gic_version == VIRT_GIC_VERSION_2) {
2768	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
2769	} else if (whpx_enabled()) {
2770	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
2771	} else if (hvf_enabled() && hvf_irqchip_in_kernel()) {
2772	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
2773	} else if (vms->gic_version == VIRT_GIC_VERSION_5) {
2774	/* GICv5 ITS is not yet implemented */
2775	vms->msi_controller = VIRT_MSI_CTRL_NONE;
2776	} else {
2777	vms->msi_controller = VIRT_MSI_CTRL_ITS;
2778	}
2779	}
2780
2781	if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
2782	if (vms->gic_version == VIRT_GIC_VERSION_2) {
2783	/*
2784	* The legacy its= option in earlier releases allowed specifying
2785	* this configuration and treated it as GICv3 + GICv2m.
2786	* Diagnose it as an error even for that case.
2787	*/
2788	error_report("GICv2 + ITS is an invalid configuration.");
2789	exit(1);
2790	}
2791	if (vms->gic_version == VIRT_GIC_VERSION_5) {
2792	error_report("GICv5 + ITS is not yet implemented.");
2793	exit(1);
2794	}
2795	if (whpx_enabled()) {
2796	error_report("ITS not supported on WHPX.");
2797	exit(1);
2798	}
2799	if (hvf_enabled() && hvf_irqchip_in_kernel()) {
2800	error_report("ITS not supported on HVF when using the hardware vGIC.");
2801	exit(1);
2802	}
2803	}
2804
2805	assert(vms->msi_controller != VIRT_MSI_CTRL_AUTO);
2806	}
2807
2808	/*
2809	* virt_post_cpus_gic_realized() must be called after the CPUs and
2810	* the GIC have both been realized.
2811	*/
2812	static void virt_post_cpus_gic_realized(VirtMachineState *vms,
2813	MemoryRegion *sysmem)
2814	{
2815	int max_cpus = MACHINE(vms)->smp.max_cpus;
2816	bool aarch64, pmu, steal_time;
2817	CPUState *cpu;
2818
2819	aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2820	pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2821	steal_time = object_property_get_bool(OBJECT(first_cpu),
2822	"kvm-steal-time", NULL);
2823
2824	if (kvm_enabled()) {
2825	hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2826	hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2827
2828	if (steal_time) {
2829	MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2830	hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2831
2832	/* The memory region size must be a multiple of host page size. */
2833	pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2834
2835	if (pvtime_size > pvtime_reg_size) {
2836	error_report("pvtime requires a %" HWADDR_PRId
2837	" byte memory region for %d CPUs,"
2838	" but only %" HWADDR_PRId " has been reserved",
2839	pvtime_size, max_cpus, pvtime_reg_size);
2840	exit(1);
2841	}
2842
2843	memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2844	memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2845	}
2846	if (!aarch64 && vms->virt) {
2847	error_report("KVM does not support EL2 on an AArch32 vCPU");
2848	exit(1);
2849	}
2850
2851	CPU_FOREACH(cpu) {
2852	if (pmu) {
2853	assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2854	if (kvm_irqchip_in_kernel()) {
2855	kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2856	}
2857	kvm_arm_pmu_init(ARM_CPU(cpu));
2858	}
2859	if (steal_time) {
2860	kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2861	+ cpu->cpu_index
2862	* PVTIME_SIZE_PER_CPU);
2863	}
2864	}
2865	} else {
2866	if (aarch64 && vms->highmem) {
2867	int requested_pa_size = 64 - clz64(vms->highest_gpa);
2868	int pamax = arm_pamax(ARM_CPU(first_cpu));
2869
2870	if (pamax < requested_pa_size) {
2871	error_report("VCPU supports less PA bits (%d) than "
2872	"requested by the memory map (%d)",
2873	pamax, requested_pa_size);
2874	exit(1);
2875	}
2876	}
2877	}
2878	}
2879
2880	static void machvirt_init(MachineState *machine)
2881	{
2882	VirtMachineState *vms = VIRT_MACHINE(machine);
2883	VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2884	MachineClass *mc = MACHINE_GET_CLASS(machine);
2885	const CPUArchIdList *possible_cpus;
2886	MemoryRegion *sysmem = get_system_memory();
2887	MemoryRegion *secure_sysmem = NULL;
2888	MemoryRegion *tag_sysmem = NULL;
2889	MemoryRegion *secure_tag_sysmem = NULL;
2890	int n, virt_max_cpus;
2891	bool firmware_loaded;
2892	bool aarch64 = true;
2893	unsigned int smp_cpus = machine->smp.cpus;
2894	unsigned int max_cpus = machine->smp.max_cpus;
2895
2896	possible_cpus = mc->possible_cpu_arch_ids(machine);
2897
2898	/*
2899	* In accelerated mode, the memory map is computed earlier in kvm_type()
2900	* for Linux, or hvf_get_physical_address_range() for macOS to create a
2901	* VM with the right number of IPA bits.
2902	*/
2903	if (!vms->memmap) {
2904	Object *cpuobj;
2905	ARMCPU *armcpu;
2906	int pa_bits;
2907
2908	/*
2909	* Instantiate a temporary CPU object to find out about what
2910	* we are about to deal with. Once this is done, get rid of
2911	* the object.
2912	*/
2913	cpuobj = object_new(possible_cpus->cpus[0].type);
2914	armcpu = ARM_CPU(cpuobj);
2915
2916	pa_bits = arm_pamax(armcpu);
2917
2918	object_unref(cpuobj);
2919
2920	virt_set_memmap(vms, pa_bits);
2921	}
2922
2923	/* We can probe only here because during property set
2924	* KVM is not available yet
2925	*/
2926	finalize_gic_version(vms);
2927	finalize_msi_controller(vms);
2928
2929	if (vms->secure) {
2930	/*
2931	* The Secure view of the world is the same as the NonSecure,
2932	* but with a few extra devices. Create it as a container region
2933	* containing the system memory at low priority; any secure-only
2934	* devices go in at higher priority and take precedence.
2935	*/
2936	secure_sysmem = g_new(MemoryRegion, 1);
2937	vms->secure_sysmem = secure_sysmem;
2938	memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2939	UINT64_MAX);
2940	memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2941	}
2942
2943	firmware_loaded = virt_firmware_init(vms, sysmem,
2944	secure_sysmem ?: sysmem);
2945
2946	/* If we have an EL3 boot ROM then the assumption is that it will
2947	* implement PSCI itself, so disable QEMU's internal implementation
2948	* so it doesn't get in the way. Instead of starting secondary
2949	* CPUs in PSCI powerdown state we will start them all running and
2950	* let the boot ROM sort them out.
2951	* The usual case is that we do use QEMU's PSCI implementation;
2952	* if the guest has EL2 then we will use SMC as the conduit,
2953	* and otherwise we will use HVC (for backwards compatibility and
2954	* because if we're using KVM then we must use HVC).
2955	*/
2956	if (vms->secure && firmware_loaded) {
2957	vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2958	} else if (vms->virt) {
2959	vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2960	} else {
2961	vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2962	}
2963
2964	/*
2965	* The maximum number of CPUs depends on the GIC version, or on how
2966	* many redistributors we can fit into the memory map (which in turn
2967	* depends on whether this is a GICv3 or v4).
2968	*/
2969	if (vms->gic_version == VIRT_GIC_VERSION_2) {
2970	virt_max_cpus = GIC_NCPU;
2971	} else if (vms->gic_version == VIRT_GIC_VERSION_5) {
2972	/*
2973	* GICv5 imposes no CPU limit beyond the 16-bit IAFFID field.
2974	* The maximum number of CPUs will be limited not by this, but
2975	* by the MachineClass::max_cpus value we set earlier.
2976	*/
2977	virt_max_cpus = 1 << QEMU_GICV5_IAFFID_BITS;
2978	} else {
2979	virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2980	if (vms->highmem_redists) {
2981	virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2982	}
2983	}
2984
2985	if (max_cpus > virt_max_cpus) {
2986	error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2987	"supported by machine 'mach-virt' (%d)",
2988	max_cpus, virt_max_cpus);
2989	if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2990	error_printf("Try 'highmem-redists=on' for more CPUs\n");
2991	}
2992
2993	exit(1);
2994	}
2995
2996	if (vms->secure && !tcg_enabled() && !qtest_enabled()) {
2997	error_report("mach-virt: %s does not support providing "
2998	"Security extensions (TrustZone) to the guest CPU",
2999	current_accel_name());
3000	exit(1);
3001	}
3002
3003	if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) {
3004	error_report("mach-virt: host kernel KVM does not support providing "
3005	"Virtualization extensions to the guest CPU");
3006	exit(1);
3007	}
3008
3009	if (vms->virt && !kvm_enabled() && !tcg_enabled()
3010	&& !hvf_enabled() && !qtest_enabled()) {
3011	error_report("mach-virt: %s does not support providing "
3012	"Virtualization extensions to the guest CPU",
3013	current_accel_name());
3014	exit(1);
3015	}
3016
3017	if (vms->mte && hvf_enabled()) {
3018	error_report("mach-virt: %s does not support providing "
3019	"MTE to the guest CPU",
3020	current_accel_name());
3021	exit(1);
3022	}
3023
3024	if ((vms->virt \|\| vms->secure) &&
3025	vms->gic_version == VIRT_GIC_VERSION_5) {
3026	error_report("mach-virt: GICv5 currently supports EL1 only");
3027	exit(1);
3028	}
3029
3030	create_fdt(vms);
3031
3032	assert(possible_cpus->len == max_cpus);
3033	for (n = 0; n < possible_cpus->len; n++) {
3034	Object *cpuobj;
3035	CPUState *cs;
3036
3037	if (n >= smp_cpus) {
3038	break;
3039	}
3040
3041	cpuobj = object_new(possible_cpus->cpus[n].type);
3042	object_property_set_int(cpuobj, "mp-affinity",
3043	possible_cpus->cpus[n].arch_id, NULL);
3044
3045	cs = CPU(cpuobj);
3046	cs->cpu_index = n;
3047
3048	numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
3049	&error_fatal);
3050
3051	aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
3052
3053	if (!vms->secure) {
3054	object_property_set_bool(cpuobj, "has_el3", false, NULL);
3055	}
3056
3057	if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
3058	object_property_set_bool(cpuobj, "has_el2", false, NULL);
3059	}
3060
3061	if (vmc->no_kvm_steal_time &&
3062	object_property_find(cpuobj, "kvm-steal-time")) {
3063	object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
3064	}
3065
3066	if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
3067	object_property_set_bool(cpuobj, "lpa2", false, NULL);
3068	}
3069
3070	if (vms->gic_version == VIRT_GIC_VERSION_5) {
3071	if (!object_property_find(cpuobj, "has_gcie")) {
3072	error_report("Using GICv5 but guest CPU does not support it");
3073	exit(1);
3074	}
3075	object_property_set_bool(cpuobj, "has_gcie", true, NULL);
3076	}
3077
3078	if (object_property_find(cpuobj, "reset-cbar")) {
3079	object_property_set_int(cpuobj, "reset-cbar",
3080	vms->memmap[VIRT_CPUPERIPHS].base,
3081	&error_abort);
3082	}
3083
3084	object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
3085	&error_abort);
3086	if (vms->secure) {
3087	object_property_set_link(cpuobj, "secure-memory",
3088	OBJECT(secure_sysmem), &error_abort);
3089	}
3090
3091	if (vms->mte) {
3092	if (tcg_enabled()) {
3093	/* Create the memory region only once, but link to all cpus. */
3094	if (!tag_sysmem) {
3095	/*
3096	* The property exists only if MemTag is supported.
3097	* If it is, we must allocate the ram to back that up.
3098	*/
3099	if (!object_property_find(cpuobj, "tag-memory")) {
3100	error_report("MTE requested, but not supported "
3101	"by the guest CPU");
3102	exit(1);
3103	}
3104
3105	tag_sysmem = g_new(MemoryRegion, 1);
3106	memory_region_init(tag_sysmem, OBJECT(machine),
3107	"tag-memory", UINT64_MAX / 32);
3108
3109	if (vms->secure) {
3110	secure_tag_sysmem = g_new(MemoryRegion, 1);
3111	memory_region_init(secure_tag_sysmem, OBJECT(machine),
3112	"secure-tag-memory",
3113	UINT64_MAX / 32);
3114
3115	/* As with ram, secure-tag takes precedence over tag. */
3116	memory_region_add_subregion_overlap(secure_tag_sysmem,
3117	0, tag_sysmem, -1);
3118	}
3119	}
3120
3121	object_property_set_link(cpuobj, "tag-memory",
3122	OBJECT(tag_sysmem), &error_abort);
3123	if (vms->secure) {
3124	object_property_set_link(cpuobj, "secure-tag-memory",
3125	OBJECT(secure_tag_sysmem),
3126	&error_abort);
3127	}
3128	} else if (kvm_enabled()) {
3129	if (!kvm_arm_mte_supported()) {
3130	error_report("MTE requested, but not supported by KVM");
3131	exit(1);
3132	}
3133	kvm_arm_enable_mte(cpuobj, &error_abort);
3134	} else {
3135	error_report("MTE requested, but not supported ");
3136	exit(1);
3137	}
3138	}
3139
3140	qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
3141	object_unref(cpuobj);
3142	}
3143
3144	/* Now we've created the CPUs we can see if they have the hypvirt timer */
3145	vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
3146	!vmc->no_ns_el2_virt_timer_irq;
3147
3148	fdt_add_timer_nodes(vms);
3149	fdt_add_cpu_nodes(vms);
3150
3151	memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
3152	machine->ram);
3153
3154	cxl_fmws_update_mmio();
3155
3156	virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
3157
3158	create_gic(vms, sysmem);
3159	create_msi_controller(vms);
3160
3161	virt_post_cpus_gic_realized(vms, sysmem);
3162
3163	fdt_add_pmu_nodes(vms);
3164
3165	/*
3166	* The first UART always exists. If the security extensions are
3167	* enabled, the second UART also always exists. Otherwise, it only exists
3168	* if a backend is configured explicitly via '-serial <backend>'.
3169	* This avoids potentially breaking existing user setups that expect
3170	* only one NonSecure UART to be present (for instance, older EDK2
3171	* binaries).
3172	*
3173	* The nodes end up in the DTB in reverse order of creation, so we must
3174	* create UART0 last to ensure it appears as the first node in the DTB,
3175	* for compatibility with guest software that just iterates through the
3176	* DTB to find the first UART, as older versions of EDK2 do.
3177	* DTB readers that follow the spec, as Linux does, should honour the
3178	* aliases node information and /chosen/stdout-path regardless of
3179	* the order that nodes appear in the DTB.
3180	*
3181	* For similar back-compatibility reasons, if UART1 is the secure UART
3182	* we create it second (and so it appears first in the DTB), because
3183	* that's what QEMU has always done.
3184	*/
3185	if (!vms->secure) {
3186	Chardev *serial1 = serial_hd(1);
3187
3188	if (serial1) {
3189	vms->second_ns_uart_present = true;
3190	create_uart(vms, VIRT_UART1, sysmem, serial1, false);
3191	}
3192	}
3193	create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
3194	if (vms->secure) {
3195	create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
3196	}
3197
3198	if (vms->secure) {
3199	create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
3200	}
3201
3202	if (tag_sysmem) {
3203	create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
3204	machine->ram_size, "mach-virt.tag");
3205	}
3206
3207	vms->highmem_ecam &= (!firmware_loaded \|\| aarch64);
3208
3209	create_rtc(vms);
3210
3211	create_pcie(vms);
3212	create_cxl_host_reg_region(vms);
3213
3214	if (aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
3215	vms->acpi_dev = create_acpi_ged(vms);
3216	vms->generic_error_notifier.notify = virt_generic_error_req;
3217	notifier_list_add(&acpi_generic_error_notifiers,
3218	&vms->generic_error_notifier);
3219	} else {
3220	create_gpio_devices(vms, VIRT_GPIO, sysmem);
3221	}
3222
3223	if (vms->secure && !vmc->no_secure_gpio) {
3224	create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
3225	}
3226
3227	/* connect powerdown request */
3228	vms->powerdown_notifier.notify = virt_powerdown_req;
3229	qemu_register_powerdown_notifier(&vms->powerdown_notifier);
3230
3231	/* Create mmio transports, so the user can create virtio backends
3232	* (which will be automatically plugged in to the transports). If
3233	* no backend is created the transport will just sit harmlessly idle.
3234	*/
3235	create_virtio_devices(vms);
3236
3237	vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
3238	rom_set_fw(vms->fw_cfg);
3239
3240	create_platform_bus(vms);
3241
3242	if (machine->nvdimms_state->is_enabled) {
3243	const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
3244	.space_id = AML_AS_SYSTEM_MEMORY,
3245	.address = vms->memmap[VIRT_NVDIMM_ACPI].base,
3246	.bit_width = NVDIMM_ACPI_IO_LEN << 3
3247	};
3248
3249	nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
3250	arm_virt_nvdimm_acpi_dsmio,
3251	vms->fw_cfg, OBJECT(vms));
3252	}
3253
3254	vms->bootinfo.ram_size = machine->ram_size;
3255	vms->bootinfo.board_id = -1;
3256	vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
3257	vms->bootinfo.get_dtb = machvirt_dtb;
3258	vms->bootinfo.skip_dtb_autoload = true;
3259	vms->bootinfo.firmware_loaded = firmware_loaded;
3260	vms->bootinfo.psci_conduit = vms->psci_conduit;
3261	arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
3262
3263	vms->machine_done.notify = virt_machine_done;
3264	qemu_add_machine_init_done_notifier(&vms->machine_done);
3265	}
3266
3267	static bool virt_get_secure(Object obj, Error *errp)
3268	{
3269	VirtMachineState *vms = VIRT_MACHINE(obj);
3270
3271	return vms->secure;
3272	}
3273
3274	static void virt_set_secure(Object obj, bool value, Error *errp)
3275	{
3276	VirtMachineState *vms = VIRT_MACHINE(obj);
3277
3278	vms->secure = value;
3279	}
3280
3281	static bool virt_get_virt(Object obj, Error *errp)
3282	{
3283	VirtMachineState *vms = VIRT_MACHINE(obj);
3284
3285	return vms->virt;
3286	}
3287
3288	static void virt_set_virt(Object obj, bool value, Error *errp)
3289	{
3290	VirtMachineState *vms = VIRT_MACHINE(obj);
3291
3292	vms->virt = value;
3293	/*
3294	* At this point, HVF is not initialised yet.
3295	* However, it needs to know if nested virt is enabled at init time.
3296	*/
3297	hvf_nested_virt_enable(value);
3298	}
3299
3300	static bool virt_get_highmem(Object obj, Error *errp)
3301	{
3302	VirtMachineState *vms = VIRT_MACHINE(obj);
3303
3304	return vms->highmem;
3305	}
3306
3307	static void virt_set_highmem(Object obj, bool value, Error *errp)
3308	{
3309	VirtMachineState *vms = VIRT_MACHINE(obj);
3310
3311	vms->highmem = value;
3312	}
3313
3314	static bool virt_get_compact_highmem(Object obj, Error *errp)
3315	{
3316	VirtMachineState *vms = VIRT_MACHINE(obj);
3317
3318	return vms->highmem_compact;
3319	}
3320
3321	static void virt_set_compact_highmem(Object obj, bool value, Error *errp)
3322	{
3323	VirtMachineState *vms = VIRT_MACHINE(obj);
3324
3325	vms->highmem_compact = value;
3326	}
3327
3328	static bool virt_get_highmem_redists(Object obj, Error *errp)
3329	{
3330	VirtMachineState *vms = VIRT_MACHINE(obj);
3331
3332	return vms->highmem_redists;
3333	}
3334
3335	static void virt_set_highmem_redists(Object obj, bool value, Error *errp)
3336	{
3337	VirtMachineState *vms = VIRT_MACHINE(obj);
3338
3339	vms->highmem_redists = value;
3340	}
3341
3342	static bool virt_get_highmem_ecam(Object obj, Error *errp)
3343	{
3344	VirtMachineState *vms = VIRT_MACHINE(obj);
3345
3346	return vms->highmem_ecam;
3347	}
3348
3349	static void virt_set_highmem_ecam(Object obj, bool value, Error *errp)
3350	{
3351	VirtMachineState *vms = VIRT_MACHINE(obj);
3352
3353	vms->highmem_ecam = value;
3354	}
3355
3356	static bool virt_get_highmem_mmio(Object obj, Error *errp)
3357	{
3358	VirtMachineState *vms = VIRT_MACHINE(obj);
3359
3360	return vms->highmem_mmio;
3361	}
3362
3363	static void virt_set_highmem_mmio(Object obj, bool value, Error *errp)
3364	{
3365	VirtMachineState *vms = VIRT_MACHINE(obj);
3366
3367	vms->highmem_mmio = value;
3368	}
3369
3370	static void virt_get_highmem_mmio_size(Object obj, Visitor v,
3371	const char name, void opaque,
3372	Error **errp)
3373	{
3374	uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size;
3375
3376	visit_type_size(v, name, &size, errp);
3377	}
3378
3379	static void virt_set_highmem_mmio_size(Object obj, Visitor v,
3380	const char name, void opaque,
3381	Error **errp)
3382	{
3383	uint64_t size;
3384
3385	if (!visit_type_size(v, name, &size, errp)) {
3386	return;
3387	}
3388
3389	if (!is_power_of_2(size)) {
3390	error_setg(errp, "highmem-mmio-size is not a power of 2");
3391	return;
3392	}
3393
3394	if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) {
3395	char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE);
3396	error_setg(errp, "highmem-mmio-size cannot be set to a lower value "
3397	"than the default (%s)", sz);
3398	g_free(sz);
3399	return;
3400	}
3401
3402	extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size;
3403	}
3404
3405	static char virt_get_msi(Object obj, Error **errp)
3406	{
3407	VirtMachineState *vms = VIRT_MACHINE(obj);
3408	const char *val;
3409
3410	switch (vms->msi_controller) {
3411	case VIRT_MSI_CTRL_NONE:
3412	case VIRT_MSI_LEGACY_OPT_ITS_OFF:
3413	val = "off";
3414	break;
3415	case VIRT_MSI_CTRL_ITS:
3416	val = "its";
3417	break;
3418	case VIRT_MSI_CTRL_GICV2M:
3419	val = "gicv2m";
3420	break;
3421	case VIRT_MSI_CTRL_AUTO:
3422	val = "auto";
3423	break;
3424	default:
3425	g_assert_not_reached();
3426	}
3427	return g_strdup(val);
3428	}
3429
3430	static void virt_set_msi(Object obj, const char value, Error **errp)
3431	{
3432	ERRP_GUARD();
3433	VirtMachineState *vms = VIRT_MACHINE(obj);
3434
3435	if (!strcmp(value, "auto")) {
3436	vms->msi_controller = VIRT_MSI_CTRL_AUTO; /* Will be overridden later */
3437	} else if (!strcmp(value, "its")) {
3438	vms->msi_controller = VIRT_MSI_CTRL_ITS;
3439	} else if (!strcmp(value, "gicv2m")) {
3440	vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
3441	} else if (!strcmp(value, "off")) {
3442	vms->msi_controller = VIRT_MSI_CTRL_NONE;
3443	} else {
3444	error_setg(errp, "Invalid msi value");
3445	error_append_hint(errp, "Valid values are auto, gicv2m, its, off\n");
3446	}
3447	}
3448
3449	static bool virt_get_its(Object obj, Error *errp)
3450	{
3451	VirtMachineState *vms = VIRT_MACHINE(obj);
3452
3453	switch (vms->msi_controller) {
3454	case VIRT_MSI_CTRL_AUTO:
3455	case VIRT_MSI_CTRL_ITS:
3456	return true;
3457	case VIRT_MSI_CTRL_NONE:
3458	case VIRT_MSI_CTRL_GICV2M:
3459	case VIRT_MSI_LEGACY_OPT_ITS_OFF:
3460	return false;
3461	default:
3462	g_assert_not_reached();
3463	}
3464	}
3465
3466	static void virt_set_its(Object obj, bool value, Error *errp)
3467	{
3468	VirtMachineState *vms = VIRT_MACHINE(obj);
3469
3470	if (value) {
3471	vms->msi_controller = VIRT_MSI_CTRL_ITS;
3472	} else {
3473	vms->msi_controller = VIRT_MSI_LEGACY_OPT_ITS_OFF;
3474	}
3475	}
3476
3477	static void virt_get_virtio_transports(Object obj, Visitor v,
3478	const char name, void opaque,
3479	Error **errp)
3480	{
3481	VirtMachineState *vms = VIRT_MACHINE(obj);
3482	uint8_t transports = vms->virtio_transports;
3483
3484	visit_type_uint8(v, name, &transports, errp);
3485	}
3486
3487	static void virt_set_virtio_transports(Object obj, Visitor v,
3488	const char name, void opaque,
3489	Error **errp)
3490	{
3491	VirtMachineState *vms = VIRT_MACHINE(obj);
3492	uint8_t transports;
3493
3494	if (!visit_type_uint8(v, name, &transports, errp)) {
3495	return;
3496	}
3497
3498	if (transports > NUM_VIRTIO_TRANSPORTS) {
3499	error_setg(errp, "virtio-mmio-transports must not exceed %d",
3500	NUM_VIRTIO_TRANSPORTS);
3501	return;
3502	}
3503
3504	vms->virtio_transports = transports;
3505	}
3506
3507	static bool virt_get_dtb_randomness(Object obj, Error *errp)
3508	{
3509	VirtMachineState *vms = VIRT_MACHINE(obj);
3510
3511	return vms->dtb_randomness;
3512	}
3513
3514	static void virt_set_dtb_randomness(Object obj, bool value, Error *errp)
3515	{
3516	VirtMachineState *vms = VIRT_MACHINE(obj);
3517
3518	vms->dtb_randomness = value;
3519	}
3520
3521	static char virt_get_oem_id(Object obj, Error **errp)
3522	{
3523	VirtMachineState *vms = VIRT_MACHINE(obj);
3524
3525	return g_strdup(vms->oem_id);
3526	}
3527
3528	static void virt_set_oem_id(Object obj, const char value, Error **errp)
3529	{
3530	VirtMachineState *vms = VIRT_MACHINE(obj);
3531	size_t len = strlen(value);
3532
3533	if (len > 6) {
3534	error_setg(errp,
3535	"User specified oem-id value is bigger than 6 bytes in size");
3536	return;
3537	}
3538
3539	strncpy(vms->oem_id, value, 6);
3540	}
3541
3542	static char virt_get_oem_table_id(Object obj, Error **errp)
3543	{
3544	VirtMachineState *vms = VIRT_MACHINE(obj);
3545
3546	return g_strdup(vms->oem_table_id);
3547	}
3548
3549	static void virt_set_oem_table_id(Object obj, const char value,
3550	Error **errp)
3551	{
3552	VirtMachineState *vms = VIRT_MACHINE(obj);
3553	size_t len = strlen(value);
3554
3555	if (len > 8) {
3556	error_setg(errp,
3557	"User specified oem-table-id value is bigger than 8 bytes in size");
3558	return;
3559	}
3560	strncpy(vms->oem_table_id, value, 8);
3561	}
3562
3563
3564	bool virt_is_acpi_enabled(const VirtMachineState *vms)
3565	{
3566	if (vms->acpi == ON_OFF_AUTO_OFF) {
3567	return false;
3568	}
3569	return true;
3570	}
3571
3572	static void virt_get_acpi(Object obj, Visitor v, const char *name,
3573	void opaque, Error *errp)
3574	{
3575	VirtMachineState *vms = VIRT_MACHINE(obj);
3576	OnOffAuto acpi = vms->acpi;
3577
3578	visit_type_OnOffAuto(v, name, &acpi, errp);
3579	}
3580
3581	static void virt_set_acpi(Object obj, Visitor v, const char *name,
3582	void opaque, Error *errp)
3583	{
3584	VirtMachineState *vms = VIRT_MACHINE(obj);
3585
3586	visit_type_OnOffAuto(v, name, &vms->acpi, errp);
3587	}
3588
3589	static bool virt_get_ras(Object obj, Error *errp)
3590	{
3591	VirtMachineState *vms = VIRT_MACHINE(obj);
3592
3593	return vms->ras;
3594	}
3595
3596	static void virt_set_ras(Object obj, bool value, Error *errp)
3597	{
3598	VirtMachineState *vms = VIRT_MACHINE(obj);
3599
3600	vms->ras = value;
3601	}
3602
3603	static bool virt_get_mte(Object obj, Error *errp)
3604	{
3605	VirtMachineState *vms = VIRT_MACHINE(obj);
3606
3607	return vms->mte;
3608	}
3609
3610	static void virt_set_mte(Object obj, bool value, Error *errp)
3611	{
3612	VirtMachineState *vms = VIRT_MACHINE(obj);
3613
3614	vms->mte = value;
3615	}
3616
3617	static char virt_get_gic_version(Object obj, Error **errp)
3618	{
3619	VirtMachineState *vms = VIRT_MACHINE(obj);
3620	const char *val;
3621
3622	switch (vms->gic_version) {
3623	case VIRT_GIC_VERSION_5:
3624	val = "x-5";
3625	break;
3626	case VIRT_GIC_VERSION_4:
3627	val = "4";
3628	break;
3629	case VIRT_GIC_VERSION_3:
3630	val = "3";
3631	break;
3632	default:
3633	val = "2";
3634	break;
3635	}
3636	return g_strdup(val);
3637	}
3638
3639	static void virt_set_gic_version(Object obj, const char value, Error **errp)
3640	{
3641	VirtMachineState *vms = VIRT_MACHINE(obj);
3642
3643	if (!strcmp(value, "x-5")) {
3644	vms->gic_version = VIRT_GIC_VERSION_5;
3645	} else if (!strcmp(value, "4")) {
3646	vms->gic_version = VIRT_GIC_VERSION_4;
3647	} else if (!strcmp(value, "3")) {
3648	vms->gic_version = VIRT_GIC_VERSION_3;
3649	} else if (!strcmp(value, "2")) {
3650	vms->gic_version = VIRT_GIC_VERSION_2;
3651	} else if (!strcmp(value, "host")) {
3652	vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
3653	} else if (!strcmp(value, "max")) {
3654	vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
3655	} else {
3656	error_setg(errp, "Invalid gic-version value");
3657	error_append_hint(errp, "Valid values are 2, 3, 4, x-5, host, and max.\n");
3658	}
3659	}
3660
3661	static char virt_get_iommu(Object obj, Error **errp)
3662	{
3663	VirtMachineState *vms = VIRT_MACHINE(obj);
3664
3665	switch (vms->iommu) {
3666	case VIRT_IOMMU_NONE:
3667	return g_strdup("none");
3668	case VIRT_IOMMU_SMMUV3:
3669	return g_strdup("smmuv3");
3670	default:
3671	g_assert_not_reached();
3672	}
3673	}
3674
3675	static void virt_set_iommu(Object obj, const char value, Error **errp)
3676	{
3677	VirtMachineState *vms = VIRT_MACHINE(obj);
3678
3679	if (!strcmp(value, "smmuv3")) {
3680	vms->iommu = VIRT_IOMMU_SMMUV3;
3681	} else if (!strcmp(value, "none")) {
3682	vms->iommu = VIRT_IOMMU_NONE;
3683	} else {
3684	error_setg(errp, "Invalid iommu value");
3685	error_append_hint(errp, "Valid values are none, smmuv3.\n");
3686	}
3687	}
3688
3689	static bool virt_get_default_bus_bypass_iommu(Object obj, Error *errp)
3690	{
3691	VirtMachineState *vms = VIRT_MACHINE(obj);
3692
3693	return vms->default_bus_bypass_iommu;
3694	}
3695
3696	static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
3697	Error **errp)
3698	{
3699	VirtMachineState *vms = VIRT_MACHINE(obj);
3700
3701	vms->default_bus_bypass_iommu = value;
3702	}
3703
3704	static CpuInstanceProperties
3705	virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
3706	{
3707	MachineClass *mc = MACHINE_GET_CLASS(ms);
3708	const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
3709
3710	assert(cpu_index < possible_cpus->len);
3711	return possible_cpus->cpus[cpu_index].props;
3712	}
3713
3714	static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
3715	{
3716	int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
3717
3718	return socket_id % ms->numa_state->num_nodes;
3719	}
3720
3721	static const CPUArchIdList virt_possible_cpu_arch_ids(MachineState ms)
3722	{
3723	int n;
3724	unsigned int max_cpus = ms->smp.max_cpus;
3725	VirtMachineState *vms = VIRT_MACHINE(ms);
3726	MachineClass *mc = MACHINE_GET_CLASS(vms);
3727
3728	if (ms->possible_cpus) {
3729	assert(ms->possible_cpus->len == max_cpus);
3730	return ms->possible_cpus;
3731	}
3732
3733	ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3734	sizeof(CPUArchId) * max_cpus);
3735	ms->possible_cpus->len = max_cpus;
3736	for (n = 0; n < ms->possible_cpus->len; n++) {
3737	ms->possible_cpus->cpus[n].type = ms->cpu_type;
3738	ms->possible_cpus->cpus[n].arch_id =
3739	virt_cpu_mp_affinity(vms, n);
3740
3741	assert(!mc->smp_props.dies_supported);
3742	ms->possible_cpus->cpus[n].props.has_socket_id = true;
3743	ms->possible_cpus->cpus[n].props.socket_id =
3744	n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
3745	ms->possible_cpus->cpus[n].props.has_cluster_id = true;
3746	ms->possible_cpus->cpus[n].props.cluster_id =
3747	(n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
3748	ms->possible_cpus->cpus[n].props.has_core_id = true;
3749	ms->possible_cpus->cpus[n].props.core_id =
3750	(n / ms->smp.threads) % ms->smp.cores;
3751	ms->possible_cpus->cpus[n].props.has_thread_id = true;
3752	ms->possible_cpus->cpus[n].props.thread_id =
3753	n % ms->smp.threads;
3754	}
3755	return ms->possible_cpus;
3756	}
3757
3758	static void virt_memory_pre_plug(HotplugHandler hotplug_dev, DeviceState dev,
3759	Error **errp)
3760	{
3761	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3762	const MachineState *ms = MACHINE(hotplug_dev);
3763	const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3764
3765	if (!vms->acpi_dev && !(is_nvdimm && !dev->hotplugged)) {
3766	error_setg(errp,
3767	"memory hotplug is not enabled: missing acpi-ged device");
3768	return;
3769	}
3770
3771	if (vms->mte) {
3772	error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
3773	return;
3774	}
3775
3776	if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
3777	error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
3778	return;
3779	}
3780
3781	pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
3782	}
3783
3784	static void virt_memory_plug(HotplugHandler *hotplug_dev,
3785	DeviceState dev, Error *errp)
3786	{
3787	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3788	MachineState *ms = MACHINE(hotplug_dev);
3789	bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3790
3791	pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
3792
3793	if (is_nvdimm) {
3794	nvdimm_plug(ms->nvdimms_state);
3795	}
3796
3797	if (vms->acpi_dev) {
3798	hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
3799	dev, &error_abort);
3800	}
3801	}
3802
3803	static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
3804	DeviceState dev, Error *errp)
3805	{
3806	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3807
3808	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3809	virt_memory_pre_plug(hotplug_dev, dev, errp);
3810	} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3811	virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3812	} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3813	hwaddr db_start = 0, db_end = 0;
3814	QList *reserved_regions;
3815	char *resv_prop_str;
3816
3817	if (vms->iommu != VIRT_IOMMU_NONE) {
3818	error_setg(errp, "virt machine does not support multiple IOMMUs");
3819	return;
3820	}
3821
3822	switch (vms->msi_controller) {
3823	case VIRT_MSI_CTRL_NONE:
3824	return;
3825	case VIRT_MSI_CTRL_ITS:
3826	/* GITS_TRANSLATER page */
3827	db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
3828	db_end = base_memmap[VIRT_GIC_ITS].base +
3829	base_memmap[VIRT_GIC_ITS].size - 1;
3830	break;
3831	case VIRT_MSI_CTRL_GICV2M:
3832	/* MSI_SETSPI_NS page */
3833	db_start = base_memmap[VIRT_GIC_V2M].base;
3834	db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
3835	break;
3836	case VIRT_MSI_CTRL_AUTO:
3837	case VIRT_MSI_LEGACY_OPT_ITS_OFF:
3838	g_assert_not_reached();
3839	}
3840	resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
3841	db_start, db_end,
3842	VIRTIO_IOMMU_RESV_MEM_T_MSI);
3843
3844	reserved_regions = qlist_new();
3845	qlist_append_str(reserved_regions, resv_prop_str);
3846	qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
3847	g_free(resv_prop_str);
3848	} else if (object_dynamic_cast(OBJECT(dev), TYPE_WDT_SBSA)) {
3849	if (!object_property_get_bool(OBJECT(dev), "wdat", &error_abort)) {
3850	uint64_t cntfrq = object_property_get_int(OBJECT(qemu_get_cpu(0)),
3851	"cntfrq", &error_abort);
3852
3853	qdev_prop_set_uint64(dev, "clock-frequency", cntfrq);
3854	}
3855	} else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) {
3856	if (vms->legacy_smmuv3_present \|\| vms->iommu == VIRT_IOMMU_VIRTIO) {
3857	error_setg(errp, "virt machine already has %s set. "
3858	"Doesn't support incompatible iommus",
3859	(vms->legacy_smmuv3_present) ?
3860	"iommu=smmuv3" : "virtio-iommu");
3861	} else if (vms->iommu == VIRT_IOMMU_NONE) {
3862	/* The new SMMUv3 device is specific to the PCI bus */
3863	object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NULL);
3864	object_property_set_link(OBJECT(dev), "memory",
3865	OBJECT(vms->sysmem), NULL);
3866	object_property_set_link(OBJECT(dev), "secure-memory",
3867	OBJECT(vms->secure_sysmem), NULL);
3868	/*
3869	* In build_iort(), the ITS node(id=0) precedes SMMUv3 nodes
3870	* when present. Account for it so this SMMUv3's identifier
3871	* is globally unique across all IORT nodes.
3872	*/
3873	uint8_t its_offset = (vms->msi_controller == VIRT_MSI_CTRL_ITS)
3874	? 1 : 0;
3875	object_property_set_uint(OBJECT(dev), "identifier",
3876	its_offset + smmuv3_dev_id++, NULL);
3877	}
3878	if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) {
3879	hwaddr db_start = 0;
3880
3881	if (!kvm_enabled() \|\| !kvm_irqchip_in_kernel()) {
3882	error_setg(errp, "SMMUv3 accel=on requires KVM with "
3883	"kernel-irqchip=on support");
3884	return;
3885	}
3886
3887	if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {
3888	/* GITS_TRANSLATER page + offset */
3889	db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000 + 0x40;
3890	} else if (vms->msi_controller == VIRT_MSI_CTRL_GICV2M) {
3891	/* MSI_SETSPI_NS page + offset */
3892	db_start = base_memmap[VIRT_GIC_V2M].base + 0x40;
3893	}
3894	object_property_set_uint(OBJECT(dev), "msi-gpa", db_start,
3895	&error_abort);
3896	vms->pci_preserve_config = true;
3897	}
3898	}
3899	}
3900
3901	static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
3902	DeviceState dev, Error *errp)
3903	{
3904	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3905
3906	if (object_dynamic_cast(OBJECT(dev), TYPE_WDT_SBSA)) {
3907	SysBusDevice *s = SYS_BUS_DEVICE(dev);
3908	hwaddr rbase = vms->memmap[VIRT_GWDT_REFRESH].base;
3909	hwaddr cbase = vms->memmap[VIRT_GWDT_CONTROL].base;
3910	int irq = vms->irqmap[VIRT_GWDT_WS0];
3911
3912	sysbus_mmio_map(s, 0, rbase);
3913	sysbus_mmio_map(s, 1, cbase);
3914	sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
3915
3916	if (!object_property_get_bool(OBJECT(dev), "wdat", &error_abort)) {
3917	create_gwdt_dt_bindings(vms);
3918	}
3919	}
3920
3921	if (vms->platform_bus_dev) {
3922	MachineClass *mc = MACHINE_GET_CLASS(vms);
3923
3924	if (device_is_dynamic_sysbus(mc, dev)) {
3925	platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
3926	SYS_BUS_DEVICE(dev));
3927	}
3928	}
3929
3930	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3931	virt_memory_plug(hotplug_dev, dev, errp);
3932	} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3933	virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3934	}
3935
3936	if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) {
3937	if (!vms->legacy_smmuv3_present && vms->platform_bus_dev) {
3938	PCIBus *bus;
3939
3940	bus = PCI_BUS(object_property_get_link(OBJECT(dev), "primary-bus",
3941	&error_abort));
3942	if (pci_bus_bypass_iommu(bus)) {
3943	error_setg(errp, "Bypass option cannot be set for SMMUv3 "
3944	"associated PCIe RC");
3945	return;
3946	}
3947
3948	create_smmuv3_dev_dtb(vms, dev, bus, errp);
3949	g_ptr_array_add(vms->smmuv3_devices, dev);
3950	}
3951	}
3952
3953	if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3954	PCIDevice *pdev = PCI_DEVICE(dev);
3955
3956	vms->iommu = VIRT_IOMMU_VIRTIO;
3957	vms->virtio_iommu_bdf = pci_get_bdf(pdev);
3958	create_virtio_iommu_dt_bindings(vms);
3959	}
3960	}
3961
3962	static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
3963	DeviceState dev, Error *errp)
3964	{
3965	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3966
3967	if (!vms->acpi_dev) {
3968	error_setg(errp,
3969	"memory hotplug is not enabled: missing acpi-ged device");
3970	return;
3971	}
3972
3973	if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
3974	error_setg(errp, "nvdimm device hot unplug is not supported yet.");
3975	return;
3976	}
3977
3978	hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
3979	errp);
3980	}
3981
3982	static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
3983	DeviceState dev, Error *errp)
3984	{
3985	VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3986	Error *local_err = NULL;
3987
3988	hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
3989	if (local_err) {
3990	goto out;
3991	}
3992
3993	pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
3994	qdev_unrealize(dev);
3995
3996	out:
3997	error_propagate(errp, local_err);
3998	}
3999
4000	static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
4001	DeviceState dev, Error *errp)
4002	{
4003	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4004	virt_dimm_unplug_request(hotplug_dev, dev, errp);
4005	} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
4006	virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
4007	errp);
4008	} else {
4009	error_setg(errp, "device unplug request for unsupported device"
4010	" type: %s", object_get_typename(OBJECT(dev)));
4011	}
4012	}
4013
4014	static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
4015	DeviceState dev, Error *errp)
4016	{
4017	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4018	virt_dimm_unplug(hotplug_dev, dev, errp);
4019	} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
4020	virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
4021	} else {
4022	error_setg(errp, "virt: device unplug for unsupported device"
4023	" type: %s", object_get_typename(OBJECT(dev)));
4024	}
4025	}
4026
4027	static HotplugHandler virt_machine_get_hotplug_handler(MachineState machine,
4028	DeviceState *dev)
4029	{
4030	MachineClass *mc = MACHINE_GET_CLASS(machine);
4031
4032	if (device_is_dynamic_sysbus(mc, dev) \|\|
4033	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) \|\|
4034	object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) \|\|
4035	object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
4036	return HOTPLUG_HANDLER(machine);
4037	}
4038	return NULL;
4039	}
4040
4041	/*
4042	* for arm64 kvm_type [7-0] encodes the requested number of bits
4043	* in the IPA address space
4044	*/
4045	static int virt_kvm_type(MachineState ms, const char type_str)
4046	{
4047	VirtMachineState *vms = VIRT_MACHINE(ms);
4048	int max_vm_pa_size, requested_pa_size;
4049	bool fixed_ipa;
4050
4051	max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
4052
4053	/* we freeze the memory map to compute the highest gpa */
4054	virt_set_memmap(vms, max_vm_pa_size);
4055
4056	requested_pa_size = 64 - clz64(vms->highest_gpa);
4057
4058	/*
4059	* KVM requires the IPA size to be at least 32 bits.
4060	*/
4061	if (requested_pa_size < 32) {
4062	requested_pa_size = 32;
4063	}
4064
4065	if (requested_pa_size > max_vm_pa_size) {
4066	error_report("-m and ,maxmem option values "
4067	"require an IPA range (%d bits) larger than "
4068	"the one supported by the host (%d bits)",
4069	requested_pa_size, max_vm_pa_size);
4070	return -1;
4071	}
4072	/*
4073	* We return the requested PA log size, unless KVM only supports
4074	* the implicit legacy 40b IPA setting, in which case the kvm_type
4075	* must be 0.
4076	*/
4077	return fixed_ipa ? 0 : requested_pa_size;
4078	}
4079
4080	static int virt_get_physical_address_range(MachineState *ms,
4081	int default_ipa_size, int max_ipa_size)
4082	{
4083	VirtMachineState *vms = VIRT_MACHINE(ms);
4084
4085	/* We freeze the memory map to compute the highest gpa */
4086	virt_set_memmap(vms, max_ipa_size);
4087
4088	int requested_ipa_size = 64 - clz64(vms->highest_gpa);
4089
4090	/*
4091	* If we're <= the default IPA size just use the default.
4092	* If we're above the default but below the maximum, round up to
4093	* the maximum. hvf/whpx_arch_get_max_ipa_bit_size() conveniently only
4094	* return values that are valid ARM PARange values.
4095	*/
4096	if (requested_ipa_size <= default_ipa_size) {
4097	requested_ipa_size = default_ipa_size;
4098	} else if (requested_ipa_size <= max_ipa_size) {
4099	requested_ipa_size = max_ipa_size;
4100	} else {
4101	error_report("-m and ,maxmem option values "
4102	"require an IPA range (%d bits) larger than "
4103	"the one supported by the host (%d bits)",
4104	requested_ipa_size, max_ipa_size);
4105	return -1;
4106	}
4107
4108	return requested_ipa_size;
4109	}
4110
4111	static bool get_kernel_irqchip_default(const MachineState *ms)
4112	{
4113	VirtMachineState *vms = VIRT_MACHINE(ms);
4114	VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
4115	if (hvf_allowed) {
4116	return !vmc->hvf_no_kernel_irqchip_default;
4117	} else {
4118	return true;
4119	}
4120	}
4121
4122	static const char virt_get_default_cpu_type(const MachineState ms)
4123	{
4124	return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15")
4125	: ARM_CPU_TYPE_NAME("max");
4126	}
4127
4128	static GPtrArray virt_get_valid_cpu_types(const MachineState ms)
4129	{
4130	GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
4131
4132	if (tcg_enabled()) {
4133	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
4134	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
4135	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8")));
4136	}
4137	if (tcg_enabled() && target_aarch64()) {
4138	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
4139	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
4140	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
4141	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76")));
4142	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710")));
4143	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx")));
4144	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
4145	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
4146	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
4147	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9")));
4148	}
4149	if (target_aarch64()) {
4150	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
4151	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
4152	if (kvm_enabled() \|\| hvf_enabled() \|\| whpx_enabled()) {
4153	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
4154	}
4155	}
4156	g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
4157
4158	return vct;
4159	}
4160
4161	static void virt_machine_class_init(ObjectClass oc, const void data)
4162	{
4163	MachineClass *mc = MACHINE_CLASS(oc);
4164	HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4165
4166	mc->init = machvirt_init;
4167	/* Start with max_cpus set to 512, which is the maximum supported by KVM.
4168	* The value may be reduced later when we have more information about the
4169	* configuration of the particular instance.
4170	*/
4171	mc->max_cpus = 512;
4172	machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
4173	machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
4174	machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3);
4175	machine_class_allow_dynamic_sysbus_dev(mc, TYPE_WDT_SBSA);
4176	#ifdef CONFIG_TPM
4177	machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
4178	#endif
4179	mc->block_default_type = IF_VIRTIO;
4180	mc->no_cdrom = 1;
4181	mc->pci_allow_0_address = true;
4182	/* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
4183	mc->minimum_page_bits = 12;
4184	mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
4185	mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
4186	mc->get_default_cpu_type = virt_get_default_cpu_type;
4187	mc->get_valid_cpu_types = virt_get_valid_cpu_types;
4188	mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
4189	mc->kvm_type = virt_kvm_type;
4190	mc->get_physical_address_range = virt_get_physical_address_range;
4191	mc->get_kernel_irqchip_default = get_kernel_irqchip_default;
4192	assert(!mc->get_hotplug_handler);
4193	mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
4194	hc->pre_plug = virt_machine_device_pre_plug_cb;
4195	hc->plug = virt_machine_device_plug_cb;
4196	hc->unplug_request = virt_machine_device_unplug_request_cb;
4197	hc->unplug = virt_machine_device_unplug_cb;
4198	mc->nvdimm_supported = true;
4199	mc->smp_props.clusters_supported = true;
4200
4201	/* Supported caches */
4202	mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
4203	mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
4204	mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
4205	mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
4206	mc->auto_enable_numa_with_memhp = true;
4207	mc->auto_enable_numa_with_memdev = true;
4208	/* platform instead of architectural choice */
4209	mc->cpu_cluster_has_numa_boundary = true;
4210	mc->default_ram_id = "mach-virt.ram";
4211	mc->default_nic = "virtio-net-pci";
4212
4213	object_class_property_add(oc, "acpi", "OnOffAuto",
4214	virt_get_acpi, virt_set_acpi,
4215	NULL, NULL);
4216	object_class_property_set_description(oc, "acpi",
4217	"Enable ACPI");
4218	object_class_property_add_bool(oc, "secure", virt_get_secure,
4219	virt_set_secure);
4220	object_class_property_set_description(oc, "secure",
4221	"Set on/off to enable/disable the ARM "
4222	"Security Extensions (TrustZone)");
4223
4224	object_class_property_add_bool(oc, "virtualization", virt_get_virt,
4225	virt_set_virt);
4226	object_class_property_set_description(oc, "virtualization",
4227	"Set on/off to enable/disable emulating a "
4228	"guest CPU which implements the ARM "
4229	"Virtualization Extensions");
4230
4231	object_class_property_add_bool(oc, "highmem", virt_get_highmem,
4232	virt_set_highmem);
4233	object_class_property_set_description(oc, "highmem",
4234	"Set on/off to enable/disable using "
4235	"physical address space above 32 bits");
4236
4237	object_class_property_add_bool(oc, "compact-highmem",
4238	virt_get_compact_highmem,
4239	virt_set_compact_highmem);
4240	object_class_property_set_description(oc, "compact-highmem",
4241	"Set on/off to enable/disable compact "
4242	"layout for high memory regions");
4243
4244	object_class_property_add_bool(oc, "highmem-redists",
4245	virt_get_highmem_redists,
4246	virt_set_highmem_redists);
4247	object_class_property_set_description(oc, "highmem-redists",
4248	"Set on/off to enable/disable high "
4249	"memory region for GICv3 or GICv4 "
4250	"redistributor");
4251
4252	object_class_property_add_bool(oc, "highmem-ecam",
4253	virt_get_highmem_ecam,
4254	virt_set_highmem_ecam);
4255	object_class_property_set_description(oc, "highmem-ecam",
4256	"Set on/off to enable/disable high "
4257	"memory region for PCI ECAM");
4258
4259	object_class_property_add_bool(oc, "highmem-mmio",
4260	virt_get_highmem_mmio,
4261	virt_set_highmem_mmio);
4262	object_class_property_set_description(oc, "highmem-mmio",
4263	"Set on/off to enable/disable high "
4264	"memory region for PCI MMIO");
4265
4266	object_class_property_add(oc, "highmem-mmio-size", "size",
4267	virt_get_highmem_mmio_size,
4268	virt_set_highmem_mmio_size,
4269	NULL, NULL);
4270	object_class_property_set_description(oc, "highmem-mmio-size",
4271	"Set the high memory region size "
4272	"for PCI MMIO");
4273
4274	object_class_property_add(oc, "virtio-mmio-transports", "uint8",
4275	virt_get_virtio_transports,
4276	virt_set_virtio_transports,
4277	NULL, NULL);
4278	object_class_property_set_description(oc, "virtio-mmio-transports",
4279	"Set the number of virtio-mmio transports to instantiate");
4280
4281	object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
4282	virt_set_gic_version);
4283	object_class_property_set_description(oc, "gic-version",
4284	"Set GIC version. "
4285	"Valid values are 2, 3, 4, x-5, host and max");
4286
4287	object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
4288	object_class_property_set_description(oc, "iommu",
4289	"Set the IOMMU type. "
4290	"Valid values are none and smmuv3");
4291
4292	object_class_property_add_bool(oc, "default-bus-bypass-iommu",
4293	virt_get_default_bus_bypass_iommu,
4294	virt_set_default_bus_bypass_iommu);
4295	object_class_property_set_description(oc, "default-bus-bypass-iommu",
4296	"Set on/off to enable/disable "
4297	"bypass_iommu for default root bus");
4298
4299	object_class_property_add_bool(oc, "ras", virt_get_ras,
4300	virt_set_ras);
4301	object_class_property_set_description(oc, "ras",
4302	"Set on/off to enable/disable reporting host memory errors "
4303	"to a KVM guest using ACPI and guest external abort exceptions");
4304
4305	object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
4306	object_class_property_set_description(oc, "mte",
4307	"Set on/off to enable/disable emulating a "
4308	"guest CPU which implements the ARM "
4309	"Memory Tagging Extension");
4310
4311	object_class_property_add_bool(oc, "its", virt_get_its,
4312	virt_set_its);
4313	object_class_property_set_description(oc, "its",
4314	"Set on/off to enable/disable "
4315	"ITS instantiation");
4316
4317	object_class_property_add_str(oc, "msi", virt_get_msi,
4318	virt_set_msi);
4319	object_class_property_set_description(oc, "msi",
4320	"Set MSI settings. "
4321	"Valid values are auto, gicv2m, its and off");
4322
4323	object_class_property_add_bool(oc, "dtb-randomness",
4324	virt_get_dtb_randomness,
4325	virt_set_dtb_randomness);
4326	object_class_property_set_description(oc, "dtb-randomness",
4327	"Set off to disable passing random or "
4328	"non-deterministic dtb nodes to guest");
4329
4330	object_class_property_add_bool(oc, "dtb-kaslr-seed",
4331	virt_get_dtb_randomness,
4332	virt_set_dtb_randomness);
4333	object_class_property_set_description(oc, "dtb-kaslr-seed",
4334	"Deprecated synonym of dtb-randomness");
4335
4336	object_class_property_add_str(oc, "x-oem-id",
4337	virt_get_oem_id,
4338	virt_set_oem_id);
4339	object_class_property_set_description(oc, "x-oem-id",
4340	"Override the default value of field OEMID "
4341	"in ACPI table header."
4342	"The string may be up to 6 bytes in size");
4343
4344
4345	object_class_property_add_str(oc, "x-oem-table-id",
4346	virt_get_oem_table_id,
4347	virt_set_oem_table_id);
4348	object_class_property_set_description(oc, "x-oem-table-id",
4349	"Override the default value of field OEM Table ID "
4350	"in ACPI table header."
4351	"The string may be up to 8 bytes in size");
4352
4353	}
4354
4355	static void virt_instance_init(Object *obj)
4356	{
4357	VirtMachineState *vms = VIRT_MACHINE(obj);
4358	VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
4359
4360	/* EL3 is disabled by default on virt: this makes us consistent
4361	* between KVM and TCG for this board, and it also allows us to
4362	* boot UEFI blobs which assume no TrustZone support.
4363	*/
4364	vms->secure = false;
4365
4366	/* EL2 is also disabled by default, for similar reasons */
4367	vms->virt = false;
4368
4369	/* High memory is enabled by default */
4370	vms->highmem = true;
4371	vms->highmem_compact = !vmc->no_highmem_compact;
4372	vms->gic_version = VIRT_GIC_VERSION_NOSEL;
4373
4374	vms->highmem_ecam = true;
4375	vms->highmem_mmio = true;
4376	vms->highmem_redists = true;
4377
4378	/* Default allows ITS instantiation if available */
4379	vms->msi_controller = VIRT_MSI_CTRL_AUTO;
4380	/* Allow ITS emulation if the machine version supports it */
4381	vms->tcg_its = !vmc->no_tcg_its;
4382
4383	/* Default disallows iommu instantiation */
4384	vms->iommu = VIRT_IOMMU_NONE;
4385
4386	/* The default root bus is attached to iommu by default */
4387	vms->default_bus_bypass_iommu = false;
4388
4389	/* Default disallows RAS instantiation */
4390	vms->ras = false;
4391
4392	/* MTE is disabled by default. */
4393	vms->mte = false;
4394
4395	/* Supply kaslr-seed and rng-seed by default */
4396	vms->dtb_randomness = true;
4397
4398	vms->irqmap = a15irqmap;
4399
4400	vms->virtio_transports = NUM_VIRTIO_TRANSPORTS;
4401
4402	virt_flash_create(vms);
4403
4404	vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
4405	vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
4406	cxl_machine_init(obj, &vms->cxl_devices_state);
4407
4408	vms->smmuv3_devices = g_ptr_array_new_with_free_func(NULL);
4409	}
4410
4411	static void virt_instance_finalize(Object *obj)
4412	{
4413	VirtMachineState *vms = VIRT_MACHINE(obj);
4414
4415	for (int i = 0; i < ARRAY_SIZE(vms->flash); i++) {
4416	if (vms->flash[i] && !qdev_is_realized(DEVICE(vms->flash[i]))) {
4417	object_unref(OBJECT(vms->flash[i]));
4418	}
4419	}
4420	g_free(vms->oem_id);
4421	g_free(vms->oem_table_id);
4422	g_ptr_array_free(vms->smmuv3_devices, TRUE);
4423	}
4424
4425	static const TypeInfo virt_machine_info = {
4426	.name = TYPE_VIRT_MACHINE,
4427	.parent = TYPE_MACHINE,
4428	.abstract = true,
4429	.instance_size = sizeof(VirtMachineState),
4430	.class_size = sizeof(VirtMachineClass),
4431	.class_init = virt_machine_class_init,
4432	.instance_init = virt_instance_init,
4433	.instance_finalize = virt_instance_finalize,
4434	.interfaces = (const InterfaceInfo[]) {
4435	{ TYPE_HOTPLUG_HANDLER },
4436	{ }
4437	},
4438	};
4439
4440	static void machvirt_machine_init(void)
4441	{
4442	type_register_static(&virt_machine_info);
4443	}
4444	type_init(machvirt_machine_init);
4445
4446	static void virt_machine_11_2_options(MachineClass *mc)
4447	{
4448	}
4449	DEFINE_VIRT_MACHINE_AS_LATEST(11, 2)
4450
4451	static void virt_machine_11_1_options(MachineClass *mc)
4452	{
4453	virt_machine_11_2_options(mc);
4454	compat_props_add(mc->compat_props, hw_compat_11_1, hw_compat_11_1_len);
4455	}
4456	DEFINE_VIRT_MACHINE(11, 1)
4457
4458	static void virt_machine_11_0_options(MachineClass *mc)
4459	{
4460	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4461
4462	virt_machine_11_1_options(mc);
4463	compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);
4464	vmc->hvf_no_kernel_irqchip_default = true;
4465	}
4466	DEFINE_VIRT_MACHINE(11, 0)
4467
4468	static void virt_machine_10_2_options(MachineClass *mc)
4469	{
4470	virt_machine_11_0_options(mc);
4471	compat_props_add(mc->compat_props, hw_compat_10_2, hw_compat_10_2_len);
4472	}
4473	DEFINE_VIRT_MACHINE(10, 2)
4474
4475	static void virt_machine_10_1_options(MachineClass *mc)
4476	{
4477	virt_machine_10_2_options(mc);
4478	mc->smbios_memory_device_size = 2047 * TiB;
4479	compat_props_add(mc->compat_props, hw_compat_10_1, hw_compat_10_1_len);
4480	}
4481	DEFINE_VIRT_MACHINE(10, 1)
4482
4483	static void virt_machine_10_0_options(MachineClass *mc)
4484	{
4485	virt_machine_10_1_options(mc);
4486	compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len);
4487	}
4488	DEFINE_VIRT_MACHINE(10, 0)
4489
4490	static void virt_machine_9_2_options(MachineClass *mc)
4491	{
4492	virt_machine_10_0_options(mc);
4493	compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len);
4494	}
4495	DEFINE_VIRT_MACHINE(9, 2)
4496
4497	static void virt_machine_9_1_options(MachineClass *mc)
4498	{
4499	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4500
4501	virt_machine_9_2_options(mc);
4502	compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
4503	/* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
4504	vmc->no_nested_smmu = true;
4505	}
4506	DEFINE_VIRT_MACHINE(9, 1)
4507
4508	static void virt_machine_9_0_options(MachineClass *mc)
4509	{
4510	virt_machine_9_1_options(mc);
4511	mc->smbios_memory_device_size = 16 * GiB;
4512	compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
4513	}
4514	DEFINE_VIRT_MACHINE(9, 0)
4515
4516	static void virt_machine_8_2_options(MachineClass *mc)
4517	{
4518	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4519
4520	virt_machine_9_0_options(mc);
4521	compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
4522	/*
4523	* Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
4524	* earlier machines. (Exposing it tickles a bug in older EDK2
4525	* guest BIOS binaries.)
4526	*/
4527	vmc->no_ns_el2_virt_timer_irq = true;
4528	}
4529	DEFINE_VIRT_MACHINE(8, 2)
4530
4531	static void virt_machine_8_1_options(MachineClass *mc)
4532	{
4533	virt_machine_8_2_options(mc);
4534	compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
4535	}
4536	DEFINE_VIRT_MACHINE(8, 1)
4537
4538	static void virt_machine_8_0_options(MachineClass *mc)
4539	{
4540	virt_machine_8_1_options(mc);
4541	compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
4542	}
4543	DEFINE_VIRT_MACHINE(8, 0)
4544
4545	static void virt_machine_7_2_options(MachineClass *mc)
4546	{
4547	virt_machine_8_0_options(mc);
4548	compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
4549	}
4550	DEFINE_VIRT_MACHINE(7, 2)
4551
4552	static void virt_machine_7_1_options(MachineClass *mc)
4553	{
4554	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4555
4556	virt_machine_7_2_options(mc);
4557	compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
4558	/* Compact layout for high memory regions was introduced with 7.2 */
4559	vmc->no_highmem_compact = true;
4560	}
4561	DEFINE_VIRT_MACHINE(7, 1)
4562
4563	static void virt_machine_7_0_options(MachineClass *mc)
4564	{
4565	virt_machine_7_1_options(mc);
4566	compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
4567	}
4568	DEFINE_VIRT_MACHINE(7, 0)
4569
4570	static void virt_machine_6_2_options(MachineClass *mc)
4571	{
4572	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4573
4574	virt_machine_7_0_options(mc);
4575	compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
4576	vmc->no_tcg_lpa2 = true;
4577	}
4578	DEFINE_VIRT_MACHINE(6, 2)
4579
4580	static void virt_machine_6_1_options(MachineClass *mc)
4581	{
4582	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4583
4584	virt_machine_6_2_options(mc);
4585	compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
4586	mc->smp_props.prefer_sockets = true;
4587	vmc->no_cpu_topology = true;
4588
4589	/* qemu ITS was introduced with 6.2 */
4590	vmc->no_tcg_its = true;
4591	}
4592	DEFINE_VIRT_MACHINE(6, 1)
4593
4594	static void virt_machine_6_0_options(MachineClass *mc)
4595	{
4596	virt_machine_6_1_options(mc);
4597	compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
4598	}
4599	DEFINE_VIRT_MACHINE(6, 0)
4600
4601	static void virt_machine_5_2_options(MachineClass *mc)
4602	{
4603	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4604
4605	virt_machine_6_0_options(mc);
4606	compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
4607	vmc->no_secure_gpio = true;
4608	}
4609	DEFINE_VIRT_MACHINE(5, 2)
4610
4611	static void virt_machine_5_1_options(MachineClass *mc)
4612	{
4613	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4614
4615	virt_machine_5_2_options(mc);
4616	compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
4617	vmc->no_kvm_steal_time = true;
4618	}
4619	DEFINE_VIRT_MACHINE(5, 1)
4620
4621	static void virt_machine_5_0_options(MachineClass *mc)
4622	{
4623	VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
4624
4625	virt_machine_5_1_options(mc);
4626	compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
4627	mc->numa_mem_supported = true;
4628	vmc->acpi_expose_flash = true;
4629	mc->auto_enable_numa_with_memdev = false;
4630	}
4631	DEFINE_VIRT_MACHINE(5, 0)