| 1 | /* |
| 2 | * Xilinx Zynq Baseboard System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2010 Xilinx. |
| 5 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) |
| 6 | * Copyright (c) 2012 Petalogix Pty Ltd. |
| 7 | * Written by Haibing Ma |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #include "qemu/osdep.h" |
| 19 | #include "qemu/units.h" |
| 20 | #include "qapi/error.h" |
| 21 | #include "hw/core/sysbus.h" |
| 22 | #include "hw/arm/boot.h" |
| 23 | #include "hw/arm/machines-qom.h" |
| 24 | #include "net/net.h" |
| 25 | #include "system/system.h" |
| 26 | #include "hw/core/boards.h" |
| 27 | #include "hw/block/flash.h" |
| 28 | #include "hw/core/loader.h" |
| 29 | #include "hw/adc/zynq-xadc.h" |
| 30 | #include "hw/ssi/ssi.h" |
| 31 | #include "hw/usb/chipidea.h" |
| 32 | #include "qemu/error-report.h" |
| 33 | #include "hw/sd/sdhci.h" |
| 34 | #include "hw/char/cadence_uart.h" |
| 35 | #include "hw/net/cadence_gem.h" |
| 36 | #include "hw/cpu/a9mpcore.h" |
| 37 | #include "hw/core/qdev-clock.h" |
| 38 | #include "hw/misc/unimp.h" |
| 39 | #include "system/reset.h" |
| 40 | #include "qom/object.h" |
| 41 | #include "exec/tswap.h" |
| 42 | #include "target/arm/cpu-qom.h" |
| 43 | #include "qapi/visitor.h" |
| 44 | #include "hw/arm/xilinx_zynq.h" |
| 45 | |
| 46 | /* board base frequency: 33.333333 MHz */ |
| 47 | #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) |
| 48 | |
| 49 | #define NUM_SPI_FLASHES 4 |
| 50 | #define NUM_QSPI_FLASHES 2 |
| 51 | #define NUM_QSPI_BUSSES 2 |
| 52 | |
| 53 | #define FLASH_SIZE (64 * 1024 * 1024) |
| 54 | #define FLASH_SECTOR_SIZE (128 * 1024) |
| 55 | |
| 56 | #define MPCORE_PERIPHBASE 0xF8F00000 |
| 57 | #define ZYNQ_BOARD_MIDR 0x413FC090 |
| 58 | |
| 59 | #define GIC_EXT_IRQS 64 /* Zynq 7000 SoC */ |
| 60 | |
| 61 | static const int dma_irqs[8] = { |
| 62 | 46, 47, 48, 49, 72, 73, 74, 75 |
| 63 | }; |
| 64 | |
| 65 | #define BOARD_SETUP_ADDR 0x100 |
| 66 | |
| 67 | #define SLCR_LOCK_OFFSET 0x004 |
| 68 | #define SLCR_UNLOCK_OFFSET 0x008 |
| 69 | #define SLCR_ARM_PLL_OFFSET 0x100 |
| 70 | |
| 71 | #define SLCR_XILINX_UNLOCK_KEY 0xdf0d |
| 72 | #define SLCR_XILINX_LOCK_KEY 0x767b |
| 73 | |
| 74 | #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ |
| 75 | |
| 76 | #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ |
| 77 | extract32((x), 12, 4) << 16) |
| 78 | |
| 79 | /* Write immediate val to address r0 + addr. r0 should contain base offset |
| 80 | * of the SLCR block. Clobbers r1. |
| 81 | */ |
| 82 | |
| 83 | #define SLCR_WRITE(addr, val) \ |
| 84 | 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ |
| 85 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ |
| 86 | 0xe5801000 + (addr) |
| 87 | |
| 88 | static void zynq_write_board_setup(ARMCPU *cpu, |
| 89 | const struct arm_boot_info *info) |
| 90 | { |
| 91 | int n; |
| 92 | uint32_t board_setup_blob[] = { |
| 93 | 0xe3a004f8, /* mov r0, #0xf8000000 */ |
| 94 | SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), |
| 95 | SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), |
| 96 | SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), |
| 97 | 0xe12fff1e, /* bx lr */ |
| 98 | }; |
| 99 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { |
| 100 | board_setup_blob[n] = tswap32(board_setup_blob[n]); |
| 101 | } |
| 102 | rom_add_blob_fixed("board-setup", board_setup_blob, |
| 103 | sizeof(board_setup_blob), BOARD_SETUP_ADDR); |
| 104 | } |
| 105 | |
| 106 | static void gem_init(uint32_t base, qemu_irq irq) |
| 107 | { |
| 108 | DeviceState *dev; |
| 109 | SysBusDevice *s; |
| 110 | |
| 111 | dev = qdev_new(TYPE_CADENCE_GEM); |
| 112 | qemu_configure_nic_device(dev, true, NULL); |
| 113 | object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); |
| 114 | s = SYS_BUS_DEVICE(dev); |
| 115 | sysbus_realize_and_unref(s, &error_fatal); |
| 116 | sysbus_mmio_map(s, 0, base); |
| 117 | sysbus_connect_irq(s, 0, irq); |
| 118 | } |
| 119 | |
| 120 | static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, |
| 121 | bool is_qspi, int unit0) |
| 122 | { |
| 123 | int unit = unit0; |
| 124 | DeviceState *dev; |
| 125 | SysBusDevice *busdev; |
| 126 | SSIBus *spi; |
| 127 | DeviceState *flash_dev; |
| 128 | int i, j; |
| 129 | int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; |
| 130 | int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; |
| 131 | |
| 132 | dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); |
| 133 | qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); |
| 134 | qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); |
| 135 | qdev_prop_set_uint8(dev, "num-busses", num_busses); |
| 136 | busdev = SYS_BUS_DEVICE(dev); |
| 137 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 138 | sysbus_mmio_map(busdev, 0, base_addr); |
| 139 | if (is_qspi) { |
| 140 | sysbus_mmio_map(busdev, 1, 0xFC000000); |
| 141 | } |
| 142 | sysbus_connect_irq(busdev, 0, irq); |
| 143 | |
| 144 | for (i = 0; i < num_busses; ++i) { |
| 145 | char bus_name[16]; |
| 146 | qemu_irq cs_line; |
| 147 | |
| 148 | snprintf(bus_name, 16, "spi%d", i); |
| 149 | spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); |
| 150 | |
| 151 | for (j = 0; j < num_ss; ++j) { |
| 152 | DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); |
| 153 | flash_dev = qdev_new("n25q128"); |
| 154 | if (dinfo) { |
| 155 | qdev_prop_set_drive_err(flash_dev, "drive", |
| 156 | blk_by_legacy_dinfo(dinfo), |
| 157 | &error_fatal); |
| 158 | } |
| 159 | qdev_prop_set_uint8(flash_dev, "cs", j); |
| 160 | qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); |
| 161 | |
| 162 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
| 163 | sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | return unit; |
| 168 | } |
| 169 | |
| 170 | static void zynq_set_boot_mode(Object *obj, const char *str, |
| 171 | Error **errp) |
| 172 | { |
| 173 | ZynqMachineState *m = ZYNQ_MACHINE(obj); |
| 174 | uint8_t mode = 0; |
| 175 | |
| 176 | if (!g_ascii_strcasecmp(str, "qspi")) { |
| 177 | mode = 1; |
| 178 | } else if (!g_ascii_strcasecmp(str, "sd")) { |
| 179 | mode = 5; |
| 180 | } else if (!g_ascii_strcasecmp(str, "nor")) { |
| 181 | mode = 2; |
| 182 | } else if (!g_ascii_strcasecmp(str, "jtag")) { |
| 183 | mode = 0; |
| 184 | } else { |
| 185 | error_setg(errp, "%s boot mode not supported", str); |
| 186 | return; |
| 187 | } |
| 188 | m->boot_mode = mode; |
| 189 | } |
| 190 | |
| 191 | static void ddr_ctrl_init(uint32_t base) |
| 192 | { |
| 193 | DeviceState *dev; |
| 194 | SysBusDevice *busdev; |
| 195 | |
| 196 | dev = qdev_new("zynq.ddr-ctlr"); |
| 197 | busdev = SYS_BUS_DEVICE(dev); |
| 198 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 199 | sysbus_mmio_map(busdev, 0, base); |
| 200 | } |
| 201 | |
| 202 | static void zynq_init(MachineState *machine) |
| 203 | { |
| 204 | ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); |
| 205 | MemoryRegion *address_space_mem = get_system_memory(); |
| 206 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); |
| 207 | DeviceState *dev, *slcr; |
| 208 | SysBusDevice *busdev; |
| 209 | qemu_irq pic[GIC_EXT_IRQS]; |
| 210 | int n; |
| 211 | unsigned int smp_cpus = machine->smp.cpus; |
| 212 | |
| 213 | /* max 2GB ram */ |
| 214 | if (machine->ram_size > 2 * GiB) { |
| 215 | error_report("RAM size more than 2 GiB is not supported"); |
| 216 | exit(EXIT_FAILURE); |
| 217 | } |
| 218 | |
| 219 | for (n = 0; n < smp_cpus; n++) { |
| 220 | Object *cpuobj = object_new(machine->cpu_type); |
| 221 | |
| 222 | object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR, |
| 223 | &error_fatal); |
| 224 | object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, |
| 225 | &error_fatal); |
| 226 | |
| 227 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 228 | |
| 229 | zynq_machine->cpu[n] = ARM_CPU(cpuobj); |
| 230 | } |
| 231 | |
| 232 | /* DDR remapped to address zero. */ |
| 233 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
| 234 | |
| 235 | /* 256K of on-chip memory */ |
| 236 | memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, |
| 237 | &error_fatal); |
| 238 | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); |
| 239 | |
| 240 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
| 241 | |
| 242 | /* AMD */ |
| 243 | pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, |
| 244 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
| 245 | FLASH_SECTOR_SIZE, 1, |
| 246 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, |
| 247 | 0); |
| 248 | |
| 249 | /* Create the main clock source, and feed slcr with it */ |
| 250 | zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); |
| 251 | object_property_add_child(OBJECT(zynq_machine), "ps_clk", |
| 252 | OBJECT(zynq_machine->ps_clk)); |
| 253 | object_unref(OBJECT(zynq_machine->ps_clk)); |
| 254 | clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); |
| 255 | |
| 256 | /* Create slcr, keep a pointer to connect clocks */ |
| 257 | slcr = qdev_new("xilinx-zynq_slcr"); |
| 258 | qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); |
| 259 | qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); |
| 260 | sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); |
| 261 | sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); |
| 262 | |
| 263 | dev = qdev_new(TYPE_A9MPCORE_PRIV); |
| 264 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
| 265 | qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); |
| 266 | busdev = SYS_BUS_DEVICE(dev); |
| 267 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 268 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
| 269 | zynq_machine->bootinfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100; |
| 270 | sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); |
| 271 | for (n = 0; n < smp_cpus; n++) { |
| 272 | /* See "hw/intc/arm_gic.h" for the IRQ line association */ |
| 273 | DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]); |
| 274 | sysbus_connect_irq(busdev, n, |
| 275 | qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
| 276 | sysbus_connect_irq(busdev, smp_cpus + n, |
| 277 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); |
| 278 | } |
| 279 | |
| 280 | for (n = 0; n < GIC_EXT_IRQS; n++) { |
| 281 | pic[n] = qdev_get_gpio_in(dev, n); |
| 282 | } |
| 283 | |
| 284 | n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0); |
| 285 | n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n); |
| 286 | n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n); |
| 287 | |
| 288 | sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]); |
| 289 | sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]); |
| 290 | |
| 291 | dev = qdev_new(TYPE_CADENCE_UART); |
| 292 | busdev = SYS_BUS_DEVICE(dev); |
| 293 | qdev_prop_set_chr(dev, "chardev", serial_hd(0)); |
| 294 | qdev_connect_clock_in(dev, "refclk", |
| 295 | qdev_get_clock_out(slcr, "uart0_ref_clk")); |
| 296 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 297 | sysbus_mmio_map(busdev, 0, 0xE0000000); |
| 298 | sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]); |
| 299 | dev = qdev_new(TYPE_CADENCE_UART); |
| 300 | busdev = SYS_BUS_DEVICE(dev); |
| 301 | qdev_prop_set_chr(dev, "chardev", serial_hd(1)); |
| 302 | qdev_connect_clock_in(dev, "refclk", |
| 303 | qdev_get_clock_out(slcr, "uart1_ref_clk")); |
| 304 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 305 | sysbus_mmio_map(busdev, 0, 0xE0001000); |
| 306 | sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]); |
| 307 | |
| 308 | sysbus_create_varargs("cadence_ttc", 0xF8001000, |
| 309 | pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL); |
| 310 | sysbus_create_varargs("cadence_ttc", 0xF8002000, |
| 311 | pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL); |
| 312 | |
| 313 | ddr_ctrl_init(0xF8006000); |
| 314 | |
| 315 | gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); |
| 316 | gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); |
| 317 | |
| 318 | for (n = 0; n < 2; n++) { |
| 319 | int hci_irq = n ? 79 : 56; |
| 320 | hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; |
| 321 | DriveInfo *di; |
| 322 | BlockBackend *blk; |
| 323 | DeviceState *carddev; |
| 324 | |
| 325 | /* Compatible with: |
| 326 | * - SD Host Controller Specification Version 2.0 Part A2 |
| 327 | * - SDIO Specification Version 2.0 |
| 328 | * - MMC Specification Version 3.31 |
| 329 | */ |
| 330 | dev = qdev_new(TYPE_SYSBUS_SDHCI); |
| 331 | qdev_prop_set_uint8(dev, "sd-spec-version", 2); |
| 332 | qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); |
| 333 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 334 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); |
| 335 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]); |
| 336 | |
| 337 | di = drive_get(IF_SD, 0, n); |
| 338 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
| 339 | carddev = qdev_new(TYPE_SD_CARD); |
| 340 | qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); |
| 341 | qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), |
| 342 | &error_fatal); |
| 343 | } |
| 344 | |
| 345 | dev = qdev_new(TYPE_ZYNQ_XADC); |
| 346 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 347 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); |
| 348 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]); |
| 349 | |
| 350 | dev = qdev_new("pl330"); |
| 351 | object_property_set_link(OBJECT(dev), "memory", |
| 352 | OBJECT(address_space_mem), |
| 353 | &error_fatal); |
| 354 | qdev_prop_set_uint8(dev, "num_chnls", 8); |
| 355 | qdev_prop_set_uint8(dev, "num_periph_req", 4); |
| 356 | qdev_prop_set_uint8(dev, "num_events", 16); |
| 357 | |
| 358 | qdev_prop_set_uint8(dev, "data_width", 64); |
| 359 | qdev_prop_set_uint8(dev, "wr_cap", 8); |
| 360 | qdev_prop_set_uint8(dev, "wr_q_dep", 16); |
| 361 | qdev_prop_set_uint8(dev, "rd_cap", 8); |
| 362 | qdev_prop_set_uint8(dev, "rd_q_dep", 16); |
| 363 | qdev_prop_set_uint16(dev, "data_buffer_dep", 256); |
| 364 | |
| 365 | busdev = SYS_BUS_DEVICE(dev); |
| 366 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 367 | sysbus_mmio_map(busdev, 0, 0xF8003000); |
| 368 | sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */ |
| 369 | for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ |
| 370 | sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]); |
| 371 | } |
| 372 | |
| 373 | dev = qdev_new("xlnx.ps7-dev-cfg"); |
| 374 | busdev = SYS_BUS_DEVICE(dev); |
| 375 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 376 | sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]); |
| 377 | sysbus_mmio_map(busdev, 0, 0xF8007000); |
| 378 | |
| 379 | /* |
| 380 | * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and |
| 381 | * the zynq-7000.dtsi. Add placeholders for unimplemented devices. |
| 382 | */ |
| 383 | create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB); |
| 384 | create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB); |
| 385 | create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB); |
| 386 | create_unimplemented_device("zynq.can1", 0xE0009000, 4 * KiB); |
| 387 | create_unimplemented_device("zynq.gpio", 0xE000A000, 4 * KiB); |
| 388 | create_unimplemented_device("zynq.smcc", 0xE000E000, 4 * KiB); |
| 389 | |
| 390 | /* Direct Memory Access Controller, PL330, Non-Secure Mode */ |
| 391 | create_unimplemented_device("zynq.dma_ns", 0xF8004000, 4 * KiB); |
| 392 | |
| 393 | /* System Watchdog Timer Registers */ |
| 394 | create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB); |
| 395 | |
| 396 | /* AXI_HP Interface (AFI) */ |
| 397 | create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28); |
| 398 | create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28); |
| 399 | create_unimplemented_device("zynq.axi_hp2", 0xF800A000, 0x28); |
| 400 | create_unimplemented_device("zynq.axi_hp3", 0xF800B000, 0x28); |
| 401 | |
| 402 | create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20); |
| 403 | |
| 404 | /* Embedded Trace Buffer */ |
| 405 | create_unimplemented_device("zynq.etb", 0xF8801000, 4 * KiB); |
| 406 | |
| 407 | /* Cross Trigger Interface, ETB and TPIU */ |
| 408 | create_unimplemented_device("zynq.cti_etb_tpiu", 0xF8802000, 4 * KiB); |
| 409 | |
| 410 | /* Trace Port Interface Unit */ |
| 411 | create_unimplemented_device("zynq.tpiu", 0xF8803000, 4 * KiB); |
| 412 | |
| 413 | /* CoreSight Trace Funnel */ |
| 414 | create_unimplemented_device("zynq.funnel", 0xF8804000, 4 * KiB); |
| 415 | |
| 416 | /* Instrumentation Trace Macrocell */ |
| 417 | create_unimplemented_device("zynq.itm", 0xF8805000, 4 * KiB); |
| 418 | |
| 419 | /* Cross Trigger Interface, FTM */ |
| 420 | create_unimplemented_device("zynq.cti_ftm", 0xF8809000, 4 * KiB); |
| 421 | |
| 422 | /* Fabric Trace Macrocell */ |
| 423 | create_unimplemented_device("zynq.ftm", 0xF880B000, 4 * KiB); |
| 424 | |
| 425 | /* Cortex A9 Performance Monitoring Unit, CPU */ |
| 426 | create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB); |
| 427 | create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB); |
| 428 | |
| 429 | /* Cross Trigger Interface, CPU */ |
| 430 | create_unimplemented_device("zynq.cpu_cti0", 0xF8898000, 4 * KiB); |
| 431 | create_unimplemented_device("zynq.cpu_cti1", 0xF8899000, 4 * KiB); |
| 432 | |
| 433 | /* CoreSight PTM-A9, CPU */ |
| 434 | create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB); |
| 435 | create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB); |
| 436 | |
| 437 | /* AMBA NIC301 TrustZone */ |
| 438 | create_unimplemented_device("zynq.trustZone", 0xF8900000, 0x20); |
| 439 | |
| 440 | /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */ |
| 441 | create_unimplemented_device("zynq.qos301_cpu", 0xF8946000, 0x130); |
| 442 | create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130); |
| 443 | create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130); |
| 444 | |
| 445 | zynq_machine->bootinfo.ram_size = machine->ram_size; |
| 446 | zynq_machine->bootinfo.board_id = 0xd32; |
| 447 | zynq_machine->bootinfo.loader_start = 0; |
| 448 | zynq_machine->bootinfo.board_setup_addr = BOARD_SETUP_ADDR; |
| 449 | zynq_machine->bootinfo.write_board_setup = zynq_write_board_setup; |
| 450 | |
| 451 | arm_load_kernel(zynq_machine->cpu[0], machine, |
| 452 | &zynq_machine->bootinfo); |
| 453 | } |
| 454 | |
| 455 | static void zynq_machine_class_init(ObjectClass *oc, const void *data) |
| 456 | { |
| 457 | static const char * const valid_cpu_types[] = { |
| 458 | ARM_CPU_TYPE_NAME("cortex-a9"), |
| 459 | NULL |
| 460 | }; |
| 461 | MachineClass *mc = MACHINE_CLASS(oc); |
| 462 | ObjectProperty *prop; |
| 463 | mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9"; |
| 464 | mc->init = zynq_init; |
| 465 | mc->max_cpus = ZYNQ_MAX_CPUS; |
| 466 | mc->ignore_memory_transaction_failures = true; |
| 467 | mc->valid_cpu_types = valid_cpu_types; |
| 468 | mc->default_ram_id = "zynq.ext_ram"; |
| 469 | prop = object_class_property_add_str(oc, "boot-mode", NULL, |
| 470 | zynq_set_boot_mode); |
| 471 | object_class_property_set_description(oc, "boot-mode", |
| 472 | "Supported boot modes:" |
| 473 | " jtag qspi sd nor"); |
| 474 | object_property_set_default_str(prop, "qspi"); |
| 475 | } |
| 476 | |
| 477 | static const TypeInfo zynq_machine_type = { |
| 478 | .name = TYPE_ZYNQ_MACHINE, |
| 479 | .parent = TYPE_MACHINE, |
| 480 | .class_init = zynq_machine_class_init, |
| 481 | .instance_size = sizeof(ZynqMachineState), |
| 482 | .interfaces = arm_machine_interfaces, |
| 483 | }; |
| 484 | |
| 485 | static void zynq_machine_register_types(void) |
| 486 | { |
| 487 | type_register_static(&zynq_machine_type); |
| 488 | } |
| 489 | |
| 490 | type_init(zynq_machine_register_types) |