| 1 | /* |
| 2 | * Xilinx Zynq MPSoC emulation |
| 3 | * |
| 4 | * Copyright (C) 2015 Xilinx Inc |
| 5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 15 | * for more details. |
| 16 | */ |
| 17 | |
| 18 | #include "qemu/osdep.h" |
| 19 | #include "qapi/error.h" |
| 20 | #include "qemu/module.h" |
| 21 | #include "hw/arm/xlnx-zynqmp.h" |
| 22 | #include "hw/intc/arm_gic_common.h" |
| 23 | #include "hw/misc/unimp.h" |
| 24 | #include "hw/core/boards.h" |
| 25 | #include "system/system.h" |
| 26 | #include "target/arm/cpu-qom.h" |
| 27 | #include "target/arm/gtimer.h" |
| 28 | |
| 29 | #define ARM_PHYS_TIMER_PPI 30 |
| 30 | #define ARM_VIRT_TIMER_PPI 27 |
| 31 | #define ARM_HYP_TIMER_PPI 26 |
| 32 | #define ARM_SEC_TIMER_PPI 29 |
| 33 | #define GIC_MAINTENANCE_PPI 25 |
| 34 | |
| 35 | #define GEM_REVISION 0x40070106 |
| 36 | |
| 37 | #define GIC_BASE_ADDR 0xf9000000 |
| 38 | #define GIC_DIST_ADDR 0xf9010000 |
| 39 | #define GIC_CPU_ADDR 0xf9020000 |
| 40 | #define GIC_VIFACE_ADDR 0xf9040000 |
| 41 | #define GIC_VCPU_ADDR 0xf9060000 |
| 42 | |
| 43 | #define SATA_INTR 133 |
| 44 | #define SATA_ADDR 0xFD0C0000 |
| 45 | #define SATA_NUM_PORTS 2 |
| 46 | |
| 47 | #define QSPI_ADDR 0xff0f0000 |
| 48 | #define LQSPI_ADDR 0xc0000000 |
| 49 | #define QSPI_IRQ 15 |
| 50 | #define QSPI_DMA_ADDR 0xff0f0800 |
| 51 | #define NUM_QSPI_IRQ_LINES 2 |
| 52 | |
| 53 | #define CRF_ADDR 0xfd1a0000 |
| 54 | #define CRF_IRQ 120 |
| 55 | |
| 56 | /* Serializer/Deserializer. */ |
| 57 | #define SERDES_ADDR 0xfd400000 |
| 58 | #define SERDES_SIZE 0x20000 |
| 59 | |
| 60 | #define DP_ADDR 0xfd4a0000 |
| 61 | #define DP_IRQ 0x77 |
| 62 | |
| 63 | #define DPDMA_ADDR 0xfd4c0000 |
| 64 | #define DPDMA_IRQ 0x7a |
| 65 | |
| 66 | #define APU_ADDR 0xfd5c0000 |
| 67 | #define APU_IRQ 153 |
| 68 | |
| 69 | #define TTC0_ADDR 0xFF110000 |
| 70 | #define TTC0_IRQ 36 |
| 71 | |
| 72 | #define IPI_ADDR 0xFF300000 |
| 73 | #define IPI_IRQ 64 |
| 74 | |
| 75 | #define RTC_ADDR 0xffa60000 |
| 76 | #define RTC_IRQ 26 |
| 77 | |
| 78 | #define BBRAM_ADDR 0xffcd0000 |
| 79 | #define BBRAM_IRQ 11 |
| 80 | |
| 81 | #define EFUSE_ADDR 0xffcc0000 |
| 82 | #define EFUSE_IRQ 87 |
| 83 | |
| 84 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ |
| 85 | |
| 86 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { |
| 87 | 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, |
| 88 | }; |
| 89 | |
| 90 | static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { |
| 91 | 57, 59, 61, 63, |
| 92 | }; |
| 93 | |
| 94 | static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { |
| 95 | 0xFF000000, 0xFF010000, |
| 96 | }; |
| 97 | |
| 98 | static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { |
| 99 | 21, 22, |
| 100 | }; |
| 101 | |
| 102 | static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { |
| 103 | 0xFF060000, 0xFF070000, |
| 104 | }; |
| 105 | |
| 106 | static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { |
| 107 | 23, 24, |
| 108 | }; |
| 109 | |
| 110 | static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { |
| 111 | 0xFF160000, 0xFF170000, |
| 112 | }; |
| 113 | |
| 114 | static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { |
| 115 | 48, 49, |
| 116 | }; |
| 117 | |
| 118 | static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { |
| 119 | 0xFF040000, 0xFF050000, |
| 120 | }; |
| 121 | |
| 122 | static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { |
| 123 | 19, 20, |
| 124 | }; |
| 125 | |
| 126 | static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { |
| 127 | 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, |
| 128 | 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 |
| 129 | }; |
| 130 | |
| 131 | static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { |
| 132 | 124, 125, 126, 127, 128, 129, 130, 131 |
| 133 | }; |
| 134 | |
| 135 | static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { |
| 136 | 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, |
| 137 | 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 |
| 138 | }; |
| 139 | |
| 140 | static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { |
| 141 | 77, 78, 79, 80, 81, 82, 83, 84 |
| 142 | }; |
| 143 | |
| 144 | static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = { |
| 145 | 0xFE200000, 0xFE300000 |
| 146 | }; |
| 147 | |
| 148 | static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = { |
| 149 | 65, 70 |
| 150 | }; |
| 151 | |
| 152 | typedef struct XlnxZynqMPGICRegion { |
| 153 | int region_index; |
| 154 | uint32_t address; |
| 155 | uint32_t offset; |
| 156 | bool virt; |
| 157 | } XlnxZynqMPGICRegion; |
| 158 | |
| 159 | static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { |
| 160 | /* Distributor */ |
| 161 | { |
| 162 | .region_index = 0, |
| 163 | .address = GIC_DIST_ADDR, |
| 164 | .offset = 0, |
| 165 | .virt = false |
| 166 | }, |
| 167 | |
| 168 | /* CPU interface */ |
| 169 | { |
| 170 | .region_index = 1, |
| 171 | .address = GIC_CPU_ADDR, |
| 172 | .offset = 0, |
| 173 | .virt = false |
| 174 | }, |
| 175 | { |
| 176 | .region_index = 1, |
| 177 | .address = GIC_CPU_ADDR + 0x10000, |
| 178 | .offset = 0x1000, |
| 179 | .virt = false |
| 180 | }, |
| 181 | |
| 182 | /* Virtual interface */ |
| 183 | { |
| 184 | .region_index = 2, |
| 185 | .address = GIC_VIFACE_ADDR, |
| 186 | .offset = 0, |
| 187 | .virt = true |
| 188 | }, |
| 189 | |
| 190 | /* Virtual CPU interface */ |
| 191 | { |
| 192 | .region_index = 3, |
| 193 | .address = GIC_VCPU_ADDR, |
| 194 | .offset = 0, |
| 195 | .virt = true |
| 196 | }, |
| 197 | { |
| 198 | .region_index = 3, |
| 199 | .address = GIC_VCPU_ADDR + 0x10000, |
| 200 | .offset = 0x1000, |
| 201 | .virt = true |
| 202 | }, |
| 203 | }; |
| 204 | |
| 205 | static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) |
| 206 | { |
| 207 | return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; |
| 208 | } |
| 209 | |
| 210 | static unsigned int xlnx_zynqmp_get_rpu_number(MachineState *ms) |
| 211 | { |
| 212 | /* |
| 213 | * RPUs will be created only if "-smp" is higher than the maximum |
| 214 | * of APUs. Round it up to 0 to avoid dealing with negative values. |
| 215 | */ |
| 216 | return MAX(0, MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), |
| 217 | XLNX_ZYNQMP_NUM_RPU_CPUS)); |
| 218 | } |
| 219 | |
| 220 | static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, |
| 221 | const char *boot_cpu, Error **errp) |
| 222 | { |
| 223 | int i; |
| 224 | int num_rpus = xlnx_zynqmp_get_rpu_number(ms); |
| 225 | |
| 226 | if (!num_rpus) { |
| 227 | /* Don't create rpu-cluster object if there's nothing to put in it */ |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, |
| 232 | TYPE_CPU_CLUSTER); |
| 233 | qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); |
| 234 | |
| 235 | for (i = 0; i < num_rpus; i++) { |
| 236 | const char *name; |
| 237 | |
| 238 | object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", |
| 239 | &s->rpu_cpu[i], |
| 240 | ARM_CPU_TYPE_NAME("cortex-r5f")); |
| 241 | |
| 242 | name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); |
| 243 | if (strcmp(name, boot_cpu)) { |
| 244 | /* |
| 245 | * Secondary CPUs start in powered-down state. |
| 246 | */ |
| 247 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), |
| 248 | "start-powered-off", true, &error_abort); |
| 249 | } else { |
| 250 | s->boot_cpu_ptr = &s->rpu_cpu[i]; |
| 251 | } |
| 252 | |
| 253 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, |
| 254 | &error_abort); |
| 255 | if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { |
| 256 | return; |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); |
| 261 | } |
| 262 | |
| 263 | static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) |
| 264 | { |
| 265 | SysBusDevice *sbd; |
| 266 | |
| 267 | object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, |
| 268 | sizeof(s->bbram), TYPE_XLNX_BBRAM, |
| 269 | &error_fatal, |
| 270 | "crc-zpads", "1", |
| 271 | NULL); |
| 272 | sbd = SYS_BUS_DEVICE(&s->bbram); |
| 273 | |
| 274 | sysbus_realize(sbd, &error_fatal); |
| 275 | sysbus_mmio_map(sbd, 0, BBRAM_ADDR); |
| 276 | sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); |
| 277 | } |
| 278 | |
| 279 | static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) |
| 280 | { |
| 281 | Object *bits = OBJECT(&s->efuse); |
| 282 | Object *ctrl = OBJECT(&s->efuse_ctrl); |
| 283 | SysBusDevice *sbd; |
| 284 | |
| 285 | object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, |
| 286 | TYPE_XLNX_ZYNQMP_EFUSE); |
| 287 | |
| 288 | object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, |
| 289 | sizeof(s->efuse), |
| 290 | TYPE_XLNX_EFUSE, &error_abort, |
| 291 | "efuse-nr", "3", |
| 292 | "efuse-size", "2048", |
| 293 | NULL); |
| 294 | |
| 295 | qdev_realize(DEVICE(bits), NULL, &error_abort); |
| 296 | object_property_set_link(ctrl, "efuse", bits, &error_abort); |
| 297 | |
| 298 | sbd = SYS_BUS_DEVICE(ctrl); |
| 299 | sysbus_realize(sbd, &error_abort); |
| 300 | sysbus_mmio_map(sbd, 0, EFUSE_ADDR); |
| 301 | sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); |
| 302 | } |
| 303 | |
| 304 | static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) |
| 305 | { |
| 306 | SysBusDevice *sbd; |
| 307 | int i; |
| 308 | |
| 309 | object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, |
| 310 | TYPE_XLNX_ZYNQMP_APU_CTRL); |
| 311 | sbd = SYS_BUS_DEVICE(&s->apu_ctrl); |
| 312 | |
| 313 | for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { |
| 314 | g_autofree gchar *name = g_strdup_printf("cpu%d", i); |
| 315 | |
| 316 | object_property_set_link(OBJECT(&s->apu_ctrl), name, |
| 317 | OBJECT(&s->apu_cpu[i]), &error_abort); |
| 318 | } |
| 319 | |
| 320 | sysbus_realize(sbd, &error_fatal); |
| 321 | sysbus_mmio_map(sbd, 0, APU_ADDR); |
| 322 | sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); |
| 323 | } |
| 324 | |
| 325 | static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) |
| 326 | { |
| 327 | SysBusDevice *sbd; |
| 328 | |
| 329 | object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); |
| 330 | sbd = SYS_BUS_DEVICE(&s->crf); |
| 331 | |
| 332 | sysbus_realize(sbd, &error_fatal); |
| 333 | sysbus_mmio_map(sbd, 0, CRF_ADDR); |
| 334 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); |
| 335 | } |
| 336 | |
| 337 | static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) |
| 338 | { |
| 339 | SysBusDevice *sbd; |
| 340 | int i, irq; |
| 341 | |
| 342 | for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { |
| 343 | object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], |
| 344 | TYPE_CADENCE_TTC); |
| 345 | sbd = SYS_BUS_DEVICE(&s->ttc[i]); |
| 346 | |
| 347 | sysbus_realize(sbd, &error_fatal); |
| 348 | sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); |
| 349 | for (irq = 0; irq < 3; irq++) { |
| 350 | sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); |
| 351 | } |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) |
| 356 | { |
| 357 | static const struct UnimpInfo { |
| 358 | const char *name; |
| 359 | hwaddr base; |
| 360 | hwaddr size; |
| 361 | } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { |
| 362 | { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, |
| 363 | }; |
| 364 | unsigned int nr; |
| 365 | |
| 366 | for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { |
| 367 | const struct UnimpInfo *info = &unimp_areas[nr]; |
| 368 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); |
| 369 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 370 | |
| 371 | assert(info->name && info->base && info->size > 0); |
| 372 | qdev_prop_set_string(dev, "name", info->name); |
| 373 | qdev_prop_set_uint64(dev, "size", info->size); |
| 374 | object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); |
| 375 | |
| 376 | sysbus_realize_and_unref(sbd, &error_fatal); |
| 377 | sysbus_mmio_map(sbd, 0, info->base); |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static void xlnx_zynqmp_init(Object *obj) |
| 382 | { |
| 383 | XlnxZynqMPState *s = XLNX_ZYNQMP(obj); |
| 384 | int i; |
| 385 | |
| 386 | object_initialize_child(obj, "apu-cluster", &s->apu_cluster, |
| 387 | TYPE_CPU_CLUSTER); |
| 388 | qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); |
| 389 | |
| 390 | object_initialize_child(obj, "gic", &s->gic, gic_class_name()); |
| 391 | |
| 392 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { |
| 393 | object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); |
| 394 | object_initialize_child(obj, "gem-irq-orgate[*]", |
| 395 | &s->gem_irq_orgate[i], TYPE_OR_IRQ); |
| 396 | } |
| 397 | |
| 398 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { |
| 399 | object_initialize_child(obj, "uart[*]", &s->uart[i], |
| 400 | TYPE_CADENCE_UART); |
| 401 | } |
| 402 | |
| 403 | for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { |
| 404 | object_initialize_child(obj, "can[*]", &s->can[i], |
| 405 | TYPE_XLNX_ZYNQMP_CAN); |
| 406 | } |
| 407 | |
| 408 | object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); |
| 409 | |
| 410 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { |
| 411 | object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], |
| 412 | TYPE_SYSBUS_SDHCI); |
| 413 | } |
| 414 | |
| 415 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { |
| 416 | object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); |
| 417 | } |
| 418 | |
| 419 | object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); |
| 420 | |
| 421 | object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); |
| 422 | |
| 423 | object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); |
| 424 | |
| 425 | object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); |
| 426 | |
| 427 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); |
| 428 | |
| 429 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
| 430 | object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); |
| 431 | } |
| 432 | |
| 433 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { |
| 434 | object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); |
| 435 | } |
| 436 | |
| 437 | object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); |
| 438 | object_initialize_child(obj, "qspi-irq-orgate", |
| 439 | &s->qspi_irq_orgate, TYPE_OR_IRQ); |
| 440 | |
| 441 | for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { |
| 442 | object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) |
| 447 | { |
| 448 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 449 | XlnxZynqMPState *s = XLNX_ZYNQMP(dev); |
| 450 | MemoryRegion *system_memory = get_system_memory(); |
| 451 | uint8_t i; |
| 452 | uint64_t ram_size; |
| 453 | int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); |
| 454 | int num_rpus = xlnx_zynqmp_get_rpu_number(ms); |
| 455 | const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; |
| 456 | ram_addr_t ddr_low_size, ddr_high_size; |
| 457 | qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; |
| 458 | Error *err = NULL; |
| 459 | |
| 460 | ram_size = memory_region_size(s->ddr_ram); |
| 461 | |
| 462 | for (i = 0; i < num_apus; i++) { |
| 463 | object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", |
| 464 | &s->apu_cpu[i], |
| 465 | ARM_CPU_TYPE_NAME("cortex-a53")); |
| 466 | } |
| 467 | |
| 468 | if (num_rpus) { |
| 469 | /* Do not create the rpu_gic if we don't have rpus */ |
| 470 | object_initialize_child(OBJECT(dev), "rpu_gic", &s->rpu_gic, |
| 471 | gic_class_name()); |
| 472 | |
| 473 | for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { |
| 474 | g_autofree char *name = g_strdup_printf("irq-splitter%d", i); |
| 475 | object_initialize_child(OBJECT(dev), name, &s->splitter[i], TYPE_SPLIT_IRQ); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | |
| 480 | /* |
| 481 | * Create the DDR Memory Regions. User friendly checks should happen at |
| 482 | * the board level |
| 483 | */ |
| 484 | if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { |
| 485 | /* |
| 486 | * The RAM size is above the maximum available for the low DDR. |
| 487 | * Create the high DDR memory region as well. |
| 488 | */ |
| 489 | assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); |
| 490 | ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; |
| 491 | ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; |
| 492 | |
| 493 | memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), |
| 494 | "ddr-ram-high", s->ddr_ram, ddr_low_size, |
| 495 | ddr_high_size); |
| 496 | memory_region_add_subregion(get_system_memory(), |
| 497 | XLNX_ZYNQMP_HIGH_RAM_START, |
| 498 | &s->ddr_ram_high); |
| 499 | } else { |
| 500 | /* RAM must be non-zero */ |
| 501 | assert(ram_size); |
| 502 | ddr_low_size = ram_size; |
| 503 | } |
| 504 | |
| 505 | memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", |
| 506 | s->ddr_ram, 0, ddr_low_size); |
| 507 | memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); |
| 508 | |
| 509 | /* Create the four OCM banks */ |
| 510 | for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { |
| 511 | char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); |
| 512 | |
| 513 | memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, |
| 514 | XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); |
| 515 | memory_region_add_subregion(get_system_memory(), |
| 516 | XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + |
| 517 | i * XLNX_ZYNQMP_OCM_RAM_SIZE, |
| 518 | &s->ocm_ram[i]); |
| 519 | |
| 520 | g_free(ocm_name); |
| 521 | } |
| 522 | |
| 523 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", |
| 524 | XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); |
| 525 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); |
| 526 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); |
| 527 | qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); |
| 528 | qdev_prop_set_bit(DEVICE(&s->gic), |
| 529 | "has-virtualization-extensions", s->virt); |
| 530 | |
| 531 | if (num_rpus) { |
| 532 | qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq", |
| 533 | XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); |
| 534 | qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1); |
| 535 | qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus); |
| 536 | qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4); |
| 537 | } |
| 538 | |
| 539 | qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); |
| 540 | |
| 541 | /* Realize APUs before realizing the GIC. KVM requires this. */ |
| 542 | for (i = 0; i < num_apus; i++) { |
| 543 | const char *name; |
| 544 | |
| 545 | name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); |
| 546 | if (strcmp(name, boot_cpu)) { |
| 547 | /* |
| 548 | * Secondary CPUs start in powered-down state. |
| 549 | */ |
| 550 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), |
| 551 | "start-powered-off", true, &error_abort); |
| 552 | } else { |
| 553 | s->boot_cpu_ptr = &s->apu_cpu[i]; |
| 554 | } |
| 555 | |
| 556 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, |
| 557 | NULL); |
| 558 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, |
| 559 | NULL); |
| 560 | object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", |
| 561 | GIC_BASE_ADDR, &error_abort); |
| 562 | object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", |
| 563 | num_apus, &error_abort); |
| 564 | if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { |
| 565 | return; |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
| 570 | return; |
| 571 | } |
| 572 | |
| 573 | assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); |
| 574 | for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { |
| 575 | SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); |
| 576 | const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; |
| 577 | MemoryRegion *mr; |
| 578 | uint32_t addr = r->address; |
| 579 | int j; |
| 580 | |
| 581 | if (r->virt && !s->virt) { |
| 582 | continue; |
| 583 | } |
| 584 | |
| 585 | mr = sysbus_mmio_get_region(gic, r->region_index); |
| 586 | for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { |
| 587 | MemoryRegion *alias = &s->gic_mr[i][j]; |
| 588 | |
| 589 | memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, |
| 590 | r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); |
| 591 | memory_region_add_subregion(system_memory, addr, alias); |
| 592 | |
| 593 | addr += XLNX_ZYNQMP_GIC_REGION_SIZE; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | for (i = 0; i < num_apus; i++) { |
| 598 | qemu_irq irq; |
| 599 | |
| 600 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, |
| 601 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), |
| 602 | ARM_CPU_IRQ)); |
| 603 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, |
| 604 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), |
| 605 | ARM_CPU_FIQ)); |
| 606 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, |
| 607 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), |
| 608 | ARM_CPU_VIRQ)); |
| 609 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, |
| 610 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), |
| 611 | ARM_CPU_VFIQ)); |
| 612 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
| 613 | arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); |
| 614 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); |
| 615 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
| 616 | arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); |
| 617 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); |
| 618 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
| 619 | arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); |
| 620 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); |
| 621 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
| 622 | arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); |
| 623 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); |
| 624 | |
| 625 | if (s->virt) { |
| 626 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
| 627 | arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); |
| 628 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); |
| 633 | if (err) { |
| 634 | error_propagate(errp, err); |
| 635 | return; |
| 636 | } |
| 637 | |
| 638 | if (num_rpus) { |
| 639 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) { |
| 640 | return; |
| 641 | } |
| 642 | |
| 643 | for (i = 0; i < num_rpus; i++) { |
| 644 | qemu_irq irq; |
| 645 | |
| 646 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1, |
| 647 | GIC_BASE_ADDR + i * 0x1000); |
| 648 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i, |
| 649 | qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), |
| 650 | ARM_CPU_IRQ)); |
| 651 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus, |
| 652 | qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), |
| 653 | ARM_CPU_FIQ)); |
| 654 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 2, |
| 655 | qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), |
| 656 | ARM_CPU_VIRQ)); |
| 657 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 3, |
| 658 | qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), |
| 659 | ARM_CPU_VFIQ)); |
| 660 | irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), |
| 661 | arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); |
| 662 | qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq); |
| 663 | irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), |
| 664 | arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); |
| 665 | qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq); |
| 666 | irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), |
| 667 | arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); |
| 668 | qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq); |
| 669 | irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), |
| 670 | arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); |
| 671 | qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq); |
| 672 | } |
| 673 | |
| 674 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR); |
| 675 | } |
| 676 | |
| 677 | if (!s->boot_cpu_ptr) { |
| 678 | error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); |
| 679 | return; |
| 680 | } |
| 681 | |
| 682 | for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) { |
| 683 | if (num_rpus) { |
| 684 | DeviceState *splitter = DEVICE(&s->splitter[i]); |
| 685 | qdev_prop_set_uint16(splitter, "num-lines", 2); |
| 686 | qdev_realize(splitter, NULL, &error_abort); |
| 687 | gic_spi[i] = qdev_get_gpio_in(splitter, 0); |
| 688 | qdev_connect_gpio_out(splitter, 0, |
| 689 | qdev_get_gpio_in(DEVICE(&s->gic), i)); |
| 690 | qdev_connect_gpio_out(splitter, 1, |
| 691 | qdev_get_gpio_in(DEVICE(&s->rpu_gic), i)); |
| 692 | } else { |
| 693 | gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); |
| 694 | } |
| 695 | } |
| 696 | |
| 697 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { |
| 698 | qemu_configure_nic_device(DEVICE(&s->gem[i]), true, NULL); |
| 699 | object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, |
| 700 | &error_abort); |
| 701 | object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, |
| 702 | &error_abort); |
| 703 | object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, |
| 704 | &error_abort); |
| 705 | object_property_set_int(OBJECT(&s->gem_irq_orgate[i]), |
| 706 | "num-lines", 2, &error_fatal); |
| 707 | qdev_realize(DEVICE(&s->gem_irq_orgate[i]), NULL, &error_fatal); |
| 708 | qdev_connect_gpio_out(DEVICE(&s->gem_irq_orgate[i]), 0, gic_spi[gem_intr[i]]); |
| 709 | |
| 710 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { |
| 711 | return; |
| 712 | } |
| 713 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); |
| 714 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, |
| 715 | qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 0)); |
| 716 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, |
| 717 | qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 1)); |
| 718 | } |
| 719 | |
| 720 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { |
| 721 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
| 722 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { |
| 723 | return; |
| 724 | } |
| 725 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); |
| 726 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 727 | gic_spi[uart_intr[i]]); |
| 728 | } |
| 729 | |
| 730 | for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { |
| 731 | object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", |
| 732 | XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); |
| 733 | |
| 734 | object_property_set_link(OBJECT(&s->can[i]), "canbus", |
| 735 | OBJECT(s->canbus[i]), &error_fatal); |
| 736 | |
| 737 | sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); |
| 738 | if (err) { |
| 739 | error_propagate(errp, err); |
| 740 | return; |
| 741 | } |
| 742 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); |
| 743 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, |
| 744 | gic_spi[can_intr[i]]); |
| 745 | } |
| 746 | |
| 747 | object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, |
| 748 | &error_abort); |
| 749 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { |
| 750 | return; |
| 751 | } |
| 752 | |
| 753 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); |
| 754 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); |
| 755 | |
| 756 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { |
| 757 | char *bus_name; |
| 758 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); |
| 759 | Object *sdhci = OBJECT(&s->sdhci[i]); |
| 760 | |
| 761 | /* |
| 762 | * Compatible with: |
| 763 | * - SD Host Controller Specification Version 3.00 |
| 764 | * - SDIO Specification Version 3.0 |
| 765 | * - eMMC Specification Version 4.51 |
| 766 | */ |
| 767 | object_property_set_uint(sdhci, "sd-spec-version", 3, &error_abort); |
| 768 | object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, |
| 769 | &error_abort); |
| 770 | object_property_set_uint(sdhci, "uhs", UHS_I, &error_abort); |
| 771 | if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { |
| 772 | return; |
| 773 | } |
| 774 | sysbus_mmio_map(sbd, 0, sdhci_addr[i]); |
| 775 | sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); |
| 776 | |
| 777 | /* Alias controller SD bus to the SoC itself */ |
| 778 | bus_name = g_strdup_printf("sd-bus%d", i); |
| 779 | object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); |
| 780 | g_free(bus_name); |
| 781 | } |
| 782 | |
| 783 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { |
| 784 | gchar *bus_name; |
| 785 | |
| 786 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
| 787 | return; |
| 788 | } |
| 789 | |
| 790 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); |
| 791 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 792 | gic_spi[spi_intr[i]]); |
| 793 | |
| 794 | /* Alias controller SPI bus to the SoC itself */ |
| 795 | bus_name = g_strdup_printf("spi%d", i); |
| 796 | object_property_add_alias(OBJECT(s), bus_name, |
| 797 | OBJECT(&s->spi[i]), "spi0"); |
| 798 | g_free(bus_name); |
| 799 | } |
| 800 | |
| 801 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { |
| 802 | return; |
| 803 | } |
| 804 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); |
| 805 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); |
| 806 | |
| 807 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { |
| 808 | return; |
| 809 | } |
| 810 | object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), |
| 811 | &error_abort); |
| 812 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); |
| 813 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); |
| 814 | |
| 815 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { |
| 816 | return; |
| 817 | } |
| 818 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); |
| 819 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); |
| 820 | |
| 821 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
| 822 | return; |
| 823 | } |
| 824 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); |
| 825 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); |
| 826 | |
| 827 | xlnx_zynqmp_create_bbram(s, gic_spi); |
| 828 | xlnx_zynqmp_create_efuse(s, gic_spi); |
| 829 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); |
| 830 | xlnx_zynqmp_create_crf(s, gic_spi); |
| 831 | xlnx_zynqmp_create_ttc(s, gic_spi); |
| 832 | xlnx_zynqmp_create_unimp_mmio(s); |
| 833 | |
| 834 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
| 835 | object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, |
| 836 | &error_abort); |
| 837 | object_property_set_link(OBJECT(&s->gdma[i]), "dma", |
| 838 | OBJECT(system_memory), &error_abort); |
| 839 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { |
| 840 | return; |
| 841 | } |
| 842 | |
| 843 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); |
| 844 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, |
| 845 | gic_spi[gdma_ch_intr[i]]); |
| 846 | } |
| 847 | |
| 848 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { |
| 849 | if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", |
| 850 | OBJECT(system_memory), errp)) { |
| 851 | return; |
| 852 | } |
| 853 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { |
| 854 | return; |
| 855 | } |
| 856 | |
| 857 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); |
| 858 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, |
| 859 | gic_spi[adma_ch_intr[i]]); |
| 860 | } |
| 861 | |
| 862 | object_property_set_int(OBJECT(&s->qspi_irq_orgate), |
| 863 | "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal); |
| 864 | qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal); |
| 865 | qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]); |
| 866 | |
| 867 | if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", |
| 868 | OBJECT(system_memory), errp)) { |
| 869 | return; |
| 870 | } |
| 871 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { |
| 872 | return; |
| 873 | } |
| 874 | |
| 875 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); |
| 876 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, |
| 877 | qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); |
| 878 | |
| 879 | object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", |
| 880 | OBJECT(&s->qspi_dma), &error_abort); |
| 881 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { |
| 882 | return; |
| 883 | } |
| 884 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); |
| 885 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); |
| 886 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, |
| 887 | qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1)); |
| 888 | |
| 889 | for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { |
| 890 | g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); |
| 891 | g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); |
| 892 | |
| 893 | /* Alias controller SPI bus to the SoC itself */ |
| 894 | object_property_add_alias(OBJECT(s), bus_name, |
| 895 | OBJECT(&s->qspi), target_bus); |
| 896 | } |
| 897 | |
| 898 | for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { |
| 899 | object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", |
| 900 | OBJECT(system_memory), &error_abort); |
| 901 | |
| 902 | qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4); |
| 903 | qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); |
| 904 | |
| 905 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) { |
| 906 | return; |
| 907 | } |
| 908 | |
| 909 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]); |
| 910 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0, |
| 911 | gic_spi[usb_intr[i]]); |
| 912 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1, |
| 913 | gic_spi[usb_intr[i] + 1]); |
| 914 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2, |
| 915 | gic_spi[usb_intr[i] + 2]); |
| 916 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3, |
| 917 | gic_spi[usb_intr[i] + 3]); |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | static const Property xlnx_zynqmp_props[] = { |
| 922 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), |
| 923 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), |
| 924 | DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), |
| 925 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, |
| 926 | MemoryRegion *), |
| 927 | DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, |
| 928 | CanBusState *), |
| 929 | DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, |
| 930 | CanBusState *), |
| 931 | }; |
| 932 | |
| 933 | static void xlnx_zynqmp_class_init(ObjectClass *oc, const void *data) |
| 934 | { |
| 935 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 936 | |
| 937 | device_class_set_props(dc, xlnx_zynqmp_props); |
| 938 | dc->realize = xlnx_zynqmp_realize; |
| 939 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
| 940 | dc->user_creatable = false; |
| 941 | } |
| 942 | |
| 943 | static const TypeInfo xlnx_zynqmp_type_info = { |
| 944 | .name = TYPE_XLNX_ZYNQMP, |
| 945 | .parent = TYPE_DEVICE, |
| 946 | .instance_size = sizeof(XlnxZynqMPState), |
| 947 | .instance_init = xlnx_zynqmp_init, |
| 948 | .class_init = xlnx_zynqmp_class_init, |
| 949 | }; |
| 950 | |
| 951 | static void xlnx_zynqmp_register_types(void) |
| 952 | { |
| 953 | type_register_static(&xlnx_zynqmp_type_info); |
| 954 | } |
| 955 | |
| 956 | type_init(xlnx_zynqmp_register_types) |