| 1 | /* |
| 2 | * Copyright (C) 2006 InnoTek Systemberatung GmbH |
| 3 | * |
| 4 | * This file is part of VirtualBox Open Source Edition (OSE), as |
| 5 | * available from http://www.virtualbox.org. This file is free software; |
| 6 | * you can redistribute it and/or modify it under the terms of the GNU |
| 7 | * General Public License as published by the Free Software Foundation, |
| 8 | * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE |
| 9 | * distribution. VirtualBox OSE is distributed in the hope that it will |
| 10 | * be useful, but WITHOUT ANY WARRANTY of any kind. |
| 11 | * |
| 12 | * If you received this file as part of a commercial VirtualBox |
| 13 | * distribution, then only the terms of your commercial VirtualBox |
| 14 | * license agreement apply instead of the previous paragraph. |
| 15 | * |
| 16 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 17 | * GNU GPL, version 2 or (at your option) any later version. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "hw/audio/model.h" |
| 22 | #include "qemu/audio.h" |
| 23 | #include "hw/pci/pci_device.h" |
| 24 | #include "hw/core/qdev-properties.h" |
| 25 | #include "migration/vmstate.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "system/dma.h" |
| 28 | #include "qom/object.h" |
| 29 | #include "qemu/error-report.h" |
| 30 | #include "ac97.h" |
| 31 | |
| 32 | #define SOFT_VOLUME |
| 33 | #define SR_FIFOE 16 /* rwc */ |
| 34 | #define SR_BCIS 8 /* rwc */ |
| 35 | #define SR_LVBCI 4 /* rwc */ |
| 36 | #define SR_CELV 2 /* ro */ |
| 37 | #define SR_DCH 1 /* ro */ |
| 38 | #define SR_VALID_MASK ((1 << 5) - 1) |
| 39 | #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) |
| 40 | #define SR_RO_MASK (SR_DCH | SR_CELV) |
| 41 | #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) |
| 42 | |
| 43 | #define CR_IOCE 16 /* rw */ |
| 44 | #define CR_FEIE 8 /* rw */ |
| 45 | #define CR_LVBIE 4 /* rw */ |
| 46 | #define CR_RR 2 /* rw */ |
| 47 | #define CR_RPBM 1 /* rw */ |
| 48 | #define CR_VALID_MASK ((1 << 5) - 1) |
| 49 | #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) |
| 50 | |
| 51 | #define GC_WR 4 /* rw */ |
| 52 | #define GC_CR 2 /* rw */ |
| 53 | #define GC_VALID_MASK ((1 << 6) - 1) |
| 54 | |
| 55 | #define GS_MD3 (1 << 17) /* rw */ |
| 56 | #define GS_AD3 (1 << 16) /* rw */ |
| 57 | #define GS_RCS (1 << 15) /* rwc */ |
| 58 | #define GS_B3S12 (1 << 14) /* ro */ |
| 59 | #define GS_B2S12 (1 << 13) /* ro */ |
| 60 | #define GS_B1S12 (1 << 12) /* ro */ |
| 61 | #define GS_S1R1 (1 << 11) /* rwc */ |
| 62 | #define GS_S0R1 (1 << 10) /* rwc */ |
| 63 | #define GS_S1CR (1 << 9) /* ro */ |
| 64 | #define GS_S0CR (1 << 8) /* ro */ |
| 65 | #define GS_MINT (1 << 7) /* ro */ |
| 66 | #define GS_POINT (1 << 6) /* ro */ |
| 67 | #define GS_PIINT (1 << 5) /* ro */ |
| 68 | #define GS_RSRVD ((1 << 4) | (1 << 3)) |
| 69 | #define GS_MOINT (1 << 2) /* ro */ |
| 70 | #define GS_MIINT (1 << 1) /* ro */ |
| 71 | #define GS_GSCI 1 /* rwc */ |
| 72 | #define GS_RO_MASK (GS_B3S12 | \ |
| 73 | GS_B2S12 | \ |
| 74 | GS_B1S12 | \ |
| 75 | GS_S1CR | \ |
| 76 | GS_S0CR | \ |
| 77 | GS_MINT | \ |
| 78 | GS_POINT | \ |
| 79 | GS_PIINT | \ |
| 80 | GS_RSRVD | \ |
| 81 | GS_MOINT | \ |
| 82 | GS_MIINT) |
| 83 | #define GS_VALID_MASK ((1 << 18) - 1) |
| 84 | #define GS_WCLEAR_MASK (GS_RCS | GS_S1R1 | GS_S0R1 | GS_GSCI) |
| 85 | |
| 86 | #define BD_IOC (1 << 31) |
| 87 | #define BD_BUP (1 << 30) |
| 88 | |
| 89 | #define TYPE_AC97 "AC97" |
| 90 | OBJECT_DECLARE_SIMPLE_TYPE(AC97LinkState, AC97) |
| 91 | |
| 92 | #define REC_MASK 7 |
| 93 | enum { |
| 94 | REC_MIC = 0, |
| 95 | REC_CD, |
| 96 | REC_VIDEO, |
| 97 | REC_AUX, |
| 98 | REC_LINE_IN, |
| 99 | REC_STEREO_MIX, |
| 100 | REC_MONO_MIX, |
| 101 | REC_PHONE |
| 102 | }; |
| 103 | |
| 104 | typedef struct BD { |
| 105 | uint32_t addr; |
| 106 | uint32_t ctl_len; |
| 107 | } BD; |
| 108 | |
| 109 | typedef struct AC97BusMasterRegs { |
| 110 | uint32_t bdbar; /* rw 0 */ |
| 111 | uint8_t civ; /* ro 0 */ |
| 112 | uint8_t lvi; /* rw 0 */ |
| 113 | uint16_t sr; /* rw 1 */ |
| 114 | uint16_t picb; /* ro 0 */ |
| 115 | uint8_t piv; /* ro 0 */ |
| 116 | uint8_t cr; /* rw 0 */ |
| 117 | unsigned int bd_valid; |
| 118 | BD bd; |
| 119 | } AC97BusMasterRegs; |
| 120 | |
| 121 | struct AC97LinkState { |
| 122 | PCIDevice dev; |
| 123 | AudioBackend *audio_be; |
| 124 | uint32_t glob_cnt; |
| 125 | uint32_t glob_sta; |
| 126 | uint32_t cas; |
| 127 | uint32_t last_samp; |
| 128 | AC97BusMasterRegs bm_regs[3]; |
| 129 | uint8_t mixer_data[256]; |
| 130 | SWVoiceIn *voice_pi; |
| 131 | SWVoiceOut *voice_po; |
| 132 | SWVoiceIn *voice_mc; |
| 133 | int invalid_freq[3]; |
| 134 | uint8_t silence[128]; |
| 135 | int bup_flag; |
| 136 | MemoryRegion io_nam; |
| 137 | MemoryRegion io_nabm; |
| 138 | }; |
| 139 | |
| 140 | enum { |
| 141 | BUP_SET = 1, |
| 142 | BUP_LAST = 2 |
| 143 | }; |
| 144 | |
| 145 | #define DEBUG_AC97 0 |
| 146 | #define dolog(fmt, ...) do { \ |
| 147 | if (DEBUG_AC97) { \ |
| 148 | error_report("ac97: " fmt, ##__VA_ARGS__); \ |
| 149 | } \ |
| 150 | } while (0) |
| 151 | |
| 152 | #define MKREGS(prefix, start) \ |
| 153 | enum { \ |
| 154 | prefix ## _BDBAR = start, \ |
| 155 | prefix ## _CIV = start + 4, \ |
| 156 | prefix ## _LVI = start + 5, \ |
| 157 | prefix ## _SR = start + 6, \ |
| 158 | prefix ## _PICB = start + 8, \ |
| 159 | prefix ## _PIV = start + 10, \ |
| 160 | prefix ## _CR = start + 11 \ |
| 161 | } |
| 162 | |
| 163 | enum { |
| 164 | PI_INDEX = 0, |
| 165 | PO_INDEX, |
| 166 | MC_INDEX, |
| 167 | LAST_INDEX |
| 168 | }; |
| 169 | |
| 170 | MKREGS(PI, PI_INDEX * 16); |
| 171 | MKREGS(PO, PO_INDEX * 16); |
| 172 | MKREGS(MC, MC_INDEX * 16); |
| 173 | |
| 174 | enum { |
| 175 | GLOB_CNT = 0x2c, |
| 176 | GLOB_STA = 0x30, |
| 177 | CAS = 0x34 |
| 178 | }; |
| 179 | |
| 180 | #define GET_BM(index) (((index) >> 4) & 3) |
| 181 | |
| 182 | static void po_callback(void *opaque, int free); |
| 183 | static void pi_callback(void *opaque, int avail); |
| 184 | static void mc_callback(void *opaque, int avail); |
| 185 | |
| 186 | static void fetch_bd(AC97LinkState *s, AC97BusMasterRegs *r) |
| 187 | { |
| 188 | uint8_t b[8]; |
| 189 | |
| 190 | pci_dma_read(&s->dev, r->bdbar + r->civ * 8, b, 8); |
| 191 | r->bd_valid = 1; |
| 192 | r->bd.addr = le32_to_cpu(*(uint32_t *) &b[0]) & ~3; |
| 193 | r->bd.ctl_len = le32_to_cpu(*(uint32_t *) &b[4]); |
| 194 | r->picb = r->bd.ctl_len & 0xffff; |
| 195 | dolog("bd %2d addr=0x%x ctl=0x%06x len=0x%x(%d bytes)", |
| 196 | r->civ, r->bd.addr, r->bd.ctl_len >> 16, |
| 197 | r->bd.ctl_len & 0xffff, (r->bd.ctl_len & 0xffff) << 1); |
| 198 | } |
| 199 | |
| 200 | static void update_sr(AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) |
| 201 | { |
| 202 | int event = 0; |
| 203 | int level = 0; |
| 204 | uint32_t new_mask = new_sr & SR_INT_MASK; |
| 205 | uint32_t old_mask = r->sr & SR_INT_MASK; |
| 206 | uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; |
| 207 | |
| 208 | if (new_mask ^ old_mask) { |
| 209 | /** @todo is IRQ deasserted when only one of status bits is cleared? */ |
| 210 | if (!new_mask) { |
| 211 | event = 1; |
| 212 | level = 0; |
| 213 | } else { |
| 214 | if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) { |
| 215 | event = 1; |
| 216 | level = 1; |
| 217 | } |
| 218 | if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { |
| 219 | event = 1; |
| 220 | level = 1; |
| 221 | } |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | r->sr = new_sr; |
| 226 | |
| 227 | dolog("IOC%d LVB%d sr=0x%x event=%d level=%d", |
| 228 | r->sr & SR_BCIS, r->sr & SR_LVBCI, r->sr, event, level); |
| 229 | |
| 230 | if (!event) { |
| 231 | return; |
| 232 | } |
| 233 | |
| 234 | if (level) { |
| 235 | s->glob_sta |= masks[r - s->bm_regs]; |
| 236 | dolog("set irq level=1"); |
| 237 | pci_irq_assert(&s->dev); |
| 238 | } else { |
| 239 | s->glob_sta &= ~masks[r - s->bm_regs]; |
| 240 | dolog("set irq level=0"); |
| 241 | pci_irq_deassert(&s->dev); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | static void voice_set_active(AC97LinkState *s, int bm_index, int on) |
| 246 | { |
| 247 | switch (bm_index) { |
| 248 | case PI_INDEX: |
| 249 | audio_be_set_active_in(s->audio_be, s->voice_pi, on); |
| 250 | break; |
| 251 | |
| 252 | case PO_INDEX: |
| 253 | audio_be_set_active_out(s->audio_be, s->voice_po, on); |
| 254 | break; |
| 255 | |
| 256 | case MC_INDEX: |
| 257 | audio_be_set_active_in(s->audio_be, s->voice_mc, on); |
| 258 | break; |
| 259 | |
| 260 | default: |
| 261 | error_report("ac97: invalid bm_index(%d) in voice_set_active", bm_index); |
| 262 | break; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | static void reset_bm_regs(AC97LinkState *s, AC97BusMasterRegs *r) |
| 267 | { |
| 268 | dolog("reset_bm_regs"); |
| 269 | r->bdbar = 0; |
| 270 | r->civ = 0; |
| 271 | r->lvi = 0; |
| 272 | /** todo do we need to do that? */ |
| 273 | update_sr(s, r, SR_DCH); |
| 274 | r->picb = 0; |
| 275 | r->piv = 0; |
| 276 | r->cr = r->cr & CR_DONT_CLEAR_MASK; |
| 277 | r->bd_valid = 0; |
| 278 | |
| 279 | voice_set_active(s, r - s->bm_regs, 0); |
| 280 | memset(s->silence, 0, sizeof(s->silence)); |
| 281 | } |
| 282 | |
| 283 | static void mixer_store(AC97LinkState *s, uint32_t i, uint16_t v) |
| 284 | { |
| 285 | if (i + 2 > sizeof(s->mixer_data)) { |
| 286 | dolog("mixer_store: index %d out of bounds %zd", |
| 287 | i, sizeof(s->mixer_data)); |
| 288 | return; |
| 289 | } |
| 290 | |
| 291 | s->mixer_data[i + 0] = v & 0xff; |
| 292 | s->mixer_data[i + 1] = v >> 8; |
| 293 | } |
| 294 | |
| 295 | static uint16_t mixer_load(AC97LinkState *s, uint32_t i) |
| 296 | { |
| 297 | uint16_t val = 0xffff; |
| 298 | |
| 299 | if (i + 2 > sizeof(s->mixer_data)) { |
| 300 | dolog("mixer_load: index %d out of bounds %zd", |
| 301 | i, sizeof(s->mixer_data)); |
| 302 | } else { |
| 303 | val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); |
| 304 | } |
| 305 | |
| 306 | return val; |
| 307 | } |
| 308 | |
| 309 | static void open_voice(AC97LinkState *s, int index, int freq) |
| 310 | { |
| 311 | struct audsettings as; |
| 312 | |
| 313 | as.freq = freq; |
| 314 | as.nchannels = 2; |
| 315 | as.fmt = AUDIO_FORMAT_S16; |
| 316 | as.big_endian = false; |
| 317 | |
| 318 | if (freq > 0) { |
| 319 | s->invalid_freq[index] = 0; |
| 320 | switch (index) { |
| 321 | case PI_INDEX: |
| 322 | s->voice_pi = audio_be_open_in( |
| 323 | s->audio_be, |
| 324 | s->voice_pi, |
| 325 | "ac97.pi", |
| 326 | s, |
| 327 | pi_callback, |
| 328 | &as |
| 329 | ); |
| 330 | break; |
| 331 | |
| 332 | case PO_INDEX: |
| 333 | s->voice_po = audio_be_open_out( |
| 334 | s->audio_be, |
| 335 | s->voice_po, |
| 336 | "ac97.po", |
| 337 | s, |
| 338 | po_callback, |
| 339 | &as |
| 340 | ); |
| 341 | break; |
| 342 | |
| 343 | case MC_INDEX: |
| 344 | s->voice_mc = audio_be_open_in( |
| 345 | s->audio_be, |
| 346 | s->voice_mc, |
| 347 | "ac97.mc", |
| 348 | s, |
| 349 | mc_callback, |
| 350 | &as |
| 351 | ); |
| 352 | break; |
| 353 | } |
| 354 | } else { |
| 355 | s->invalid_freq[index] = freq; |
| 356 | switch (index) { |
| 357 | case PI_INDEX: |
| 358 | audio_be_close_in(s->audio_be, s->voice_pi); |
| 359 | s->voice_pi = NULL; |
| 360 | break; |
| 361 | |
| 362 | case PO_INDEX: |
| 363 | audio_be_close_out(s->audio_be, s->voice_po); |
| 364 | s->voice_po = NULL; |
| 365 | break; |
| 366 | |
| 367 | case MC_INDEX: |
| 368 | audio_be_close_in(s->audio_be, s->voice_mc); |
| 369 | s->voice_mc = NULL; |
| 370 | break; |
| 371 | } |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | static void reset_voices(AC97LinkState *s, uint8_t active[LAST_INDEX]) |
| 376 | { |
| 377 | uint16_t freq; |
| 378 | |
| 379 | freq = mixer_load(s, AC97_PCM_LR_ADC_Rate); |
| 380 | open_voice(s, PI_INDEX, freq); |
| 381 | audio_be_set_active_in(s->audio_be, s->voice_pi, active[PI_INDEX]); |
| 382 | |
| 383 | freq = mixer_load(s, AC97_PCM_Front_DAC_Rate); |
| 384 | open_voice(s, PO_INDEX, freq); |
| 385 | audio_be_set_active_out(s->audio_be, s->voice_po, active[PO_INDEX]); |
| 386 | |
| 387 | freq = mixer_load(s, AC97_MIC_ADC_Rate); |
| 388 | open_voice(s, MC_INDEX, freq); |
| 389 | audio_be_set_active_in(s->audio_be, s->voice_mc, active[MC_INDEX]); |
| 390 | } |
| 391 | |
| 392 | static void get_volume(uint16_t vol, uint16_t mask, int inverse, |
| 393 | int *mute, uint8_t *lvol, uint8_t *rvol) |
| 394 | { |
| 395 | *mute = (vol >> MUTE_SHIFT) & 1; |
| 396 | *rvol = (255 * (vol & mask)) / mask; |
| 397 | *lvol = (255 * ((vol >> 8) & mask)) / mask; |
| 398 | |
| 399 | if (inverse) { |
| 400 | *rvol = 255 - *rvol; |
| 401 | *lvol = 255 - *lvol; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | static void update_combined_volume_out(AC97LinkState *s) |
| 406 | { |
| 407 | uint8_t lvol, rvol, plvol, prvol; |
| 408 | int mute, pmute; |
| 409 | |
| 410 | get_volume(mixer_load(s, AC97_Master_Volume_Mute), 0x3f, 1, |
| 411 | &mute, &lvol, &rvol); |
| 412 | get_volume(mixer_load(s, AC97_PCM_Out_Volume_Mute), 0x1f, 1, |
| 413 | &pmute, &plvol, &prvol); |
| 414 | |
| 415 | mute = mute | pmute; |
| 416 | lvol = (lvol * plvol) / 255; |
| 417 | rvol = (rvol * prvol) / 255; |
| 418 | |
| 419 | audio_be_set_volume_out_lr(s->audio_be, s->voice_po, mute, lvol, rvol); |
| 420 | } |
| 421 | |
| 422 | static void update_volume_in(AC97LinkState *s) |
| 423 | { |
| 424 | uint8_t lvol, rvol; |
| 425 | int mute; |
| 426 | |
| 427 | get_volume(mixer_load(s, AC97_Record_Gain_Mute), 0x0f, 0, |
| 428 | &mute, &lvol, &rvol); |
| 429 | |
| 430 | audio_be_set_volume_in_lr(s->audio_be, s->voice_pi, mute, lvol, rvol); |
| 431 | } |
| 432 | |
| 433 | static void set_volume(AC97LinkState *s, int index, uint32_t val) |
| 434 | { |
| 435 | switch (index) { |
| 436 | case AC97_Master_Volume_Mute: |
| 437 | val &= 0xbf3f; |
| 438 | mixer_store(s, index, val); |
| 439 | update_combined_volume_out(s); |
| 440 | break; |
| 441 | case AC97_PCM_Out_Volume_Mute: |
| 442 | val &= 0x9f1f; |
| 443 | mixer_store(s, index, val); |
| 444 | update_combined_volume_out(s); |
| 445 | break; |
| 446 | case AC97_Record_Gain_Mute: |
| 447 | val &= 0x8f0f; |
| 448 | mixer_store(s, index, val); |
| 449 | update_volume_in(s); |
| 450 | break; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | static void record_select(AC97LinkState *s, uint32_t val) |
| 455 | { |
| 456 | uint8_t rs = val & REC_MASK; |
| 457 | uint8_t ls = (val >> 8) & REC_MASK; |
| 458 | mixer_store(s, AC97_Record_Select, rs | (ls << 8)); |
| 459 | } |
| 460 | |
| 461 | static void mixer_reset(AC97LinkState *s) |
| 462 | { |
| 463 | uint8_t active[LAST_INDEX]; |
| 464 | |
| 465 | dolog("mixer_reset"); |
| 466 | memset(s->mixer_data, 0, sizeof(s->mixer_data)); |
| 467 | memset(active, 0, sizeof(active)); |
| 468 | mixer_store(s, AC97_Reset, 0x0000); /* 6940 */ |
| 469 | mixer_store(s, AC97_Headphone_Volume_Mute, 0x0000); |
| 470 | mixer_store(s, AC97_Master_Volume_Mono_Mute, 0x0000); |
| 471 | mixer_store(s, AC97_Master_Tone_RL, 0x0000); |
| 472 | mixer_store(s, AC97_PC_BEEP_Volume_Mute, 0x0000); |
| 473 | mixer_store(s, AC97_Phone_Volume_Mute, 0x0000); |
| 474 | mixer_store(s, AC97_Mic_Volume_Mute, 0x0000); |
| 475 | mixer_store(s, AC97_Line_In_Volume_Mute, 0x0000); |
| 476 | mixer_store(s, AC97_CD_Volume_Mute, 0x0000); |
| 477 | mixer_store(s, AC97_Video_Volume_Mute, 0x0000); |
| 478 | mixer_store(s, AC97_Aux_Volume_Mute, 0x0000); |
| 479 | mixer_store(s, AC97_Record_Gain_Mic_Mute, 0x0000); |
| 480 | mixer_store(s, AC97_General_Purpose, 0x0000); |
| 481 | mixer_store(s, AC97_3D_Control, 0x0000); |
| 482 | mixer_store(s, AC97_Powerdown_Ctrl_Stat, 0x000f); |
| 483 | |
| 484 | /* |
| 485 | * Sigmatel 9700 (STAC9700) |
| 486 | */ |
| 487 | mixer_store(s, AC97_Vendor_ID1, 0x8384); |
| 488 | mixer_store(s, AC97_Vendor_ID2, 0x7600); /* 7608 */ |
| 489 | |
| 490 | mixer_store(s, AC97_Extended_Audio_ID, 0x0809); |
| 491 | mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); |
| 492 | mixer_store(s, AC97_PCM_Front_DAC_Rate, 0xbb80); |
| 493 | mixer_store(s, AC97_PCM_Surround_DAC_Rate, 0xbb80); |
| 494 | mixer_store(s, AC97_PCM_LFE_DAC_Rate, 0xbb80); |
| 495 | mixer_store(s, AC97_PCM_LR_ADC_Rate, 0xbb80); |
| 496 | mixer_store(s, AC97_MIC_ADC_Rate, 0xbb80); |
| 497 | |
| 498 | record_select(s, 0); |
| 499 | set_volume(s, AC97_Master_Volume_Mute, 0x8000); |
| 500 | set_volume(s, AC97_PCM_Out_Volume_Mute, 0x8808); |
| 501 | set_volume(s, AC97_Record_Gain_Mute, 0x8808); |
| 502 | |
| 503 | reset_voices(s, active); |
| 504 | } |
| 505 | |
| 506 | /** |
| 507 | * Native audio mixer |
| 508 | * I/O Reads |
| 509 | */ |
| 510 | static uint32_t nam_readb(void *opaque, uint32_t addr) |
| 511 | { |
| 512 | AC97LinkState *s = opaque; |
| 513 | dolog("U nam readb 0x%x", addr); |
| 514 | s->cas = 0; |
| 515 | return ~0U; |
| 516 | } |
| 517 | |
| 518 | static uint32_t nam_readw(void *opaque, uint32_t addr) |
| 519 | { |
| 520 | AC97LinkState *s = opaque; |
| 521 | s->cas = 0; |
| 522 | return mixer_load(s, addr); |
| 523 | } |
| 524 | |
| 525 | static uint32_t nam_readl(void *opaque, uint32_t addr) |
| 526 | { |
| 527 | AC97LinkState *s = opaque; |
| 528 | dolog("U nam readl 0x%x", addr); |
| 529 | s->cas = 0; |
| 530 | return ~0U; |
| 531 | } |
| 532 | |
| 533 | /** |
| 534 | * Native audio mixer |
| 535 | * I/O Writes |
| 536 | */ |
| 537 | static void nam_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 538 | { |
| 539 | AC97LinkState *s = opaque; |
| 540 | dolog("U nam writeb 0x%x <- 0x%x", addr, val); |
| 541 | s->cas = 0; |
| 542 | } |
| 543 | |
| 544 | static void nam_writew(void *opaque, uint32_t addr, uint32_t val) |
| 545 | { |
| 546 | AC97LinkState *s = opaque; |
| 547 | |
| 548 | s->cas = 0; |
| 549 | switch (addr) { |
| 550 | case AC97_Reset: |
| 551 | mixer_reset(s); |
| 552 | break; |
| 553 | case AC97_Powerdown_Ctrl_Stat: |
| 554 | val &= ~0x800f; |
| 555 | val |= mixer_load(s, addr) & 0xf; |
| 556 | mixer_store(s, addr, val); |
| 557 | break; |
| 558 | case AC97_PCM_Out_Volume_Mute: |
| 559 | case AC97_Master_Volume_Mute: |
| 560 | case AC97_Record_Gain_Mute: |
| 561 | set_volume(s, addr, val); |
| 562 | break; |
| 563 | case AC97_Record_Select: |
| 564 | record_select(s, val); |
| 565 | break; |
| 566 | case AC97_Vendor_ID1: |
| 567 | case AC97_Vendor_ID2: |
| 568 | dolog("Attempt to write vendor ID to 0x%x", val); |
| 569 | break; |
| 570 | case AC97_Extended_Audio_ID: |
| 571 | dolog("Attempt to write extended audio ID to 0x%x", val); |
| 572 | break; |
| 573 | case AC97_Extended_Audio_Ctrl_Stat: |
| 574 | if (!(val & EACS_VRA)) { |
| 575 | mixer_store(s, AC97_PCM_Front_DAC_Rate, 0xbb80); |
| 576 | mixer_store(s, AC97_PCM_LR_ADC_Rate, 0xbb80); |
| 577 | open_voice(s, PI_INDEX, 48000); |
| 578 | open_voice(s, PO_INDEX, 48000); |
| 579 | } |
| 580 | if (!(val & EACS_VRM)) { |
| 581 | mixer_store(s, AC97_MIC_ADC_Rate, 0xbb80); |
| 582 | open_voice(s, MC_INDEX, 48000); |
| 583 | } |
| 584 | dolog("Setting extended audio control to 0x%x", val); |
| 585 | mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, val); |
| 586 | break; |
| 587 | case AC97_PCM_Front_DAC_Rate: |
| 588 | if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { |
| 589 | mixer_store(s, addr, val); |
| 590 | dolog("Set front DAC rate to %d", val); |
| 591 | open_voice(s, PO_INDEX, val); |
| 592 | } else { |
| 593 | dolog("Attempt to set front DAC rate to %d, but VRA is not set", |
| 594 | val); |
| 595 | } |
| 596 | break; |
| 597 | case AC97_MIC_ADC_Rate: |
| 598 | if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) { |
| 599 | mixer_store(s, addr, val); |
| 600 | dolog("Set MIC ADC rate to %d", val); |
| 601 | open_voice(s, MC_INDEX, val); |
| 602 | } else { |
| 603 | dolog("Attempt to set MIC ADC rate to %d, but VRM is not set", |
| 604 | val); |
| 605 | } |
| 606 | break; |
| 607 | case AC97_PCM_LR_ADC_Rate: |
| 608 | if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { |
| 609 | mixer_store(s, addr, val); |
| 610 | dolog("Set front LR ADC rate to %d", val); |
| 611 | open_voice(s, PI_INDEX, val); |
| 612 | } else { |
| 613 | dolog("Attempt to set LR ADC rate to %d, but VRA is not set", |
| 614 | val); |
| 615 | } |
| 616 | break; |
| 617 | case AC97_Headphone_Volume_Mute: |
| 618 | case AC97_Master_Volume_Mono_Mute: |
| 619 | case AC97_Master_Tone_RL: |
| 620 | case AC97_PC_BEEP_Volume_Mute: |
| 621 | case AC97_Phone_Volume_Mute: |
| 622 | case AC97_Mic_Volume_Mute: |
| 623 | case AC97_Line_In_Volume_Mute: |
| 624 | case AC97_CD_Volume_Mute: |
| 625 | case AC97_Video_Volume_Mute: |
| 626 | case AC97_Aux_Volume_Mute: |
| 627 | case AC97_Record_Gain_Mic_Mute: |
| 628 | case AC97_General_Purpose: |
| 629 | case AC97_3D_Control: |
| 630 | case AC97_Sigmatel_Analog: |
| 631 | case AC97_Sigmatel_Dac2Invert: |
| 632 | /* None of the features in these regs are emulated, so they are RO */ |
| 633 | break; |
| 634 | default: |
| 635 | dolog("U nam writew 0x%x <- 0x%x", addr, val); |
| 636 | mixer_store(s, addr, val); |
| 637 | break; |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | static void nam_writel(void *opaque, uint32_t addr, uint32_t val) |
| 642 | { |
| 643 | AC97LinkState *s = opaque; |
| 644 | dolog("U nam writel 0x%x <- 0x%x", addr, val); |
| 645 | s->cas = 0; |
| 646 | } |
| 647 | |
| 648 | /** |
| 649 | * Native audio bus master |
| 650 | * I/O Reads |
| 651 | */ |
| 652 | static uint32_t nabm_readb(void *opaque, uint32_t addr) |
| 653 | { |
| 654 | AC97LinkState *s = opaque; |
| 655 | AC97BusMasterRegs *r = NULL; |
| 656 | uint32_t val = ~0U; |
| 657 | |
| 658 | switch (addr) { |
| 659 | case CAS: |
| 660 | dolog("CAS %d", s->cas); |
| 661 | val = s->cas; |
| 662 | s->cas = 1; |
| 663 | break; |
| 664 | case PI_CIV: |
| 665 | case PO_CIV: |
| 666 | case MC_CIV: |
| 667 | r = &s->bm_regs[GET_BM(addr)]; |
| 668 | val = r->civ; |
| 669 | dolog("CIV[%d] -> 0x%x", GET_BM(addr), val); |
| 670 | break; |
| 671 | case PI_LVI: |
| 672 | case PO_LVI: |
| 673 | case MC_LVI: |
| 674 | r = &s->bm_regs[GET_BM(addr)]; |
| 675 | val = r->lvi; |
| 676 | dolog("LVI[%d] -> 0x%x", GET_BM(addr), val); |
| 677 | break; |
| 678 | case PI_PIV: |
| 679 | case PO_PIV: |
| 680 | case MC_PIV: |
| 681 | r = &s->bm_regs[GET_BM(addr)]; |
| 682 | val = r->piv; |
| 683 | dolog("PIV[%d] -> 0x%x", GET_BM(addr), val); |
| 684 | break; |
| 685 | case PI_CR: |
| 686 | case PO_CR: |
| 687 | case MC_CR: |
| 688 | r = &s->bm_regs[GET_BM(addr)]; |
| 689 | val = r->cr; |
| 690 | dolog("CR[%d] -> 0x%x", GET_BM(addr), val); |
| 691 | break; |
| 692 | case PI_SR: |
| 693 | case PO_SR: |
| 694 | case MC_SR: |
| 695 | r = &s->bm_regs[GET_BM(addr)]; |
| 696 | val = r->sr & 0xff; |
| 697 | dolog("SRb[%d] -> 0x%x", GET_BM(addr), val); |
| 698 | break; |
| 699 | default: |
| 700 | dolog("U nabm readb 0x%x -> 0x%x", addr, val); |
| 701 | break; |
| 702 | } |
| 703 | return val; |
| 704 | } |
| 705 | |
| 706 | static uint32_t nabm_readw(void *opaque, uint32_t addr) |
| 707 | { |
| 708 | AC97LinkState *s = opaque; |
| 709 | AC97BusMasterRegs *r = NULL; |
| 710 | uint32_t val = ~0U; |
| 711 | |
| 712 | switch (addr) { |
| 713 | case PI_SR: |
| 714 | case PO_SR: |
| 715 | case MC_SR: |
| 716 | r = &s->bm_regs[GET_BM(addr)]; |
| 717 | val = r->sr; |
| 718 | dolog("SR[%d] -> 0x%x", GET_BM(addr), val); |
| 719 | break; |
| 720 | case PI_PICB: |
| 721 | case PO_PICB: |
| 722 | case MC_PICB: |
| 723 | r = &s->bm_regs[GET_BM(addr)]; |
| 724 | val = r->picb; |
| 725 | dolog("PICB[%d] -> 0x%x", GET_BM(addr), val); |
| 726 | break; |
| 727 | default: |
| 728 | dolog("U nabm readw 0x%x -> 0x%x", addr, val); |
| 729 | break; |
| 730 | } |
| 731 | return val; |
| 732 | } |
| 733 | |
| 734 | static uint32_t nabm_readl(void *opaque, uint32_t addr) |
| 735 | { |
| 736 | AC97LinkState *s = opaque; |
| 737 | AC97BusMasterRegs *r = NULL; |
| 738 | uint32_t val = ~0U; |
| 739 | |
| 740 | switch (addr) { |
| 741 | case PI_BDBAR: |
| 742 | case PO_BDBAR: |
| 743 | case MC_BDBAR: |
| 744 | r = &s->bm_regs[GET_BM(addr)]; |
| 745 | val = r->bdbar; |
| 746 | dolog("BMADDR[%d] -> 0x%x", GET_BM(addr), val); |
| 747 | break; |
| 748 | case PI_CIV: |
| 749 | case PO_CIV: |
| 750 | case MC_CIV: |
| 751 | r = &s->bm_regs[GET_BM(addr)]; |
| 752 | val = r->civ | (r->lvi << 8) | (r->sr << 16); |
| 753 | dolog("CIV LVI SR[%d] -> 0x%x, 0x%x, 0x%x", GET_BM(addr), |
| 754 | r->civ, r->lvi, r->sr); |
| 755 | break; |
| 756 | case PI_PICB: |
| 757 | case PO_PICB: |
| 758 | case MC_PICB: |
| 759 | r = &s->bm_regs[GET_BM(addr)]; |
| 760 | val = r->picb | (r->piv << 16) | (r->cr << 24); |
| 761 | dolog("PICB PIV CR[%d] -> 0x%x 0x%x 0x%x 0x%x", GET_BM(addr), |
| 762 | val, r->picb, r->piv, r->cr); |
| 763 | break; |
| 764 | case GLOB_CNT: |
| 765 | val = s->glob_cnt; |
| 766 | dolog("glob_cnt -> 0x%x", val); |
| 767 | break; |
| 768 | case GLOB_STA: |
| 769 | val = s->glob_sta | GS_S0CR; |
| 770 | dolog("glob_sta -> 0x%x", val); |
| 771 | break; |
| 772 | default: |
| 773 | dolog("U nabm readl 0x%x -> 0x%x", addr, val); |
| 774 | break; |
| 775 | } |
| 776 | return val; |
| 777 | } |
| 778 | |
| 779 | /** |
| 780 | * Native audio bus master |
| 781 | * I/O Writes |
| 782 | */ |
| 783 | static void nabm_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 784 | { |
| 785 | AC97LinkState *s = opaque; |
| 786 | AC97BusMasterRegs *r = NULL; |
| 787 | |
| 788 | switch (addr) { |
| 789 | case PI_LVI: |
| 790 | case PO_LVI: |
| 791 | case MC_LVI: |
| 792 | r = &s->bm_regs[GET_BM(addr)]; |
| 793 | if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { |
| 794 | r->sr &= ~(SR_DCH | SR_CELV); |
| 795 | r->civ = r->piv; |
| 796 | r->piv = (r->piv + 1) % 32; |
| 797 | fetch_bd(s, r); |
| 798 | } |
| 799 | r->lvi = val % 32; |
| 800 | dolog("LVI[%d] <- 0x%x", GET_BM(addr), val); |
| 801 | break; |
| 802 | case PI_CR: |
| 803 | case PO_CR: |
| 804 | case MC_CR: |
| 805 | r = &s->bm_regs[GET_BM(addr)]; |
| 806 | if (val & CR_RR) { |
| 807 | reset_bm_regs(s, r); |
| 808 | } else { |
| 809 | r->cr = val & CR_VALID_MASK; |
| 810 | if (!(r->cr & CR_RPBM)) { |
| 811 | voice_set_active(s, r - s->bm_regs, 0); |
| 812 | r->sr |= SR_DCH; |
| 813 | } else { |
| 814 | r->civ = r->piv; |
| 815 | r->piv = (r->piv + 1) % 32; |
| 816 | fetch_bd(s, r); |
| 817 | r->sr &= ~SR_DCH; |
| 818 | voice_set_active(s, r - s->bm_regs, 1); |
| 819 | } |
| 820 | } |
| 821 | dolog("CR[%d] <- 0x%x (cr 0x%x)", GET_BM(addr), val, r->cr); |
| 822 | break; |
| 823 | case PI_SR: |
| 824 | case PO_SR: |
| 825 | case MC_SR: |
| 826 | r = &s->bm_regs[GET_BM(addr)]; |
| 827 | r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); |
| 828 | update_sr(s, r, r->sr & ~(val & SR_WCLEAR_MASK)); |
| 829 | dolog("SR[%d] <- 0x%x (sr 0x%x)", GET_BM(addr), val, r->sr); |
| 830 | break; |
| 831 | default: |
| 832 | dolog("U nabm writeb 0x%x <- 0x%x", addr, val); |
| 833 | break; |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | static void nabm_writew(void *opaque, uint32_t addr, uint32_t val) |
| 838 | { |
| 839 | AC97LinkState *s = opaque; |
| 840 | AC97BusMasterRegs *r = NULL; |
| 841 | |
| 842 | switch (addr) { |
| 843 | case PI_SR: |
| 844 | case PO_SR: |
| 845 | case MC_SR: |
| 846 | r = &s->bm_regs[GET_BM(addr)]; |
| 847 | r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); |
| 848 | update_sr(s, r, r->sr & ~(val & SR_WCLEAR_MASK)); |
| 849 | dolog("SR[%d] <- 0x%x (sr 0x%x)", GET_BM(addr), val, r->sr); |
| 850 | break; |
| 851 | default: |
| 852 | dolog("U nabm writew 0x%x <- 0x%x", addr, val); |
| 853 | break; |
| 854 | } |
| 855 | } |
| 856 | |
| 857 | static void nabm_writel(void *opaque, uint32_t addr, uint32_t val) |
| 858 | { |
| 859 | AC97LinkState *s = opaque; |
| 860 | AC97BusMasterRegs *r = NULL; |
| 861 | |
| 862 | switch (addr) { |
| 863 | case PI_BDBAR: |
| 864 | case PO_BDBAR: |
| 865 | case MC_BDBAR: |
| 866 | r = &s->bm_regs[GET_BM(addr)]; |
| 867 | r->bdbar = val & ~3; |
| 868 | dolog("BDBAR[%d] <- 0x%x (bdbar 0x%x)", GET_BM(addr), val, r->bdbar); |
| 869 | break; |
| 870 | case GLOB_CNT: |
| 871 | /* TODO: Handle WR or CR being set (warm/cold reset requests) */ |
| 872 | if (!(val & (GC_WR | GC_CR))) { |
| 873 | s->glob_cnt = val & GC_VALID_MASK; |
| 874 | } |
| 875 | dolog("glob_cnt <- 0x%x (glob_cnt 0x%x)", val, s->glob_cnt); |
| 876 | break; |
| 877 | case GLOB_STA: |
| 878 | s->glob_sta &= ~(val & GS_WCLEAR_MASK); |
| 879 | s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; |
| 880 | dolog("glob_sta <- 0x%x (glob_sta 0x%x)", val, s->glob_sta); |
| 881 | break; |
| 882 | default: |
| 883 | dolog("U nabm writel 0x%x <- 0x%x", addr, val); |
| 884 | break; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | static int write_audio(AC97LinkState *s, AC97BusMasterRegs *r, |
| 889 | int max, int *stop) |
| 890 | { |
| 891 | QEMU_UNINITIALIZED uint8_t tmpbuf[4096]; |
| 892 | uint32_t addr = r->bd.addr; |
| 893 | uint32_t temp = r->picb << 1; |
| 894 | uint32_t written = 0; |
| 895 | int to_copy = 0; |
| 896 | temp = MIN(temp, max); |
| 897 | |
| 898 | if (!temp) { |
| 899 | *stop = 1; |
| 900 | return 0; |
| 901 | } |
| 902 | |
| 903 | while (temp) { |
| 904 | int copied; |
| 905 | to_copy = MIN(temp, sizeof(tmpbuf)); |
| 906 | pci_dma_read(&s->dev, addr, tmpbuf, to_copy); |
| 907 | copied = audio_be_write(s->audio_be, s->voice_po, tmpbuf, to_copy); |
| 908 | dolog("write_audio max=%x to_copy=%x copied=%x", |
| 909 | max, to_copy, copied); |
| 910 | if (!copied) { |
| 911 | *stop = 1; |
| 912 | break; |
| 913 | } |
| 914 | temp -= copied; |
| 915 | addr += copied; |
| 916 | written += copied; |
| 917 | } |
| 918 | |
| 919 | if (!temp) { |
| 920 | if (to_copy < 4) { |
| 921 | dolog("whoops"); |
| 922 | s->last_samp = 0; |
| 923 | } else { |
| 924 | s->last_samp = *(uint32_t *)&tmpbuf[to_copy - 4]; |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | r->bd.addr = addr; |
| 929 | return written; |
| 930 | } |
| 931 | |
| 932 | static void write_bup(AC97LinkState *s, int elapsed) |
| 933 | { |
| 934 | dolog("write_bup"); |
| 935 | if (!(s->bup_flag & BUP_SET)) { |
| 936 | if (s->bup_flag & BUP_LAST) { |
| 937 | int i; |
| 938 | uint8_t *p = s->silence; |
| 939 | for (i = 0; i < sizeof(s->silence) / 4; i++, p += 4) { |
| 940 | *(uint32_t *) p = s->last_samp; |
| 941 | } |
| 942 | } else { |
| 943 | memset(s->silence, 0, sizeof(s->silence)); |
| 944 | } |
| 945 | s->bup_flag |= BUP_SET; |
| 946 | } |
| 947 | |
| 948 | while (elapsed) { |
| 949 | int temp = MIN(elapsed, sizeof(s->silence)); |
| 950 | while (temp) { |
| 951 | int copied = audio_be_write(s->audio_be, s->voice_po, s->silence, temp); |
| 952 | if (!copied) { |
| 953 | return; |
| 954 | } |
| 955 | temp -= copied; |
| 956 | elapsed -= copied; |
| 957 | } |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | static int read_audio(AC97LinkState *s, AC97BusMasterRegs *r, |
| 962 | int max, int *stop) |
| 963 | { |
| 964 | QEMU_UNINITIALIZED uint8_t tmpbuf[4096]; |
| 965 | uint32_t addr = r->bd.addr; |
| 966 | uint32_t temp = r->picb << 1; |
| 967 | uint32_t nread = 0; |
| 968 | int to_copy = 0; |
| 969 | SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; |
| 970 | |
| 971 | temp = MIN(temp, max); |
| 972 | |
| 973 | if (!temp) { |
| 974 | *stop = 1; |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | while (temp) { |
| 979 | int acquired; |
| 980 | to_copy = MIN(temp, sizeof(tmpbuf)); |
| 981 | acquired = audio_be_read(s->audio_be, voice, tmpbuf, to_copy); |
| 982 | if (!acquired) { |
| 983 | *stop = 1; |
| 984 | break; |
| 985 | } |
| 986 | pci_dma_write(&s->dev, addr, tmpbuf, acquired); |
| 987 | temp -= acquired; |
| 988 | addr += acquired; |
| 989 | nread += acquired; |
| 990 | } |
| 991 | |
| 992 | r->bd.addr = addr; |
| 993 | return nread; |
| 994 | } |
| 995 | |
| 996 | static void transfer_audio(AC97LinkState *s, int index, int elapsed) |
| 997 | { |
| 998 | AC97BusMasterRegs *r = &s->bm_regs[index]; |
| 999 | int stop = 0; |
| 1000 | |
| 1001 | if (s->invalid_freq[index]) { |
| 1002 | error_report("ac97: attempt to use voice %d with invalid frequency %d", |
| 1003 | index, s->invalid_freq[index]); |
| 1004 | return; |
| 1005 | } |
| 1006 | |
| 1007 | if (r->sr & SR_DCH) { |
| 1008 | if (r->cr & CR_RPBM) { |
| 1009 | switch (index) { |
| 1010 | case PO_INDEX: |
| 1011 | write_bup(s, elapsed); |
| 1012 | break; |
| 1013 | } |
| 1014 | } |
| 1015 | return; |
| 1016 | } |
| 1017 | |
| 1018 | while ((elapsed >> 1) && !stop) { |
| 1019 | int temp; |
| 1020 | |
| 1021 | if (!r->bd_valid) { |
| 1022 | dolog("invalid bd"); |
| 1023 | fetch_bd(s, r); |
| 1024 | } |
| 1025 | |
| 1026 | if (!r->picb) { |
| 1027 | dolog("fresh bd %d is empty 0x%x 0x%x", |
| 1028 | r->civ, r->bd.addr, r->bd.ctl_len); |
| 1029 | if (r->civ == r->lvi) { |
| 1030 | r->sr |= SR_DCH; /* CELV? */ |
| 1031 | s->bup_flag = 0; |
| 1032 | break; |
| 1033 | } |
| 1034 | r->sr &= ~SR_CELV; |
| 1035 | r->civ = r->piv; |
| 1036 | r->piv = (r->piv + 1) % 32; |
| 1037 | fetch_bd(s, r); |
| 1038 | return; |
| 1039 | } |
| 1040 | |
| 1041 | switch (index) { |
| 1042 | case PO_INDEX: |
| 1043 | temp = write_audio(s, r, elapsed, &stop); |
| 1044 | elapsed -= temp; |
| 1045 | r->picb -= (temp >> 1); |
| 1046 | break; |
| 1047 | |
| 1048 | case PI_INDEX: |
| 1049 | case MC_INDEX: |
| 1050 | temp = read_audio(s, r, elapsed, &stop); |
| 1051 | elapsed -= temp; |
| 1052 | r->picb -= (temp >> 1); |
| 1053 | break; |
| 1054 | } |
| 1055 | |
| 1056 | if (!r->picb) { |
| 1057 | uint32_t new_sr = r->sr & ~SR_CELV; |
| 1058 | |
| 1059 | if (r->bd.ctl_len & BD_IOC) { |
| 1060 | new_sr |= SR_BCIS; |
| 1061 | } |
| 1062 | |
| 1063 | if (r->civ == r->lvi) { |
| 1064 | dolog("Underrun civ (%d) == lvi (%d)", r->civ, r->lvi); |
| 1065 | |
| 1066 | new_sr |= SR_LVBCI | SR_DCH | SR_CELV; |
| 1067 | stop = 1; |
| 1068 | s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; |
| 1069 | } else { |
| 1070 | r->civ = r->piv; |
| 1071 | r->piv = (r->piv + 1) % 32; |
| 1072 | fetch_bd(s, r); |
| 1073 | } |
| 1074 | |
| 1075 | update_sr(s, r, new_sr); |
| 1076 | } |
| 1077 | } |
| 1078 | } |
| 1079 | |
| 1080 | static void pi_callback(void *opaque, int avail) |
| 1081 | { |
| 1082 | transfer_audio(opaque, PI_INDEX, avail); |
| 1083 | } |
| 1084 | |
| 1085 | static void mc_callback(void *opaque, int avail) |
| 1086 | { |
| 1087 | transfer_audio(opaque, MC_INDEX, avail); |
| 1088 | } |
| 1089 | |
| 1090 | static void po_callback(void *opaque, int free) |
| 1091 | { |
| 1092 | transfer_audio(opaque, PO_INDEX, free); |
| 1093 | } |
| 1094 | |
| 1095 | static const VMStateDescription vmstate_ac97_bm_regs = { |
| 1096 | .name = "ac97_bm_regs", |
| 1097 | .version_id = 1, |
| 1098 | .minimum_version_id = 1, |
| 1099 | .fields = (const VMStateField[]) { |
| 1100 | VMSTATE_UINT32(bdbar, AC97BusMasterRegs), |
| 1101 | VMSTATE_UINT8(civ, AC97BusMasterRegs), |
| 1102 | VMSTATE_UINT8(lvi, AC97BusMasterRegs), |
| 1103 | VMSTATE_UINT16(sr, AC97BusMasterRegs), |
| 1104 | VMSTATE_UINT16(picb, AC97BusMasterRegs), |
| 1105 | VMSTATE_UINT8(piv, AC97BusMasterRegs), |
| 1106 | VMSTATE_UINT8(cr, AC97BusMasterRegs), |
| 1107 | VMSTATE_UINT32(bd_valid, AC97BusMasterRegs), |
| 1108 | VMSTATE_UINT32(bd.addr, AC97BusMasterRegs), |
| 1109 | VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs), |
| 1110 | VMSTATE_END_OF_LIST() |
| 1111 | } |
| 1112 | }; |
| 1113 | |
| 1114 | static int ac97_post_load(void *opaque, int version_id) |
| 1115 | { |
| 1116 | uint8_t active[LAST_INDEX]; |
| 1117 | AC97LinkState *s = opaque; |
| 1118 | |
| 1119 | record_select(s, mixer_load(s, AC97_Record_Select)); |
| 1120 | set_volume(s, AC97_Master_Volume_Mute, |
| 1121 | mixer_load(s, AC97_Master_Volume_Mute)); |
| 1122 | set_volume(s, AC97_PCM_Out_Volume_Mute, |
| 1123 | mixer_load(s, AC97_PCM_Out_Volume_Mute)); |
| 1124 | set_volume(s, AC97_Record_Gain_Mute, |
| 1125 | mixer_load(s, AC97_Record_Gain_Mute)); |
| 1126 | |
| 1127 | active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); |
| 1128 | active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); |
| 1129 | active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); |
| 1130 | reset_voices(s, active); |
| 1131 | |
| 1132 | s->bup_flag = 0; |
| 1133 | s->last_samp = 0; |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
| 1137 | static bool is_version_2(void *opaque, int version_id) |
| 1138 | { |
| 1139 | return version_id == 2; |
| 1140 | } |
| 1141 | |
| 1142 | static const VMStateDescription vmstate_ac97 = { |
| 1143 | .name = "ac97", |
| 1144 | .version_id = 3, |
| 1145 | .minimum_version_id = 2, |
| 1146 | .post_load = ac97_post_load, |
| 1147 | .fields = (const VMStateField[]) { |
| 1148 | VMSTATE_PCI_DEVICE(dev, AC97LinkState), |
| 1149 | VMSTATE_UINT32(glob_cnt, AC97LinkState), |
| 1150 | VMSTATE_UINT32(glob_sta, AC97LinkState), |
| 1151 | VMSTATE_UINT32(cas, AC97LinkState), |
| 1152 | VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1, |
| 1153 | vmstate_ac97_bm_regs, AC97BusMasterRegs), |
| 1154 | VMSTATE_BUFFER(mixer_data, AC97LinkState), |
| 1155 | VMSTATE_UNUSED_TEST(is_version_2, 3), |
| 1156 | VMSTATE_END_OF_LIST() |
| 1157 | } |
| 1158 | }; |
| 1159 | |
| 1160 | static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) |
| 1161 | { |
| 1162 | if ((addr / size) > 256) { |
| 1163 | return -1; |
| 1164 | } |
| 1165 | |
| 1166 | switch (size) { |
| 1167 | case 1: |
| 1168 | return nam_readb(opaque, addr); |
| 1169 | case 2: |
| 1170 | return nam_readw(opaque, addr); |
| 1171 | case 4: |
| 1172 | return nam_readl(opaque, addr); |
| 1173 | default: |
| 1174 | return -1; |
| 1175 | } |
| 1176 | } |
| 1177 | |
| 1178 | static void nam_write(void *opaque, hwaddr addr, uint64_t val, |
| 1179 | unsigned size) |
| 1180 | { |
| 1181 | if ((addr / size) > 256) { |
| 1182 | return; |
| 1183 | } |
| 1184 | |
| 1185 | switch (size) { |
| 1186 | case 1: |
| 1187 | nam_writeb(opaque, addr, val); |
| 1188 | break; |
| 1189 | case 2: |
| 1190 | nam_writew(opaque, addr, val); |
| 1191 | break; |
| 1192 | case 4: |
| 1193 | nam_writel(opaque, addr, val); |
| 1194 | break; |
| 1195 | } |
| 1196 | } |
| 1197 | |
| 1198 | static const MemoryRegionOps ac97_io_nam_ops = { |
| 1199 | .read = nam_read, |
| 1200 | .write = nam_write, |
| 1201 | .impl = { |
| 1202 | .min_access_size = 1, |
| 1203 | .max_access_size = 4, |
| 1204 | }, |
| 1205 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1206 | }; |
| 1207 | |
| 1208 | static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) |
| 1209 | { |
| 1210 | if ((addr / size) > 64) { |
| 1211 | return -1; |
| 1212 | } |
| 1213 | |
| 1214 | switch (size) { |
| 1215 | case 1: |
| 1216 | return nabm_readb(opaque, addr); |
| 1217 | case 2: |
| 1218 | return nabm_readw(opaque, addr); |
| 1219 | case 4: |
| 1220 | return nabm_readl(opaque, addr); |
| 1221 | default: |
| 1222 | return -1; |
| 1223 | } |
| 1224 | } |
| 1225 | |
| 1226 | static void nabm_write(void *opaque, hwaddr addr, uint64_t val, |
| 1227 | unsigned size) |
| 1228 | { |
| 1229 | if ((addr / size) > 64) { |
| 1230 | return; |
| 1231 | } |
| 1232 | |
| 1233 | switch (size) { |
| 1234 | case 1: |
| 1235 | nabm_writeb(opaque, addr, val); |
| 1236 | break; |
| 1237 | case 2: |
| 1238 | nabm_writew(opaque, addr, val); |
| 1239 | break; |
| 1240 | case 4: |
| 1241 | nabm_writel(opaque, addr, val); |
| 1242 | break; |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | |
| 1247 | static const MemoryRegionOps ac97_io_nabm_ops = { |
| 1248 | .read = nabm_read, |
| 1249 | .write = nabm_write, |
| 1250 | .impl = { |
| 1251 | .min_access_size = 1, |
| 1252 | .max_access_size = 4, |
| 1253 | }, |
| 1254 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1255 | }; |
| 1256 | |
| 1257 | static void ac97_on_reset(DeviceState *dev) |
| 1258 | { |
| 1259 | AC97LinkState *s = AC97(dev); |
| 1260 | |
| 1261 | reset_bm_regs(s, &s->bm_regs[0]); |
| 1262 | reset_bm_regs(s, &s->bm_regs[1]); |
| 1263 | reset_bm_regs(s, &s->bm_regs[2]); |
| 1264 | |
| 1265 | /* |
| 1266 | * Reset the mixer too. The Windows XP driver seems to rely on |
| 1267 | * this. At least it wants to read the vendor id before it resets |
| 1268 | * the codec manually. |
| 1269 | */ |
| 1270 | mixer_reset(s); |
| 1271 | } |
| 1272 | |
| 1273 | static void ac97_realize(PCIDevice *dev, Error **errp) |
| 1274 | { |
| 1275 | AC97LinkState *s = AC97(dev); |
| 1276 | uint8_t *c = s->dev.config; |
| 1277 | |
| 1278 | if (!audio_be_check(&s->audio_be, errp)) { |
| 1279 | return; |
| 1280 | } |
| 1281 | |
| 1282 | c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */ |
| 1283 | c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; |
| 1284 | |
| 1285 | c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */ |
| 1286 | |
| 1287 | c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ |
| 1288 | c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ |
| 1289 | |
| 1290 | memory_region_init_io(&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s, |
| 1291 | "ac97-nam", 1024); |
| 1292 | memory_region_init_io(&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s, |
| 1293 | "ac97-nabm", 256); |
| 1294 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); |
| 1295 | pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); |
| 1296 | |
| 1297 | ac97_on_reset(DEVICE(s)); |
| 1298 | } |
| 1299 | |
| 1300 | static void ac97_exit(PCIDevice *dev) |
| 1301 | { |
| 1302 | AC97LinkState *s = AC97(dev); |
| 1303 | |
| 1304 | audio_be_close_in(s->audio_be, s->voice_pi); |
| 1305 | audio_be_close_out(s->audio_be, s->voice_po); |
| 1306 | audio_be_close_in(s->audio_be, s->voice_mc); |
| 1307 | } |
| 1308 | |
| 1309 | static const Property ac97_properties[] = { |
| 1310 | DEFINE_AUDIO_PROPERTIES(AC97LinkState, audio_be), |
| 1311 | }; |
| 1312 | |
| 1313 | static void ac97_class_init(ObjectClass *klass, const void *data) |
| 1314 | { |
| 1315 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1316 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 1317 | |
| 1318 | k->realize = ac97_realize; |
| 1319 | k->exit = ac97_exit; |
| 1320 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 1321 | k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; |
| 1322 | k->revision = 0x01; |
| 1323 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; |
| 1324 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
| 1325 | dc->desc = "Intel 82801AA AC97 Audio"; |
| 1326 | dc->vmsd = &vmstate_ac97; |
| 1327 | device_class_set_props(dc, ac97_properties); |
| 1328 | device_class_set_legacy_reset(dc, ac97_on_reset); |
| 1329 | } |
| 1330 | |
| 1331 | static const TypeInfo ac97_info = { |
| 1332 | .name = TYPE_AC97, |
| 1333 | .parent = TYPE_PCI_DEVICE, |
| 1334 | .instance_size = sizeof(AC97LinkState), |
| 1335 | .class_init = ac97_class_init, |
| 1336 | .interfaces = (const InterfaceInfo[]) { |
| 1337 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 1338 | { }, |
| 1339 | }, |
| 1340 | }; |
| 1341 | |
| 1342 | static void ac97_register_types(void) |
| 1343 | { |
| 1344 | type_register_static(&ac97_info); |
| 1345 | audio_register_model("ac97", "Intel 82801AA AC97 Audio", TYPE_AC97); |
| 1346 | } |
| 1347 | |
| 1348 | type_init(ac97_register_types) |