| 1 | /* |
| 2 | * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command |
| 3 | * set. Known devices table current as of Jun/2012 and taken from linux. |
| 4 | * See drivers/mtd/devices/m25p80.c. |
| 5 | * |
| 6 | * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> |
| 7 | * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> |
| 8 | * Copyright (C) 2012 PetaLogix |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 or |
| 13 | * (at your option) a later version of the License. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along |
| 21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 22 | */ |
| 23 | |
| 24 | #include "qemu/osdep.h" |
| 25 | #include "qemu/units.h" |
| 26 | #include "system/block-backend.h" |
| 27 | #include "hw/block/block.h" |
| 28 | #include "hw/block/flash.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "hw/core/qdev-properties-system.h" |
| 31 | #include "hw/ssi/ssi.h" |
| 32 | #include "migration/vmstate.h" |
| 33 | #include "qemu/bitops.h" |
| 34 | #include "qemu/log.h" |
| 35 | #include "qemu/module.h" |
| 36 | #include "qemu/error-report.h" |
| 37 | #include "qapi/error.h" |
| 38 | #include "trace.h" |
| 39 | #include "qom/object.h" |
| 40 | #include "m25p80_sfdp.h" |
| 41 | |
| 42 | /* 16 MiB max in 3 byte address mode */ |
| 43 | #define MAX_3BYTES_SIZE 0x1000000 |
| 44 | #define SPI_NOR_MAX_ID_LEN 6 |
| 45 | |
| 46 | /* Fields for FlashPartInfo->flags */ |
| 47 | enum spi_flash_option_flags { |
| 48 | ER_4K = BIT(0), |
| 49 | ER_32K = BIT(1), |
| 50 | EEPROM = BIT(2), |
| 51 | HAS_SR_TB = BIT(3), |
| 52 | HAS_SR_BP3_BIT6 = BIT(4), |
| 53 | }; |
| 54 | |
| 55 | typedef struct FlashPartInfo { |
| 56 | const char *part_name; |
| 57 | /* |
| 58 | * This array stores the ID bytes. |
| 59 | * The first three bytes are the JEDIC ID. |
| 60 | * JEDEC ID zero means "no ID" (mostly older chips). |
| 61 | */ |
| 62 | uint8_t id[SPI_NOR_MAX_ID_LEN]; |
| 63 | uint8_t id_len; |
| 64 | /* |
| 65 | * there is confusion between manufacturers as to what a sector is. In this |
| 66 | * device model, a "sector" is the size that is erased by the ERASE_SECTOR |
| 67 | * command (opcode 0xd8). |
| 68 | */ |
| 69 | uint32_t sector_size; |
| 70 | uint32_t n_sectors; |
| 71 | uint32_t page_size; |
| 72 | uint16_t flags; |
| 73 | /* |
| 74 | * Big sized spi nor are often stacked devices, thus sometime |
| 75 | * replace chip erase with die erase. |
| 76 | * This field inform how many die is in the chip. |
| 77 | */ |
| 78 | uint8_t die_cnt; |
| 79 | uint8_t (*sfdp_read)(uint32_t sfdp_addr); |
| 80 | } FlashPartInfo; |
| 81 | |
| 82 | /* adapted from linux */ |
| 83 | /* Used when the "_ext_id" is two bytes at most */ |
| 84 | #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ |
| 85 | .part_name = _part_name,\ |
| 86 | .id = {\ |
| 87 | ((_jedec_id) >> 16) & 0xff,\ |
| 88 | ((_jedec_id) >> 8) & 0xff,\ |
| 89 | (_jedec_id) & 0xff,\ |
| 90 | ((_ext_id) >> 8) & 0xff,\ |
| 91 | (_ext_id) & 0xff,\ |
| 92 | },\ |
| 93 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ |
| 94 | .sector_size = (_sector_size),\ |
| 95 | .n_sectors = (_n_sectors),\ |
| 96 | .page_size = 256,\ |
| 97 | .flags = (_flags),\ |
| 98 | .die_cnt = 0 |
| 99 | |
| 100 | #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ |
| 101 | .part_name = _part_name,\ |
| 102 | .id = {\ |
| 103 | ((_jedec_id) >> 16) & 0xff,\ |
| 104 | ((_jedec_id) >> 8) & 0xff,\ |
| 105 | (_jedec_id) & 0xff,\ |
| 106 | ((_ext_id) >> 16) & 0xff,\ |
| 107 | ((_ext_id) >> 8) & 0xff,\ |
| 108 | (_ext_id) & 0xff,\ |
| 109 | },\ |
| 110 | .id_len = 6,\ |
| 111 | .sector_size = (_sector_size),\ |
| 112 | .n_sectors = (_n_sectors),\ |
| 113 | .page_size = 256,\ |
| 114 | .flags = (_flags),\ |
| 115 | .die_cnt = 0 |
| 116 | |
| 117 | #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ |
| 118 | _flags, _die_cnt)\ |
| 119 | .part_name = _part_name,\ |
| 120 | .id = {\ |
| 121 | ((_jedec_id) >> 16) & 0xff,\ |
| 122 | ((_jedec_id) >> 8) & 0xff,\ |
| 123 | (_jedec_id) & 0xff,\ |
| 124 | ((_ext_id) >> 8) & 0xff,\ |
| 125 | (_ext_id) & 0xff,\ |
| 126 | },\ |
| 127 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ |
| 128 | .sector_size = (_sector_size),\ |
| 129 | .n_sectors = (_n_sectors),\ |
| 130 | .page_size = 256,\ |
| 131 | .flags = (_flags),\ |
| 132 | .die_cnt = _die_cnt |
| 133 | |
| 134 | #define JEDEC_NUMONYX 0x20 |
| 135 | #define JEDEC_WINBOND 0xEF |
| 136 | #define JEDEC_SPANSION 0x01 |
| 137 | |
| 138 | /* Numonyx (Micron) Configuration register macros */ |
| 139 | #define VCFG_DUMMY 0x1 |
| 140 | #define VCFG_WRAP_SEQUENTIAL 0x2 |
| 141 | #define NVCFG_XIP_MODE_DISABLED (7 << 9) |
| 142 | #define NVCFG_XIP_MODE_MASK (7 << 9) |
| 143 | #define VCFG_XIP_MODE_DISABLED (1 << 3) |
| 144 | #define CFG_DUMMY_CLK_LEN 4 |
| 145 | #define NVCFG_DUMMY_CLK_POS 12 |
| 146 | #define VCFG_DUMMY_CLK_POS 4 |
| 147 | #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 |
| 148 | #define EVCFG_VPP_ACCELERATOR (1 << 3) |
| 149 | #define EVCFG_RESET_HOLD_ENABLED (1 << 4) |
| 150 | #define NVCFG_DUAL_IO_MASK (1 << 2) |
| 151 | #define EVCFG_DUAL_IO_DISABLED (1 << 6) |
| 152 | #define NVCFG_QUAD_IO_MASK (1 << 3) |
| 153 | #define EVCFG_QUAD_IO_DISABLED (1 << 7) |
| 154 | #define NVCFG_4BYTE_ADDR_MASK (1 << 0) |
| 155 | #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) |
| 156 | |
| 157 | /* Numonyx (Micron) Flag Status Register macros */ |
| 158 | #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 |
| 159 | #define FSR_FLASH_READY (1 << 7) |
| 160 | |
| 161 | /* Spansion configuration registers macros. */ |
| 162 | #define SPANSION_QUAD_CFG_POS 0 |
| 163 | #define SPANSION_QUAD_CFG_LEN 1 |
| 164 | #define SPANSION_DUMMY_CLK_POS 0 |
| 165 | #define SPANSION_DUMMY_CLK_LEN 4 |
| 166 | #define SPANSION_ADDR_LEN_POS 7 |
| 167 | #define SPANSION_ADDR_LEN_LEN 1 |
| 168 | |
| 169 | /* |
| 170 | * Spansion read mode command length in bytes, |
| 171 | * the mode is currently not supported. |
| 172 | */ |
| 173 | |
| 174 | #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 |
| 175 | #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 |
| 176 | |
| 177 | static const FlashPartInfo known_devices[] = { |
| 178 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
| 179 | { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, |
| 180 | { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, |
| 181 | |
| 182 | { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, |
| 183 | { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, |
| 184 | { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, |
| 185 | |
| 186 | { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, |
| 187 | { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, |
| 188 | { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, |
| 189 | { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, |
| 190 | |
| 191 | { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, |
| 192 | |
| 193 | /* |
| 194 | * Atmel EEPROMS - it is assumed, that don't care bit in command |
| 195 | * is set to 0. Block protection is not supported. |
| 196 | */ |
| 197 | { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, |
| 198 | { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, |
| 199 | |
| 200 | /* EON -- en25xxx */ |
| 201 | { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, |
| 202 | { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, |
| 203 | { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, |
| 204 | { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, |
| 205 | { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, |
| 206 | |
| 207 | /* GigaDevice */ |
| 208 | { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, |
| 209 | { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, |
| 210 | |
| 211 | /* Intel/Numonyx -- xxxs33b */ |
| 212 | { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, |
| 213 | { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, |
| 214 | { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, |
| 215 | { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, |
| 216 | |
| 217 | /* ISSI */ |
| 218 | { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, |
| 219 | { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, |
| 220 | { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, |
| 221 | ER_4K | HAS_SR_TB) }, |
| 222 | { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, |
| 223 | { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, |
| 224 | { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, |
| 225 | { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, |
| 226 | { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, |
| 227 | { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, |
| 228 | { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, |
| 229 | { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), |
| 230 | .sfdp_read = m25p80_sfdp_is25wp256 }, |
| 231 | |
| 232 | /* Macronix */ |
| 233 | { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, |
| 234 | { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, |
| 235 | { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, |
| 236 | { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, |
| 237 | { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, |
| 238 | { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, |
| 239 | { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, |
| 240 | { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, |
| 241 | { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, |
| 242 | ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, |
| 243 | { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, |
| 244 | ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, |
| 245 | { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, |
| 246 | { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, |
| 247 | { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, |
| 248 | { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, |
| 249 | { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), |
| 250 | .sfdp_read = m25p80_sfdp_mx66l1g45g }, |
| 251 | |
| 252 | /* Micron */ |
| 253 | { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, |
| 254 | { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, |
| 255 | { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, |
| 256 | { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, |
| 257 | { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, |
| 258 | { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, |
| 259 | { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, |
| 260 | { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), |
| 261 | .sfdp_read = m25p80_sfdp_n25q256a }, |
| 262 | { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, |
| 263 | { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, |
| 264 | { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, |
| 265 | { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, |
| 266 | ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), |
| 267 | .sfdp_read = m25p80_sfdp_n25q256a }, |
| 268 | { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, |
| 269 | { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, |
| 270 | { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, |
| 271 | { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, |
| 272 | ER_4K | ER_32K, 2), |
| 273 | .sfdp_read = m25p80_sfdp_mt35xu01g }, |
| 274 | { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048, |
| 275 | ER_4K | ER_32K, 4), |
| 276 | .sfdp_read = m25p80_sfdp_mt35xu02g }, |
| 277 | { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, |
| 278 | { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, |
| 279 | { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, |
| 280 | { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, |
| 281 | { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, |
| 282 | ER_4K | ER_32K, 2) }, |
| 283 | { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, |
| 284 | ER_4K | ER_32K, 2) }, |
| 285 | |
| 286 | /* |
| 287 | * Spansion -- single (large) sector size only, at least |
| 288 | * for the chips listed here (without boot sectors). |
| 289 | */ |
| 290 | { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, |
| 291 | { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, |
| 292 | { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, |
| 293 | { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, |
| 294 | { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, |
| 295 | { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, |
| 296 | { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, |
| 297 | { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, |
| 298 | { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, |
| 299 | { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, |
| 300 | { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, |
| 301 | { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, |
| 302 | { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, |
| 303 | { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, |
| 304 | { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, |
| 305 | { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, |
| 306 | { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, |
| 307 | |
| 308 | /* Spansion -- boot sectors support */ |
| 309 | { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, |
| 310 | { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, |
| 311 | |
| 312 | /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ |
| 313 | { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, |
| 314 | { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, |
| 315 | { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, |
| 316 | { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, |
| 317 | { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, |
| 318 | { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, |
| 319 | { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, |
| 320 | { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, |
| 321 | { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, |
| 322 | |
| 323 | /* ST Microelectronics -- newer production may have feature updates */ |
| 324 | { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, |
| 325 | { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, |
| 326 | { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, |
| 327 | { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, |
| 328 | { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, |
| 329 | { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, |
| 330 | { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, |
| 331 | { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, |
| 332 | { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, |
| 333 | { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, |
| 334 | |
| 335 | { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, |
| 336 | { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, |
| 337 | { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, |
| 338 | |
| 339 | { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, |
| 340 | { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, |
| 341 | { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, |
| 342 | |
| 343 | { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, |
| 344 | { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, |
| 345 | { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, |
| 346 | { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, |
| 347 | |
| 348 | /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ |
| 349 | { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, |
| 350 | { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, |
| 351 | { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, |
| 352 | { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, |
| 353 | { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, |
| 354 | { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, |
| 355 | { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, |
| 356 | { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, |
| 357 | { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, |
| 358 | { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, |
| 359 | { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, |
| 360 | { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K), |
| 361 | .sfdp_read = m25p80_sfdp_w25q80bl }, |
| 362 | { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), |
| 363 | .sfdp_read = m25p80_sfdp_w25q256 }, |
| 364 | { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), |
| 365 | .sfdp_read = m25p80_sfdp_w25q512jv }, |
| 366 | { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), |
| 367 | .sfdp_read = m25p80_sfdp_w25q01jvq }, |
| 368 | { INFO("w25q02jvm", 0xef7022, 0, 64 << 10, 4096, ER_4K), |
| 369 | .sfdp_read = m25p80_sfdp_w25q02jvm }, |
| 370 | |
| 371 | /* Microchip */ |
| 372 | { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) }, |
| 373 | }; |
| 374 | |
| 375 | typedef enum { |
| 376 | NOP = 0, |
| 377 | WRSR = 0x1, |
| 378 | WRDI = 0x4, |
| 379 | RDSR = 0x5, |
| 380 | WREN = 0x6, |
| 381 | BRRD = 0x16, |
| 382 | BRWR = 0x17, |
| 383 | JEDEC_READ = 0x9f, |
| 384 | BULK_ERASE_60 = 0x60, |
| 385 | BULK_ERASE = 0xc7, |
| 386 | READ_FSR = 0x70, |
| 387 | RDCR = 0x15, |
| 388 | RDSFDP = 0x5a, |
| 389 | |
| 390 | READ = 0x03, |
| 391 | READ4 = 0x13, |
| 392 | FAST_READ = 0x0b, |
| 393 | FAST_READ4 = 0x0c, |
| 394 | DOR = 0x3b, |
| 395 | DOR4 = 0x3c, |
| 396 | QOR = 0x6b, |
| 397 | QOR4 = 0x6c, |
| 398 | DIOR = 0xbb, |
| 399 | DIOR4 = 0xbc, |
| 400 | QIOR = 0xeb, |
| 401 | QIOR4 = 0xec, |
| 402 | |
| 403 | PP = 0x02, |
| 404 | PP4 = 0x12, |
| 405 | PP4_4 = 0x3e, |
| 406 | DPP = 0xa2, |
| 407 | QPP = 0x32, |
| 408 | QPP_4 = 0x34, |
| 409 | RDID_90 = 0x90, |
| 410 | RDID_AB = 0xab, |
| 411 | AAI_WP = 0xad, |
| 412 | |
| 413 | ERASE_4K = 0x20, |
| 414 | ERASE4_4K = 0x21, |
| 415 | ERASE_32K = 0x52, |
| 416 | ERASE4_32K = 0x5c, |
| 417 | ERASE_SECTOR = 0xd8, |
| 418 | ERASE4_SECTOR = 0xdc, |
| 419 | |
| 420 | EN_4BYTE_ADDR = 0xB7, |
| 421 | EX_4BYTE_ADDR = 0xE9, |
| 422 | |
| 423 | EXTEND_ADDR_READ = 0xC8, |
| 424 | EXTEND_ADDR_WRITE = 0xC5, |
| 425 | |
| 426 | RESET_ENABLE = 0x66, |
| 427 | RESET_MEMORY = 0x99, |
| 428 | |
| 429 | /* |
| 430 | * Micron: 0x35 - enable QPI |
| 431 | * Spansion: 0x35 - read control register |
| 432 | * Winbond: 0x35 - quad enable |
| 433 | */ |
| 434 | RDCR_EQIO = 0x35, |
| 435 | RSTQIO = 0xf5, |
| 436 | |
| 437 | /* |
| 438 | * Winbond: 0x31 - write status register 2 |
| 439 | */ |
| 440 | WRSR2 = 0x31, |
| 441 | |
| 442 | RNVCR = 0xB5, |
| 443 | WNVCR = 0xB1, |
| 444 | |
| 445 | RVCR = 0x85, |
| 446 | WVCR = 0x81, |
| 447 | |
| 448 | REVCR = 0x65, |
| 449 | WEVCR = 0x61, |
| 450 | |
| 451 | DIE_ERASE = 0xC4, |
| 452 | } FlashCMD; |
| 453 | |
| 454 | typedef enum { |
| 455 | STATE_IDLE, |
| 456 | STATE_PAGE_PROGRAM, |
| 457 | STATE_READ, |
| 458 | STATE_COLLECTING_DATA, |
| 459 | STATE_COLLECTING_VAR_LEN_DATA, |
| 460 | STATE_READING_DATA, |
| 461 | STATE_READING_SFDP, |
| 462 | } CMDState; |
| 463 | |
| 464 | typedef enum { |
| 465 | MAN_SPANSION, |
| 466 | MAN_MACRONIX, |
| 467 | MAN_NUMONYX, |
| 468 | MAN_WINBOND, |
| 469 | MAN_SST, |
| 470 | MAN_ISSI, |
| 471 | MAN_GENERIC, |
| 472 | } Manufacturer; |
| 473 | |
| 474 | typedef enum { |
| 475 | MODE_STD = 0, |
| 476 | MODE_DIO = 1, |
| 477 | MODE_QIO = 2 |
| 478 | } SPIMode; |
| 479 | |
| 480 | #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 |
| 481 | |
| 482 | struct Flash { |
| 483 | SSIPeripheral parent_obj; |
| 484 | |
| 485 | BlockBackend *blk; |
| 486 | |
| 487 | uint8_t *storage; |
| 488 | uint32_t size; |
| 489 | int page_size; |
| 490 | |
| 491 | uint8_t state; |
| 492 | uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; |
| 493 | uint32_t len; |
| 494 | uint32_t pos; |
| 495 | bool data_read_loop; |
| 496 | uint8_t needed_bytes; |
| 497 | uint8_t cmd_in_progress; |
| 498 | uint32_t cur_addr; |
| 499 | uint32_t nonvolatile_cfg; |
| 500 | /* Configuration register for Macronix */ |
| 501 | uint32_t volatile_cfg; |
| 502 | uint32_t enh_volatile_cfg; |
| 503 | /* Spansion cfg registers. */ |
| 504 | uint8_t spansion_cr1nv; |
| 505 | uint8_t spansion_cr2nv; |
| 506 | uint8_t spansion_cr3nv; |
| 507 | uint8_t spansion_cr4nv; |
| 508 | uint8_t spansion_cr1v; |
| 509 | uint8_t spansion_cr2v; |
| 510 | uint8_t spansion_cr3v; |
| 511 | uint8_t spansion_cr4v; |
| 512 | bool wp_level; |
| 513 | bool write_enable; |
| 514 | bool four_bytes_address_mode; |
| 515 | bool reset_enable; |
| 516 | bool quad_enable; |
| 517 | bool aai_enable; |
| 518 | bool block_protect0; |
| 519 | bool block_protect1; |
| 520 | bool block_protect2; |
| 521 | bool block_protect3; |
| 522 | bool top_bottom_bit; |
| 523 | bool status_register_write_disabled; |
| 524 | uint8_t ear; |
| 525 | |
| 526 | int64_t dirty_page; |
| 527 | |
| 528 | const FlashPartInfo *pi; |
| 529 | |
| 530 | }; |
| 531 | |
| 532 | struct M25P80Class { |
| 533 | SSIPeripheralClass parent_class; |
| 534 | const FlashPartInfo *pi; |
| 535 | }; |
| 536 | |
| 537 | OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) |
| 538 | |
| 539 | static inline Manufacturer get_man(Flash *s) |
| 540 | { |
| 541 | switch (s->pi->id[0]) { |
| 542 | case 0x20: |
| 543 | return MAN_NUMONYX; |
| 544 | case 0xEF: |
| 545 | return MAN_WINBOND; |
| 546 | case 0x01: |
| 547 | return MAN_SPANSION; |
| 548 | case 0xC2: |
| 549 | return MAN_MACRONIX; |
| 550 | case 0xBF: |
| 551 | return MAN_SST; |
| 552 | case 0x9D: |
| 553 | return MAN_ISSI; |
| 554 | default: |
| 555 | return MAN_GENERIC; |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | static void blk_sync_complete(void *opaque, int ret) |
| 560 | { |
| 561 | QEMUIOVector *iov = opaque; |
| 562 | |
| 563 | qemu_iovec_destroy(iov); |
| 564 | g_free(iov); |
| 565 | |
| 566 | /* |
| 567 | * do nothing. Masters do not directly interact with the backing store, |
| 568 | * only the working copy so no mutexing required. |
| 569 | */ |
| 570 | } |
| 571 | |
| 572 | static void flash_sync_page(Flash *s, int page) |
| 573 | { |
| 574 | QEMUIOVector *iov; |
| 575 | |
| 576 | if (!s->blk || !blk_is_writable(s->blk)) { |
| 577 | return; |
| 578 | } |
| 579 | |
| 580 | iov = g_new(QEMUIOVector, 1); |
| 581 | qemu_iovec_init(iov, 1); |
| 582 | qemu_iovec_add(iov, s->storage + page * s->pi->page_size, |
| 583 | s->pi->page_size); |
| 584 | blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, |
| 585 | blk_sync_complete, iov); |
| 586 | } |
| 587 | |
| 588 | static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) |
| 589 | { |
| 590 | QEMUIOVector *iov; |
| 591 | |
| 592 | if (!s->blk || !blk_is_writable(s->blk)) { |
| 593 | return; |
| 594 | } |
| 595 | |
| 596 | assert(!(len % BDRV_SECTOR_SIZE)); |
| 597 | iov = g_new(QEMUIOVector, 1); |
| 598 | qemu_iovec_init(iov, 1); |
| 599 | qemu_iovec_add(iov, s->storage + off, len); |
| 600 | blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); |
| 601 | } |
| 602 | |
| 603 | static void flash_erase(Flash *s, int offset, FlashCMD cmd) |
| 604 | { |
| 605 | uint32_t len; |
| 606 | uint8_t capa_to_assert = 0; |
| 607 | |
| 608 | switch (cmd) { |
| 609 | case ERASE_4K: |
| 610 | case ERASE4_4K: |
| 611 | len = 4 * KiB; |
| 612 | capa_to_assert = ER_4K; |
| 613 | break; |
| 614 | case ERASE_32K: |
| 615 | case ERASE4_32K: |
| 616 | len = 32 * KiB; |
| 617 | capa_to_assert = ER_32K; |
| 618 | break; |
| 619 | case ERASE_SECTOR: |
| 620 | case ERASE4_SECTOR: |
| 621 | len = s->pi->sector_size; |
| 622 | break; |
| 623 | case BULK_ERASE: |
| 624 | len = s->size; |
| 625 | break; |
| 626 | case DIE_ERASE: |
| 627 | if (s->pi->die_cnt) { |
| 628 | len = s->size / s->pi->die_cnt; |
| 629 | offset = offset & (~(len - 1)); |
| 630 | } else { |
| 631 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" |
| 632 | " by device\n"); |
| 633 | return; |
| 634 | } |
| 635 | break; |
| 636 | default: |
| 637 | abort(); |
| 638 | } |
| 639 | |
| 640 | trace_m25p80_flash_erase(s, offset, len); |
| 641 | |
| 642 | if ((s->pi->flags & capa_to_assert) != capa_to_assert) { |
| 643 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" |
| 644 | " device\n", len); |
| 645 | } |
| 646 | |
| 647 | if (!s->write_enable) { |
| 648 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); |
| 649 | return; |
| 650 | } |
| 651 | memset(s->storage + offset, 0xff, len); |
| 652 | flash_sync_area(s, offset, len); |
| 653 | } |
| 654 | |
| 655 | static inline void flash_sync_dirty(Flash *s, int64_t newpage) |
| 656 | { |
| 657 | if (s->dirty_page >= 0 && s->dirty_page != newpage) { |
| 658 | flash_sync_page(s, s->dirty_page); |
| 659 | s->dirty_page = newpage; |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | static inline |
| 664 | void flash_write8(Flash *s, uint32_t addr, uint8_t data) |
| 665 | { |
| 666 | uint32_t page = addr / s->pi->page_size; |
| 667 | uint8_t prev = s->storage[s->cur_addr]; |
| 668 | uint32_t block_protect_value = (s->block_protect3 << 3) | |
| 669 | (s->block_protect2 << 2) | |
| 670 | (s->block_protect1 << 1) | |
| 671 | (s->block_protect0 << 0); |
| 672 | |
| 673 | if (!s->write_enable) { |
| 674 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); |
| 675 | return; |
| 676 | } |
| 677 | |
| 678 | if (block_protect_value > 0) { |
| 679 | uint32_t num_protected_sectors = 1 << (block_protect_value - 1); |
| 680 | uint32_t sector = addr / s->pi->sector_size; |
| 681 | |
| 682 | /* top_bottom_bit == 0 means TOP */ |
| 683 | if (!s->top_bottom_bit) { |
| 684 | if (s->pi->n_sectors <= sector + num_protected_sectors) { |
| 685 | qemu_log_mask(LOG_GUEST_ERROR, |
| 686 | "M25P80: write with write protect!\n"); |
| 687 | return; |
| 688 | } |
| 689 | } else { |
| 690 | if (sector < num_protected_sectors) { |
| 691 | qemu_log_mask(LOG_GUEST_ERROR, |
| 692 | "M25P80: write with write protect!\n"); |
| 693 | return; |
| 694 | } |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | if ((prev ^ data) & data) { |
| 699 | trace_m25p80_programming_zero_to_one(s, addr, prev, data); |
| 700 | } |
| 701 | |
| 702 | if (s->pi->flags & EEPROM) { |
| 703 | s->storage[s->cur_addr] = data; |
| 704 | } else { |
| 705 | s->storage[s->cur_addr] &= data; |
| 706 | } |
| 707 | |
| 708 | flash_sync_dirty(s, page); |
| 709 | s->dirty_page = page; |
| 710 | } |
| 711 | |
| 712 | static inline int get_addr_length(Flash *s) |
| 713 | { |
| 714 | /* check if eeprom is in use */ |
| 715 | if (s->pi->flags == EEPROM) { |
| 716 | return 2; |
| 717 | } |
| 718 | |
| 719 | switch (s->cmd_in_progress) { |
| 720 | case RDSFDP: |
| 721 | return 3; |
| 722 | case PP4: |
| 723 | case PP4_4: |
| 724 | case QPP_4: |
| 725 | case READ4: |
| 726 | case QIOR4: |
| 727 | case ERASE4_4K: |
| 728 | case ERASE4_32K: |
| 729 | case ERASE4_SECTOR: |
| 730 | case FAST_READ4: |
| 731 | case DOR4: |
| 732 | case QOR4: |
| 733 | case DIOR4: |
| 734 | return 4; |
| 735 | default: |
| 736 | return s->four_bytes_address_mode ? 4 : 3; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | static void complete_collecting_data(Flash *s) |
| 741 | { |
| 742 | int i, n; |
| 743 | |
| 744 | n = get_addr_length(s); |
| 745 | s->cur_addr = (n == 3 ? s->ear : 0); |
| 746 | for (i = 0; i < n; ++i) { |
| 747 | s->cur_addr <<= 8; |
| 748 | s->cur_addr |= s->data[i]; |
| 749 | } |
| 750 | |
| 751 | s->cur_addr &= s->size - 1; |
| 752 | |
| 753 | s->state = STATE_IDLE; |
| 754 | |
| 755 | trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, |
| 756 | s->cur_addr); |
| 757 | |
| 758 | switch (s->cmd_in_progress) { |
| 759 | case DPP: |
| 760 | case QPP: |
| 761 | case QPP_4: |
| 762 | case PP: |
| 763 | case PP4: |
| 764 | case PP4_4: |
| 765 | s->state = STATE_PAGE_PROGRAM; |
| 766 | break; |
| 767 | case AAI_WP: |
| 768 | /* AAI programming starts from the even address */ |
| 769 | s->cur_addr &= ~BIT(0); |
| 770 | s->state = STATE_PAGE_PROGRAM; |
| 771 | break; |
| 772 | case READ: |
| 773 | case READ4: |
| 774 | case FAST_READ: |
| 775 | case FAST_READ4: |
| 776 | case DOR: |
| 777 | case DOR4: |
| 778 | case QOR: |
| 779 | case QOR4: |
| 780 | case DIOR: |
| 781 | case DIOR4: |
| 782 | case QIOR: |
| 783 | case QIOR4: |
| 784 | s->state = STATE_READ; |
| 785 | break; |
| 786 | case ERASE_4K: |
| 787 | case ERASE4_4K: |
| 788 | case ERASE_32K: |
| 789 | case ERASE4_32K: |
| 790 | case ERASE_SECTOR: |
| 791 | case ERASE4_SECTOR: |
| 792 | case DIE_ERASE: |
| 793 | flash_erase(s, s->cur_addr, s->cmd_in_progress); |
| 794 | break; |
| 795 | case WRSR: |
| 796 | s->status_register_write_disabled = extract32(s->data[0], 7, 1); |
| 797 | s->block_protect0 = extract32(s->data[0], 2, 1); |
| 798 | s->block_protect1 = extract32(s->data[0], 3, 1); |
| 799 | s->block_protect2 = extract32(s->data[0], 4, 1); |
| 800 | if (s->pi->flags & HAS_SR_TB) { |
| 801 | s->top_bottom_bit = extract32(s->data[0], 5, 1); |
| 802 | } |
| 803 | if (s->pi->flags & HAS_SR_BP3_BIT6) { |
| 804 | s->block_protect3 = extract32(s->data[0], 6, 1); |
| 805 | } |
| 806 | |
| 807 | switch (get_man(s)) { |
| 808 | case MAN_SPANSION: |
| 809 | s->quad_enable = !!(s->data[1] & 0x02); |
| 810 | break; |
| 811 | case MAN_ISSI: |
| 812 | s->quad_enable = extract32(s->data[0], 6, 1); |
| 813 | break; |
| 814 | case MAN_MACRONIX: |
| 815 | s->quad_enable = extract32(s->data[0], 6, 1); |
| 816 | if (s->len > 1) { |
| 817 | s->volatile_cfg = s->data[1]; |
| 818 | s->four_bytes_address_mode = extract32(s->data[1], 5, 1); |
| 819 | } |
| 820 | break; |
| 821 | case MAN_WINBOND: |
| 822 | if (s->len > 1) { |
| 823 | s->quad_enable = !!(s->data[1] & 0x02); |
| 824 | } |
| 825 | break; |
| 826 | default: |
| 827 | break; |
| 828 | } |
| 829 | if (s->write_enable) { |
| 830 | s->write_enable = false; |
| 831 | } |
| 832 | break; |
| 833 | case WRSR2: |
| 834 | switch (get_man(s)) { |
| 835 | case MAN_WINBOND: |
| 836 | s->quad_enable = !!(s->data[0] & 0x02); |
| 837 | break; |
| 838 | default: |
| 839 | break; |
| 840 | } |
| 841 | break; |
| 842 | case BRWR: |
| 843 | case EXTEND_ADDR_WRITE: |
| 844 | s->ear = s->data[0]; |
| 845 | break; |
| 846 | case WNVCR: |
| 847 | s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); |
| 848 | break; |
| 849 | case WVCR: |
| 850 | s->volatile_cfg = s->data[0]; |
| 851 | break; |
| 852 | case WEVCR: |
| 853 | s->enh_volatile_cfg = s->data[0]; |
| 854 | break; |
| 855 | case RDID_90: |
| 856 | case RDID_AB: |
| 857 | if (get_man(s) == MAN_SST) { |
| 858 | if (s->cur_addr <= 1) { |
| 859 | if (s->cur_addr) { |
| 860 | s->data[0] = s->pi->id[2]; |
| 861 | s->data[1] = s->pi->id[0]; |
| 862 | } else { |
| 863 | s->data[0] = s->pi->id[0]; |
| 864 | s->data[1] = s->pi->id[2]; |
| 865 | } |
| 866 | s->pos = 0; |
| 867 | s->len = 2; |
| 868 | s->data_read_loop = true; |
| 869 | s->state = STATE_READING_DATA; |
| 870 | } else { |
| 871 | qemu_log_mask(LOG_GUEST_ERROR, |
| 872 | "M25P80: Invalid read id address\n"); |
| 873 | } |
| 874 | } else { |
| 875 | qemu_log_mask(LOG_GUEST_ERROR, |
| 876 | "M25P80: Read id (command 0x90/0xAB) is not supported" |
| 877 | " by device\n"); |
| 878 | } |
| 879 | break; |
| 880 | |
| 881 | case RDSFDP: |
| 882 | s->state = STATE_READING_SFDP; |
| 883 | break; |
| 884 | |
| 885 | default: |
| 886 | break; |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | static void reset_memory(Flash *s) |
| 891 | { |
| 892 | s->cmd_in_progress = NOP; |
| 893 | s->cur_addr = 0; |
| 894 | s->ear = 0; |
| 895 | s->four_bytes_address_mode = false; |
| 896 | s->len = 0; |
| 897 | s->needed_bytes = 0; |
| 898 | s->pos = 0; |
| 899 | s->state = STATE_IDLE; |
| 900 | s->write_enable = false; |
| 901 | s->reset_enable = false; |
| 902 | s->quad_enable = false; |
| 903 | s->aai_enable = false; |
| 904 | |
| 905 | switch (get_man(s)) { |
| 906 | case MAN_NUMONYX: |
| 907 | s->volatile_cfg = 0; |
| 908 | s->volatile_cfg |= VCFG_DUMMY; |
| 909 | s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; |
| 910 | if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) |
| 911 | == NVCFG_XIP_MODE_DISABLED) { |
| 912 | s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; |
| 913 | } |
| 914 | s->volatile_cfg |= deposit32(s->volatile_cfg, |
| 915 | VCFG_DUMMY_CLK_POS, |
| 916 | CFG_DUMMY_CLK_LEN, |
| 917 | extract32(s->nonvolatile_cfg, |
| 918 | NVCFG_DUMMY_CLK_POS, |
| 919 | CFG_DUMMY_CLK_LEN) |
| 920 | ); |
| 921 | |
| 922 | s->enh_volatile_cfg = 0; |
| 923 | s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; |
| 924 | s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; |
| 925 | s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; |
| 926 | if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { |
| 927 | s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; |
| 928 | } |
| 929 | if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { |
| 930 | s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; |
| 931 | } |
| 932 | if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { |
| 933 | s->four_bytes_address_mode = true; |
| 934 | } |
| 935 | if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { |
| 936 | s->ear = s->size / MAX_3BYTES_SIZE - 1; |
| 937 | } |
| 938 | break; |
| 939 | case MAN_MACRONIX: |
| 940 | s->volatile_cfg = 0x7; |
| 941 | break; |
| 942 | case MAN_SPANSION: |
| 943 | s->spansion_cr1v = s->spansion_cr1nv; |
| 944 | s->spansion_cr2v = s->spansion_cr2nv; |
| 945 | s->spansion_cr3v = s->spansion_cr3nv; |
| 946 | s->spansion_cr4v = s->spansion_cr4nv; |
| 947 | s->quad_enable = extract32(s->spansion_cr1v, |
| 948 | SPANSION_QUAD_CFG_POS, |
| 949 | SPANSION_QUAD_CFG_LEN |
| 950 | ); |
| 951 | s->four_bytes_address_mode = extract32(s->spansion_cr2v, |
| 952 | SPANSION_ADDR_LEN_POS, |
| 953 | SPANSION_ADDR_LEN_LEN |
| 954 | ); |
| 955 | break; |
| 956 | default: |
| 957 | break; |
| 958 | } |
| 959 | |
| 960 | trace_m25p80_reset_done(s); |
| 961 | } |
| 962 | |
| 963 | static uint8_t numonyx_mode(Flash *s) |
| 964 | { |
| 965 | if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { |
| 966 | return MODE_QIO; |
| 967 | } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { |
| 968 | return MODE_DIO; |
| 969 | } else { |
| 970 | return MODE_STD; |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | static uint8_t numonyx_extract_cfg_dummy_bytes(Flash *s) |
| 975 | { |
| 976 | uint8_t dummy_bits; |
| 977 | uint8_t mode; |
| 978 | |
| 979 | mode = numonyx_mode(s); |
| 980 | dummy_bits = extract32(s->volatile_cfg, 4, 4); |
| 981 | |
| 982 | /* |
| 983 | * The default nubmer of dummy cycles is only related to the SPI |
| 984 | * protocol mode. For QSPI it is 10, otherwise it is 8. |
| 985 | */ |
| 986 | if (dummy_bits == 0x0 || dummy_bits == 0xf) { |
| 987 | dummy_bits = (mode == MODE_QIO) ? 10 : 8; |
| 988 | } |
| 989 | |
| 990 | /* |
| 991 | * Convert the number of dummy cycles to bytes. |
| 992 | * |
| 993 | * In the Dual I/O and Quad I/O protocols, all command phases use 2 or 4 |
| 994 | * lines. In standard/extended SPI mode the phase width depends on the |
| 995 | * command sequence: output-only fast reads keep the dummy clocks on the |
| 996 | * single address line, while input/output fast reads use the same 2-line |
| 997 | * or 4-line phase as the address. |
| 998 | */ |
| 999 | |
| 1000 | if (mode == MODE_QIO) { |
| 1001 | dummy_bits *= 4; |
| 1002 | } else if (mode == MODE_DIO) { |
| 1003 | dummy_bits *= 2; |
| 1004 | } else { |
| 1005 | switch (s->cmd_in_progress) { |
| 1006 | case QIOR: |
| 1007 | case QIOR4: |
| 1008 | dummy_bits *= 4; |
| 1009 | break; |
| 1010 | case DIOR: |
| 1011 | case DIOR4: |
| 1012 | dummy_bits *= 2; |
| 1013 | break; |
| 1014 | } |
| 1015 | } |
| 1016 | |
| 1017 | /* |
| 1018 | * Assert that the dummy bit count is byte-aligned |
| 1019 | * as SSI core can only consume whole dummy bytes. |
| 1020 | */ |
| 1021 | assert(dummy_bits % 8 == 0); |
| 1022 | |
| 1023 | /* return the number of dummy bytes */ |
| 1024 | return dummy_bits / 8; |
| 1025 | } |
| 1026 | |
| 1027 | static uint8_t macronix_extract_cfg_dummy_bytes(Flash *s, uint8_t bus_width) |
| 1028 | { |
| 1029 | static const uint8_t dummy_cycles_fast[4] = { 8, 6, 8, 10 }; |
| 1030 | static const uint8_t dummy_cycles_dio[4] = { 4, 6, 8, 10 }; |
| 1031 | static const uint8_t dummy_cycles_qio[4] = { 6, 4, 8, 10 }; |
| 1032 | const uint8_t *dummy_cycles = dummy_cycles_fast; |
| 1033 | uint8_t dummy_bits; |
| 1034 | |
| 1035 | switch (s->cmd_in_progress) { |
| 1036 | case DIOR: |
| 1037 | case DIOR4: |
| 1038 | dummy_cycles = dummy_cycles_dio; |
| 1039 | break; |
| 1040 | case QIOR: |
| 1041 | case QIOR4: |
| 1042 | dummy_cycles = dummy_cycles_qio; |
| 1043 | break; |
| 1044 | default: |
| 1045 | break; |
| 1046 | } |
| 1047 | |
| 1048 | dummy_bits = dummy_cycles[extract32(s->volatile_cfg, 6, 2)]; |
| 1049 | dummy_bits *= bus_width; |
| 1050 | |
| 1051 | /* |
| 1052 | * Assert that the dummy bit count is byte-aligned |
| 1053 | * as SSI core can only consume whole dummy bytes. |
| 1054 | */ |
| 1055 | assert(dummy_bits % 8 == 0); |
| 1056 | |
| 1057 | return dummy_bits / 8; |
| 1058 | } |
| 1059 | |
| 1060 | static uint8_t spansion_extract_cfg_dummy_bytes(Flash *s, uint8_t bus_width) |
| 1061 | { |
| 1062 | uint8_t dummy_bits; |
| 1063 | |
| 1064 | dummy_bits = extract32(s->spansion_cr2v, SPANSION_DUMMY_CLK_POS, |
| 1065 | SPANSION_DUMMY_CLK_LEN); |
| 1066 | dummy_bits *= bus_width; |
| 1067 | |
| 1068 | /* |
| 1069 | * Assert that the dummy bit count is byte-aligned |
| 1070 | * as SSI core can only consume whole dummy bytes. |
| 1071 | */ |
| 1072 | assert(dummy_bits % 8 == 0); |
| 1073 | |
| 1074 | return dummy_bits / 8; |
| 1075 | } |
| 1076 | |
| 1077 | static void decode_fast_read_cmd(Flash *s) |
| 1078 | { |
| 1079 | s->needed_bytes = get_addr_length(s); |
| 1080 | switch (get_man(s)) { |
| 1081 | /* Dummy cycles - modeled with bytes writes instead of bits */ |
| 1082 | case MAN_SST: |
| 1083 | s->needed_bytes += 1; |
| 1084 | break; |
| 1085 | case MAN_WINBOND: |
| 1086 | s->needed_bytes += 1; |
| 1087 | break; |
| 1088 | case MAN_NUMONYX: |
| 1089 | s->needed_bytes += numonyx_extract_cfg_dummy_bytes(s); |
| 1090 | break; |
| 1091 | case MAN_MACRONIX: |
| 1092 | s->needed_bytes += macronix_extract_cfg_dummy_bytes(s, 1); |
| 1093 | break; |
| 1094 | case MAN_SPANSION: |
| 1095 | s->needed_bytes += spansion_extract_cfg_dummy_bytes(s, 1); |
| 1096 | break; |
| 1097 | case MAN_ISSI: |
| 1098 | /* |
| 1099 | * The Fast Read instruction code is followed by address bytes and |
| 1100 | * dummy cycles, transmitted via the SI line. |
| 1101 | * |
| 1102 | * The number of dummy cycles is configurable but this is currently |
| 1103 | * unmodeled, hence the default value 8 is used. |
| 1104 | * |
| 1105 | * QPI (Quad Peripheral Interface) mode has different default value |
| 1106 | * of dummy cycles, but this is unsupported at the time being. |
| 1107 | */ |
| 1108 | s->needed_bytes += 1; |
| 1109 | break; |
| 1110 | default: |
| 1111 | break; |
| 1112 | } |
| 1113 | s->pos = 0; |
| 1114 | s->len = 0; |
| 1115 | s->state = STATE_COLLECTING_DATA; |
| 1116 | } |
| 1117 | |
| 1118 | static void decode_dio_read_cmd(Flash *s) |
| 1119 | { |
| 1120 | s->needed_bytes = get_addr_length(s); |
| 1121 | /* Dummy cycles modeled with bytes writes instead of bits */ |
| 1122 | switch (get_man(s)) { |
| 1123 | case MAN_WINBOND: |
| 1124 | s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; |
| 1125 | break; |
| 1126 | case MAN_SPANSION: |
| 1127 | s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; |
| 1128 | s->needed_bytes += spansion_extract_cfg_dummy_bytes(s, 2); |
| 1129 | break; |
| 1130 | case MAN_NUMONYX: |
| 1131 | s->needed_bytes += numonyx_extract_cfg_dummy_bytes(s); |
| 1132 | break; |
| 1133 | case MAN_MACRONIX: |
| 1134 | s->needed_bytes += macronix_extract_cfg_dummy_bytes(s, 2); |
| 1135 | break; |
| 1136 | case MAN_ISSI: |
| 1137 | /* |
| 1138 | * The Fast Read Dual I/O instruction code is followed by address bytes |
| 1139 | * and dummy cycles, transmitted via the IO1 and IO0 line. |
| 1140 | * |
| 1141 | * The number of dummy cycles is configurable but this is currently |
| 1142 | * unmodeled, hence the default value 4 is used. |
| 1143 | */ |
| 1144 | s->needed_bytes += 1; |
| 1145 | break; |
| 1146 | default: |
| 1147 | break; |
| 1148 | } |
| 1149 | s->pos = 0; |
| 1150 | s->len = 0; |
| 1151 | s->state = STATE_COLLECTING_DATA; |
| 1152 | } |
| 1153 | |
| 1154 | static void decode_qio_read_cmd(Flash *s) |
| 1155 | { |
| 1156 | s->needed_bytes = get_addr_length(s); |
| 1157 | /* Dummy cycles modeled with bytes writes instead of bits */ |
| 1158 | switch (get_man(s)) { |
| 1159 | case MAN_WINBOND: |
| 1160 | s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; |
| 1161 | s->needed_bytes += 2; |
| 1162 | break; |
| 1163 | case MAN_SPANSION: |
| 1164 | s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; |
| 1165 | s->needed_bytes += spansion_extract_cfg_dummy_bytes(s, 4); |
| 1166 | break; |
| 1167 | case MAN_NUMONYX: |
| 1168 | s->needed_bytes += numonyx_extract_cfg_dummy_bytes(s); |
| 1169 | break; |
| 1170 | case MAN_MACRONIX: |
| 1171 | s->needed_bytes += macronix_extract_cfg_dummy_bytes(s, 4); |
| 1172 | break; |
| 1173 | case MAN_ISSI: |
| 1174 | /* |
| 1175 | * The Fast Read Quad I/O instruction code is followed by address bytes |
| 1176 | * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. |
| 1177 | * |
| 1178 | * The number of dummy cycles is configurable but this is currently |
| 1179 | * unmodeled, hence the default value 6 is used. |
| 1180 | * |
| 1181 | * QPI (Quad Peripheral Interface) mode has different default value |
| 1182 | * of dummy cycles, but this is unsupported at the time being. |
| 1183 | */ |
| 1184 | s->needed_bytes += 3; |
| 1185 | break; |
| 1186 | default: |
| 1187 | break; |
| 1188 | } |
| 1189 | s->pos = 0; |
| 1190 | s->len = 0; |
| 1191 | s->state = STATE_COLLECTING_DATA; |
| 1192 | } |
| 1193 | |
| 1194 | static bool is_valid_aai_cmd(uint32_t cmd) |
| 1195 | { |
| 1196 | return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; |
| 1197 | } |
| 1198 | |
| 1199 | static void decode_new_cmd(Flash *s, uint32_t value) |
| 1200 | { |
| 1201 | int i; |
| 1202 | |
| 1203 | s->cmd_in_progress = value; |
| 1204 | trace_m25p80_command_decoded(s, value); |
| 1205 | |
| 1206 | if (value != RESET_MEMORY) { |
| 1207 | s->reset_enable = false; |
| 1208 | } |
| 1209 | |
| 1210 | if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { |
| 1211 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1212 | "M25P80: Invalid cmd within AAI programming sequence"); |
| 1213 | } |
| 1214 | |
| 1215 | switch (value) { |
| 1216 | |
| 1217 | case ERASE_4K: |
| 1218 | case ERASE4_4K: |
| 1219 | case ERASE_32K: |
| 1220 | case ERASE4_32K: |
| 1221 | case ERASE_SECTOR: |
| 1222 | case ERASE4_SECTOR: |
| 1223 | case PP: |
| 1224 | case PP4: |
| 1225 | case DIE_ERASE: |
| 1226 | case RDID_90: |
| 1227 | case RDID_AB: |
| 1228 | s->needed_bytes = get_addr_length(s); |
| 1229 | s->pos = 0; |
| 1230 | s->len = 0; |
| 1231 | s->state = STATE_COLLECTING_DATA; |
| 1232 | break; |
| 1233 | case READ: |
| 1234 | case READ4: |
| 1235 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { |
| 1236 | s->needed_bytes = get_addr_length(s); |
| 1237 | s->pos = 0; |
| 1238 | s->len = 0; |
| 1239 | s->state = STATE_COLLECTING_DATA; |
| 1240 | } else { |
| 1241 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1242 | "DIO or QIO mode\n", s->cmd_in_progress); |
| 1243 | } |
| 1244 | break; |
| 1245 | case DPP: |
| 1246 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { |
| 1247 | s->needed_bytes = get_addr_length(s); |
| 1248 | s->pos = 0; |
| 1249 | s->len = 0; |
| 1250 | s->state = STATE_COLLECTING_DATA; |
| 1251 | } else { |
| 1252 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1253 | "QIO mode\n", s->cmd_in_progress); |
| 1254 | } |
| 1255 | break; |
| 1256 | case QPP: |
| 1257 | case QPP_4: |
| 1258 | case PP4_4: |
| 1259 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { |
| 1260 | s->needed_bytes = get_addr_length(s); |
| 1261 | s->pos = 0; |
| 1262 | s->len = 0; |
| 1263 | s->state = STATE_COLLECTING_DATA; |
| 1264 | } else { |
| 1265 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1266 | "DIO mode\n", s->cmd_in_progress); |
| 1267 | } |
| 1268 | break; |
| 1269 | |
| 1270 | case FAST_READ: |
| 1271 | case FAST_READ4: |
| 1272 | decode_fast_read_cmd(s); |
| 1273 | break; |
| 1274 | case DOR: |
| 1275 | case DOR4: |
| 1276 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { |
| 1277 | decode_fast_read_cmd(s); |
| 1278 | } else { |
| 1279 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1280 | "QIO mode\n", s->cmd_in_progress); |
| 1281 | } |
| 1282 | break; |
| 1283 | case QOR: |
| 1284 | case QOR4: |
| 1285 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { |
| 1286 | decode_fast_read_cmd(s); |
| 1287 | } else { |
| 1288 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1289 | "DIO mode\n", s->cmd_in_progress); |
| 1290 | } |
| 1291 | break; |
| 1292 | |
| 1293 | case DIOR: |
| 1294 | case DIOR4: |
| 1295 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { |
| 1296 | decode_dio_read_cmd(s); |
| 1297 | } else { |
| 1298 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1299 | "QIO mode\n", s->cmd_in_progress); |
| 1300 | } |
| 1301 | break; |
| 1302 | |
| 1303 | case QIOR: |
| 1304 | case QIOR4: |
| 1305 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { |
| 1306 | decode_qio_read_cmd(s); |
| 1307 | } else { |
| 1308 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " |
| 1309 | "DIO mode\n", s->cmd_in_progress); |
| 1310 | } |
| 1311 | break; |
| 1312 | |
| 1313 | case WRSR: |
| 1314 | /* |
| 1315 | * If WP# is low and status_register_write_disabled is high, |
| 1316 | * status register writes are disabled. |
| 1317 | * This is also called "hardware protected mode" (HPM). All other |
| 1318 | * combinations of the two states are called "software protected mode" |
| 1319 | * (SPM), and status register writes are permitted. |
| 1320 | */ |
| 1321 | if ((s->wp_level == 0 && s->status_register_write_disabled) |
| 1322 | || !s->write_enable) { |
| 1323 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1324 | "M25P80: Status register write is disabled!\n"); |
| 1325 | break; |
| 1326 | } |
| 1327 | |
| 1328 | switch (get_man(s)) { |
| 1329 | case MAN_SPANSION: |
| 1330 | s->needed_bytes = 2; |
| 1331 | s->state = STATE_COLLECTING_DATA; |
| 1332 | break; |
| 1333 | case MAN_MACRONIX: |
| 1334 | s->needed_bytes = 2; |
| 1335 | s->state = STATE_COLLECTING_VAR_LEN_DATA; |
| 1336 | break; |
| 1337 | case MAN_WINBOND: |
| 1338 | s->needed_bytes = 2; |
| 1339 | s->state = STATE_COLLECTING_VAR_LEN_DATA; |
| 1340 | break; |
| 1341 | default: |
| 1342 | s->needed_bytes = 1; |
| 1343 | s->state = STATE_COLLECTING_DATA; |
| 1344 | } |
| 1345 | s->pos = 0; |
| 1346 | break; |
| 1347 | case WRSR2: |
| 1348 | /* |
| 1349 | * If WP# is low and status_register_write_disabled is high, |
| 1350 | * status register writes are disabled. |
| 1351 | * This is also called "hardware protected mode" (HPM). All other |
| 1352 | * combinations of the two states are called "software protected mode" |
| 1353 | * (SPM), and status register writes are permitted. |
| 1354 | */ |
| 1355 | if ((s->wp_level == 0 && s->status_register_write_disabled) |
| 1356 | || !s->write_enable) { |
| 1357 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1358 | "M25P80: Status register 2 write is disabled!\n"); |
| 1359 | break; |
| 1360 | } |
| 1361 | |
| 1362 | switch (get_man(s)) { |
| 1363 | case MAN_WINBOND: |
| 1364 | s->needed_bytes = 1; |
| 1365 | s->state = STATE_COLLECTING_DATA; |
| 1366 | s->pos = 0; |
| 1367 | break; |
| 1368 | default: |
| 1369 | break; |
| 1370 | } |
| 1371 | break; |
| 1372 | case WRDI: |
| 1373 | s->write_enable = false; |
| 1374 | if (get_man(s) == MAN_SST) { |
| 1375 | s->aai_enable = false; |
| 1376 | } |
| 1377 | break; |
| 1378 | case WREN: |
| 1379 | s->write_enable = true; |
| 1380 | break; |
| 1381 | |
| 1382 | case RDSR: |
| 1383 | s->data[0] = (!!s->write_enable) << 1; |
| 1384 | s->data[0] |= (!!s->status_register_write_disabled) << 7; |
| 1385 | s->data[0] |= (!!s->block_protect0) << 2; |
| 1386 | s->data[0] |= (!!s->block_protect1) << 3; |
| 1387 | s->data[0] |= (!!s->block_protect2) << 4; |
| 1388 | if (s->pi->flags & HAS_SR_TB) { |
| 1389 | s->data[0] |= (!!s->top_bottom_bit) << 5; |
| 1390 | } |
| 1391 | if (s->pi->flags & HAS_SR_BP3_BIT6) { |
| 1392 | s->data[0] |= (!!s->block_protect3) << 6; |
| 1393 | } |
| 1394 | |
| 1395 | if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { |
| 1396 | s->data[0] |= (!!s->quad_enable) << 6; |
| 1397 | } |
| 1398 | if (get_man(s) == MAN_SST) { |
| 1399 | s->data[0] |= (!!s->aai_enable) << 6; |
| 1400 | } |
| 1401 | |
| 1402 | s->pos = 0; |
| 1403 | s->len = 1; |
| 1404 | s->data_read_loop = true; |
| 1405 | s->state = STATE_READING_DATA; |
| 1406 | break; |
| 1407 | |
| 1408 | case READ_FSR: |
| 1409 | s->data[0] = FSR_FLASH_READY; |
| 1410 | if (s->four_bytes_address_mode) { |
| 1411 | s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; |
| 1412 | } |
| 1413 | s->pos = 0; |
| 1414 | s->len = 1; |
| 1415 | s->data_read_loop = true; |
| 1416 | s->state = STATE_READING_DATA; |
| 1417 | break; |
| 1418 | |
| 1419 | case JEDEC_READ: |
| 1420 | if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { |
| 1421 | trace_m25p80_populated_jedec(s); |
| 1422 | for (i = 0; i < s->pi->id_len; i++) { |
| 1423 | s->data[i] = s->pi->id[i]; |
| 1424 | } |
| 1425 | for (; i < SPI_NOR_MAX_ID_LEN; i++) { |
| 1426 | s->data[i] = 0; |
| 1427 | } |
| 1428 | |
| 1429 | s->len = SPI_NOR_MAX_ID_LEN; |
| 1430 | s->pos = 0; |
| 1431 | s->state = STATE_READING_DATA; |
| 1432 | } else { |
| 1433 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " |
| 1434 | "in DIO or QIO mode\n"); |
| 1435 | } |
| 1436 | break; |
| 1437 | |
| 1438 | case RDCR: |
| 1439 | s->data[0] = s->volatile_cfg & 0xFF; |
| 1440 | s->data[0] |= (!!s->four_bytes_address_mode) << 5; |
| 1441 | s->pos = 0; |
| 1442 | s->len = 1; |
| 1443 | s->state = STATE_READING_DATA; |
| 1444 | break; |
| 1445 | |
| 1446 | case BULK_ERASE_60: |
| 1447 | case BULK_ERASE: |
| 1448 | if (s->write_enable) { |
| 1449 | trace_m25p80_chip_erase(s); |
| 1450 | flash_erase(s, 0, BULK_ERASE); |
| 1451 | } else { |
| 1452 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " |
| 1453 | "protect!\n"); |
| 1454 | } |
| 1455 | break; |
| 1456 | case NOP: |
| 1457 | break; |
| 1458 | case EN_4BYTE_ADDR: |
| 1459 | s->four_bytes_address_mode = true; |
| 1460 | break; |
| 1461 | case EX_4BYTE_ADDR: |
| 1462 | s->four_bytes_address_mode = false; |
| 1463 | break; |
| 1464 | case BRRD: |
| 1465 | case EXTEND_ADDR_READ: |
| 1466 | s->data[0] = s->ear; |
| 1467 | s->pos = 0; |
| 1468 | s->len = 1; |
| 1469 | s->state = STATE_READING_DATA; |
| 1470 | break; |
| 1471 | case BRWR: |
| 1472 | case EXTEND_ADDR_WRITE: |
| 1473 | if (s->write_enable) { |
| 1474 | s->needed_bytes = 1; |
| 1475 | s->pos = 0; |
| 1476 | s->len = 0; |
| 1477 | s->state = STATE_COLLECTING_DATA; |
| 1478 | } |
| 1479 | break; |
| 1480 | case RNVCR: |
| 1481 | s->data[0] = s->nonvolatile_cfg & 0xFF; |
| 1482 | s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; |
| 1483 | s->pos = 0; |
| 1484 | s->len = 2; |
| 1485 | s->state = STATE_READING_DATA; |
| 1486 | break; |
| 1487 | case WNVCR: |
| 1488 | if (s->write_enable && get_man(s) == MAN_NUMONYX) { |
| 1489 | s->needed_bytes = 2; |
| 1490 | s->pos = 0; |
| 1491 | s->len = 0; |
| 1492 | s->state = STATE_COLLECTING_DATA; |
| 1493 | } |
| 1494 | break; |
| 1495 | case RVCR: |
| 1496 | s->data[0] = s->volatile_cfg & 0xFF; |
| 1497 | s->pos = 0; |
| 1498 | s->len = 1; |
| 1499 | s->state = STATE_READING_DATA; |
| 1500 | break; |
| 1501 | case WVCR: |
| 1502 | if (s->write_enable) { |
| 1503 | s->needed_bytes = 1; |
| 1504 | s->pos = 0; |
| 1505 | s->len = 0; |
| 1506 | s->state = STATE_COLLECTING_DATA; |
| 1507 | } |
| 1508 | break; |
| 1509 | case REVCR: |
| 1510 | s->data[0] = s->enh_volatile_cfg & 0xFF; |
| 1511 | s->pos = 0; |
| 1512 | s->len = 1; |
| 1513 | s->state = STATE_READING_DATA; |
| 1514 | break; |
| 1515 | case WEVCR: |
| 1516 | if (s->write_enable) { |
| 1517 | s->needed_bytes = 1; |
| 1518 | s->pos = 0; |
| 1519 | s->len = 0; |
| 1520 | s->state = STATE_COLLECTING_DATA; |
| 1521 | } |
| 1522 | break; |
| 1523 | case RESET_ENABLE: |
| 1524 | s->reset_enable = true; |
| 1525 | break; |
| 1526 | case RESET_MEMORY: |
| 1527 | if (s->reset_enable) { |
| 1528 | reset_memory(s); |
| 1529 | } |
| 1530 | break; |
| 1531 | case RDCR_EQIO: |
| 1532 | switch (get_man(s)) { |
| 1533 | case MAN_SPANSION: |
| 1534 | s->data[0] = (!!s->quad_enable) << 1; |
| 1535 | s->pos = 0; |
| 1536 | s->len = 1; |
| 1537 | s->state = STATE_READING_DATA; |
| 1538 | break; |
| 1539 | case MAN_MACRONIX: |
| 1540 | s->quad_enable = true; |
| 1541 | break; |
| 1542 | case MAN_WINBOND: |
| 1543 | s->data[0] = (!!s->quad_enable) << 1; |
| 1544 | s->pos = 0; |
| 1545 | s->len = 1; |
| 1546 | s->state = STATE_READING_DATA; |
| 1547 | break; |
| 1548 | default: |
| 1549 | break; |
| 1550 | } |
| 1551 | break; |
| 1552 | case RSTQIO: |
| 1553 | s->quad_enable = false; |
| 1554 | break; |
| 1555 | case AAI_WP: |
| 1556 | if (get_man(s) == MAN_SST) { |
| 1557 | if (s->write_enable) { |
| 1558 | if (s->aai_enable) { |
| 1559 | s->state = STATE_PAGE_PROGRAM; |
| 1560 | } else { |
| 1561 | s->aai_enable = true; |
| 1562 | s->needed_bytes = get_addr_length(s); |
| 1563 | s->state = STATE_COLLECTING_DATA; |
| 1564 | } |
| 1565 | } else { |
| 1566 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1567 | "M25P80: AAI_WP with write protect\n"); |
| 1568 | } |
| 1569 | } else { |
| 1570 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); |
| 1571 | } |
| 1572 | break; |
| 1573 | case RDSFDP: |
| 1574 | if (s->pi->sfdp_read) { |
| 1575 | s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ |
| 1576 | s->pos = 0; |
| 1577 | s->len = 0; |
| 1578 | s->state = STATE_COLLECTING_DATA; |
| 1579 | break; |
| 1580 | } |
| 1581 | /* Fallthrough */ |
| 1582 | |
| 1583 | default: |
| 1584 | s->pos = 0; |
| 1585 | s->len = 1; |
| 1586 | s->state = STATE_READING_DATA; |
| 1587 | s->data_read_loop = true; |
| 1588 | s->data[0] = 0; |
| 1589 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); |
| 1590 | break; |
| 1591 | } |
| 1592 | } |
| 1593 | |
| 1594 | static int m25p80_cs(SSIPeripheral *ss, bool select) |
| 1595 | { |
| 1596 | Flash *s = M25P80(ss); |
| 1597 | |
| 1598 | if (select) { |
| 1599 | if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { |
| 1600 | complete_collecting_data(s); |
| 1601 | } |
| 1602 | s->len = 0; |
| 1603 | s->pos = 0; |
| 1604 | s->state = STATE_IDLE; |
| 1605 | flash_sync_dirty(s, -1); |
| 1606 | s->data_read_loop = false; |
| 1607 | } |
| 1608 | |
| 1609 | trace_m25p80_select(s, select ? "de" : ""); |
| 1610 | |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) |
| 1615 | { |
| 1616 | Flash *s = M25P80(ss); |
| 1617 | uint32_t r = 0; |
| 1618 | |
| 1619 | trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, |
| 1620 | s->cur_addr, (uint8_t)tx); |
| 1621 | |
| 1622 | switch (s->state) { |
| 1623 | |
| 1624 | case STATE_PAGE_PROGRAM: |
| 1625 | trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); |
| 1626 | flash_write8(s, s->cur_addr, (uint8_t)tx); |
| 1627 | s->cur_addr = (s->cur_addr + 1) & (s->size - 1); |
| 1628 | |
| 1629 | if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { |
| 1630 | /* |
| 1631 | * There is no wrap mode during AAI programming once the highest |
| 1632 | * unprotected memory address is reached. The Write-Enable-Latch |
| 1633 | * bit is automatically reset, and AAI programming mode aborts. |
| 1634 | */ |
| 1635 | s->write_enable = false; |
| 1636 | s->aai_enable = false; |
| 1637 | } |
| 1638 | |
| 1639 | break; |
| 1640 | |
| 1641 | case STATE_READ: |
| 1642 | r = s->storage[s->cur_addr]; |
| 1643 | trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); |
| 1644 | s->cur_addr = (s->cur_addr + 1) & (s->size - 1); |
| 1645 | break; |
| 1646 | |
| 1647 | case STATE_COLLECTING_DATA: |
| 1648 | case STATE_COLLECTING_VAR_LEN_DATA: |
| 1649 | |
| 1650 | if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { |
| 1651 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1652 | "M25P80: Write overrun internal data buffer. " |
| 1653 | "SPI controller (QEMU emulator or guest driver) " |
| 1654 | "is misbehaving\n"); |
| 1655 | s->len = s->pos = 0; |
| 1656 | s->state = STATE_IDLE; |
| 1657 | break; |
| 1658 | } |
| 1659 | |
| 1660 | s->data[s->len] = (uint8_t)tx; |
| 1661 | s->len++; |
| 1662 | |
| 1663 | if (s->len == s->needed_bytes) { |
| 1664 | complete_collecting_data(s); |
| 1665 | } |
| 1666 | break; |
| 1667 | |
| 1668 | case STATE_READING_DATA: |
| 1669 | |
| 1670 | if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { |
| 1671 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1672 | "M25P80: Read overrun internal data buffer. " |
| 1673 | "SPI controller (QEMU emulator or guest driver) " |
| 1674 | "is misbehaving\n"); |
| 1675 | s->len = s->pos = 0; |
| 1676 | s->state = STATE_IDLE; |
| 1677 | break; |
| 1678 | } |
| 1679 | |
| 1680 | r = s->data[s->pos]; |
| 1681 | trace_m25p80_read_data(s, s->pos, (uint8_t)r); |
| 1682 | s->pos++; |
| 1683 | if (s->pos == s->len) { |
| 1684 | s->pos = 0; |
| 1685 | if (!s->data_read_loop) { |
| 1686 | s->state = STATE_IDLE; |
| 1687 | } |
| 1688 | } |
| 1689 | break; |
| 1690 | case STATE_READING_SFDP: |
| 1691 | assert(s->pi->sfdp_read); |
| 1692 | r = s->pi->sfdp_read(s->cur_addr); |
| 1693 | trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); |
| 1694 | s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); |
| 1695 | break; |
| 1696 | |
| 1697 | default: |
| 1698 | case STATE_IDLE: |
| 1699 | decode_new_cmd(s, (uint8_t)tx); |
| 1700 | break; |
| 1701 | } |
| 1702 | |
| 1703 | return r; |
| 1704 | } |
| 1705 | |
| 1706 | static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) |
| 1707 | { |
| 1708 | Flash *s = M25P80(opaque); |
| 1709 | /* WP# is just a single pin. */ |
| 1710 | assert(n == 0); |
| 1711 | s->wp_level = !!level; |
| 1712 | } |
| 1713 | |
| 1714 | static void m25p80_realize(SSIPeripheral *ss, Error **errp) |
| 1715 | { |
| 1716 | Flash *s = M25P80(ss); |
| 1717 | M25P80Class *mc = M25P80_GET_CLASS(s); |
| 1718 | int ret; |
| 1719 | |
| 1720 | s->pi = mc->pi; |
| 1721 | |
| 1722 | s->size = s->pi->sector_size * s->pi->n_sectors; |
| 1723 | s->dirty_page = -1; |
| 1724 | |
| 1725 | if (s->blk) { |
| 1726 | uint64_t perm = BLK_PERM_CONSISTENT_READ | |
| 1727 | (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); |
| 1728 | ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); |
| 1729 | if (ret < 0) { |
| 1730 | return; |
| 1731 | } |
| 1732 | |
| 1733 | trace_m25p80_binding(s); |
| 1734 | s->storage = blk_blockalign(s->blk, s->size); |
| 1735 | |
| 1736 | if (!blk_check_size_and_read_all(s->blk, DEVICE(s), |
| 1737 | s->storage, s->size, errp)) { |
| 1738 | return; |
| 1739 | } |
| 1740 | } else { |
| 1741 | trace_m25p80_binding_no_bdrv(s); |
| 1742 | s->storage = blk_blockalign(NULL, s->size); |
| 1743 | memset(s->storage, 0xFF, s->size); |
| 1744 | } |
| 1745 | |
| 1746 | qdev_init_gpio_in_named(DEVICE(s), |
| 1747 | m25p80_write_protect_pin_irq_handler, "WP#", 1); |
| 1748 | } |
| 1749 | |
| 1750 | static void m25p80_reset(DeviceState *d) |
| 1751 | { |
| 1752 | Flash *s = M25P80(d); |
| 1753 | |
| 1754 | s->wp_level = true; |
| 1755 | s->status_register_write_disabled = false; |
| 1756 | s->block_protect0 = false; |
| 1757 | s->block_protect1 = false; |
| 1758 | s->block_protect2 = false; |
| 1759 | s->block_protect3 = false; |
| 1760 | s->top_bottom_bit = false; |
| 1761 | |
| 1762 | reset_memory(s); |
| 1763 | } |
| 1764 | |
| 1765 | static int m25p80_pre_save(void *opaque) |
| 1766 | { |
| 1767 | flash_sync_dirty((Flash *)opaque, -1); |
| 1768 | |
| 1769 | return 0; |
| 1770 | } |
| 1771 | |
| 1772 | static const Property m25p80_properties[] = { |
| 1773 | /* This is default value for Micron flash */ |
| 1774 | DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), |
| 1775 | DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), |
| 1776 | DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), |
| 1777 | DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), |
| 1778 | DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), |
| 1779 | DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), |
| 1780 | DEFINE_PROP_DRIVE("drive", Flash, blk), |
| 1781 | }; |
| 1782 | |
| 1783 | static int m25p80_pre_load(void *opaque) |
| 1784 | { |
| 1785 | Flash *s = (Flash *)opaque; |
| 1786 | |
| 1787 | s->data_read_loop = false; |
| 1788 | return 0; |
| 1789 | } |
| 1790 | |
| 1791 | static bool m25p80_data_read_loop_needed(void *opaque) |
| 1792 | { |
| 1793 | Flash *s = (Flash *)opaque; |
| 1794 | |
| 1795 | return s->data_read_loop; |
| 1796 | } |
| 1797 | |
| 1798 | static const VMStateDescription vmstate_m25p80_data_read_loop = { |
| 1799 | .name = "m25p80/data_read_loop", |
| 1800 | .version_id = 1, |
| 1801 | .minimum_version_id = 1, |
| 1802 | .needed = m25p80_data_read_loop_needed, |
| 1803 | .fields = (const VMStateField[]) { |
| 1804 | VMSTATE_BOOL(data_read_loop, Flash), |
| 1805 | VMSTATE_END_OF_LIST() |
| 1806 | } |
| 1807 | }; |
| 1808 | |
| 1809 | static bool m25p80_aai_enable_needed(void *opaque) |
| 1810 | { |
| 1811 | Flash *s = (Flash *)opaque; |
| 1812 | |
| 1813 | return s->aai_enable; |
| 1814 | } |
| 1815 | |
| 1816 | static const VMStateDescription vmstate_m25p80_aai_enable = { |
| 1817 | .name = "m25p80/aai_enable", |
| 1818 | .version_id = 1, |
| 1819 | .minimum_version_id = 1, |
| 1820 | .needed = m25p80_aai_enable_needed, |
| 1821 | .fields = (const VMStateField[]) { |
| 1822 | VMSTATE_BOOL(aai_enable, Flash), |
| 1823 | VMSTATE_END_OF_LIST() |
| 1824 | } |
| 1825 | }; |
| 1826 | |
| 1827 | static bool m25p80_wp_level_srwd_needed(void *opaque) |
| 1828 | { |
| 1829 | Flash *s = (Flash *)opaque; |
| 1830 | |
| 1831 | return !s->wp_level || s->status_register_write_disabled; |
| 1832 | } |
| 1833 | |
| 1834 | static const VMStateDescription vmstate_m25p80_write_protect = { |
| 1835 | .name = "m25p80/write_protect", |
| 1836 | .version_id = 1, |
| 1837 | .minimum_version_id = 1, |
| 1838 | .needed = m25p80_wp_level_srwd_needed, |
| 1839 | .fields = (const VMStateField[]) { |
| 1840 | VMSTATE_BOOL(wp_level, Flash), |
| 1841 | VMSTATE_BOOL(status_register_write_disabled, Flash), |
| 1842 | VMSTATE_END_OF_LIST() |
| 1843 | } |
| 1844 | }; |
| 1845 | |
| 1846 | static bool m25p80_block_protect_needed(void *opaque) |
| 1847 | { |
| 1848 | Flash *s = (Flash *)opaque; |
| 1849 | |
| 1850 | return s->block_protect0 || |
| 1851 | s->block_protect1 || |
| 1852 | s->block_protect2 || |
| 1853 | s->block_protect3 || |
| 1854 | s->top_bottom_bit; |
| 1855 | } |
| 1856 | |
| 1857 | static const VMStateDescription vmstate_m25p80_block_protect = { |
| 1858 | .name = "m25p80/block_protect", |
| 1859 | .version_id = 1, |
| 1860 | .minimum_version_id = 1, |
| 1861 | .needed = m25p80_block_protect_needed, |
| 1862 | .fields = (const VMStateField[]) { |
| 1863 | VMSTATE_BOOL(block_protect0, Flash), |
| 1864 | VMSTATE_BOOL(block_protect1, Flash), |
| 1865 | VMSTATE_BOOL(block_protect2, Flash), |
| 1866 | VMSTATE_BOOL(block_protect3, Flash), |
| 1867 | VMSTATE_BOOL(top_bottom_bit, Flash), |
| 1868 | VMSTATE_END_OF_LIST() |
| 1869 | } |
| 1870 | }; |
| 1871 | |
| 1872 | static const VMStateDescription vmstate_m25p80 = { |
| 1873 | .name = "m25p80", |
| 1874 | .version_id = 0, |
| 1875 | .minimum_version_id = 0, |
| 1876 | .pre_save = m25p80_pre_save, |
| 1877 | .pre_load = m25p80_pre_load, |
| 1878 | .fields = (const VMStateField[]) { |
| 1879 | VMSTATE_UINT8(state, Flash), |
| 1880 | VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), |
| 1881 | VMSTATE_UINT32(len, Flash), |
| 1882 | VMSTATE_UINT32(pos, Flash), |
| 1883 | VMSTATE_UINT8(needed_bytes, Flash), |
| 1884 | VMSTATE_UINT8(cmd_in_progress, Flash), |
| 1885 | VMSTATE_UINT32(cur_addr, Flash), |
| 1886 | VMSTATE_BOOL(write_enable, Flash), |
| 1887 | VMSTATE_BOOL(reset_enable, Flash), |
| 1888 | VMSTATE_UINT8(ear, Flash), |
| 1889 | VMSTATE_BOOL(four_bytes_address_mode, Flash), |
| 1890 | VMSTATE_UINT32(nonvolatile_cfg, Flash), |
| 1891 | VMSTATE_UINT32(volatile_cfg, Flash), |
| 1892 | VMSTATE_UINT32(enh_volatile_cfg, Flash), |
| 1893 | VMSTATE_BOOL(quad_enable, Flash), |
| 1894 | VMSTATE_UINT8(spansion_cr1nv, Flash), |
| 1895 | VMSTATE_UINT8(spansion_cr2nv, Flash), |
| 1896 | VMSTATE_UINT8(spansion_cr3nv, Flash), |
| 1897 | VMSTATE_UINT8(spansion_cr4nv, Flash), |
| 1898 | VMSTATE_END_OF_LIST() |
| 1899 | }, |
| 1900 | .subsections = (const VMStateDescription * const []) { |
| 1901 | &vmstate_m25p80_data_read_loop, |
| 1902 | &vmstate_m25p80_aai_enable, |
| 1903 | &vmstate_m25p80_write_protect, |
| 1904 | &vmstate_m25p80_block_protect, |
| 1905 | NULL |
| 1906 | } |
| 1907 | }; |
| 1908 | |
| 1909 | static void m25p80_class_init(ObjectClass *klass, const void *data) |
| 1910 | { |
| 1911 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1912 | SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); |
| 1913 | M25P80Class *mc = M25P80_CLASS(klass); |
| 1914 | |
| 1915 | k->realize = m25p80_realize; |
| 1916 | k->transfer = m25p80_transfer8; |
| 1917 | k->set_cs = m25p80_cs; |
| 1918 | k->cs_polarity = SSI_CS_LOW; |
| 1919 | dc->vmsd = &vmstate_m25p80; |
| 1920 | device_class_set_props(dc, m25p80_properties); |
| 1921 | device_class_set_legacy_reset(dc, m25p80_reset); |
| 1922 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 1923 | mc->pi = data; |
| 1924 | dc->desc = "Serial Flash"; |
| 1925 | } |
| 1926 | |
| 1927 | static const TypeInfo m25p80_info = { |
| 1928 | .name = TYPE_M25P80, |
| 1929 | .parent = TYPE_SSI_PERIPHERAL, |
| 1930 | .instance_size = sizeof(Flash), |
| 1931 | .class_size = sizeof(M25P80Class), |
| 1932 | .abstract = true, |
| 1933 | }; |
| 1934 | |
| 1935 | static void m25p80_register_types(void) |
| 1936 | { |
| 1937 | int i; |
| 1938 | |
| 1939 | type_register_static(&m25p80_info); |
| 1940 | for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { |
| 1941 | const TypeInfo ti = { |
| 1942 | .name = known_devices[i].part_name, |
| 1943 | .parent = TYPE_M25P80, |
| 1944 | .class_init = m25p80_class_init, |
| 1945 | .class_data = &known_devices[i], |
| 1946 | }; |
| 1947 | type_register_static(&ti); |
| 1948 | } |
| 1949 | } |
| 1950 | |
| 1951 | type_init(m25p80_register_types) |
| 1952 | |
| 1953 | BlockBackend *m25p80_get_blk(DeviceState *dev) |
| 1954 | { |
| 1955 | return M25P80(dev)->blk; |
| 1956 | } |