| 1 | /* |
| 2 | * CFI parallel flash with Intel command set emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Thorsten Zitterell |
| 5 | * Copyright (c) 2005 Jocelyn Mayer |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. |
| 23 | * Supported commands/modes are: |
| 24 | * - flash read |
| 25 | * - flash write |
| 26 | * - flash ID read |
| 27 | * - sector erase |
| 28 | * - CFI queries |
| 29 | * |
| 30 | * It does not support timings |
| 31 | * It does not support flash interleaving |
| 32 | * It does not implement software data protection as found in many real chips |
| 33 | * It does not implement erase suspend/resume commands |
| 34 | * It does not implement multiple sectors erase |
| 35 | * |
| 36 | * It does not implement much more ... |
| 37 | */ |
| 38 | |
| 39 | #include "qemu/osdep.h" |
| 40 | #include "hw/block/block.h" |
| 41 | #include "hw/block/flash.h" |
| 42 | #include "hw/core/qdev-properties.h" |
| 43 | #include "hw/core/qdev-properties-system.h" |
| 44 | #include "system/block-backend.h" |
| 45 | #include "qapi/error.h" |
| 46 | #include "qemu/error-report.h" |
| 47 | #include "qemu/bitops.h" |
| 48 | #include "qemu/host-utils.h" |
| 49 | #include "qemu/log.h" |
| 50 | #include "qemu/option.h" |
| 51 | #include "hw/core/sysbus.h" |
| 52 | #include "migration/vmstate.h" |
| 53 | #include "system/blockdev.h" |
| 54 | #include "system/runstate.h" |
| 55 | #include "trace.h" |
| 56 | |
| 57 | #define PFLASH_BE 0 |
| 58 | #define PFLASH_SECURE 1 |
| 59 | |
| 60 | struct PFlashCFI01 { |
| 61 | /*< private >*/ |
| 62 | SysBusDevice parent_obj; |
| 63 | /*< public >*/ |
| 64 | |
| 65 | BlockBackend *blk; |
| 66 | uint32_t nb_blocs; |
| 67 | uint64_t sector_len; |
| 68 | uint8_t bank_width; |
| 69 | uint8_t device_width; /* If 0, device width not specified. */ |
| 70 | uint8_t max_device_width; /* max device width in bytes */ |
| 71 | uint32_t features; |
| 72 | uint8_t wcycle; /* if 0, the flash is read normally */ |
| 73 | bool ro; |
| 74 | uint8_t cmd; |
| 75 | uint8_t status; |
| 76 | uint16_t ident0; |
| 77 | uint16_t ident1; |
| 78 | uint16_t ident2; |
| 79 | uint16_t ident3; |
| 80 | uint8_t cfi_table[0x52]; |
| 81 | uint64_t counter; |
| 82 | uint32_t writeblock_size; |
| 83 | MemoryRegion mem; |
| 84 | char *name; |
| 85 | void *storage; |
| 86 | VMChangeStateEntry *vmstate; |
| 87 | |
| 88 | /* block update buffer */ |
| 89 | unsigned char *blk_bytes; |
| 90 | uint32_t blk_offset; |
| 91 | }; |
| 92 | |
| 93 | static int pflash_post_load(void *opaque, int version_id); |
| 94 | |
| 95 | static bool pflash_blk_write_state_needed(void *opaque) |
| 96 | { |
| 97 | PFlashCFI01 *pfl = opaque; |
| 98 | |
| 99 | return (pfl->blk_offset != -1); |
| 100 | } |
| 101 | |
| 102 | static const VMStateDescription vmstate_pflash_blk_write = { |
| 103 | .name = "pflash_cfi01_blk_write", |
| 104 | .version_id = 1, |
| 105 | .minimum_version_id = 1, |
| 106 | .needed = pflash_blk_write_state_needed, |
| 107 | .fields = (const VMStateField[]) { |
| 108 | VMSTATE_VBUFFER_UINT32(blk_bytes, PFlashCFI01, 0, NULL, writeblock_size), |
| 109 | VMSTATE_UINT32(blk_offset, PFlashCFI01), |
| 110 | VMSTATE_END_OF_LIST() |
| 111 | } |
| 112 | }; |
| 113 | |
| 114 | static const VMStateDescription vmstate_pflash = { |
| 115 | .name = "pflash_cfi01", |
| 116 | .version_id = 1, |
| 117 | .minimum_version_id = 1, |
| 118 | .post_load = pflash_post_load, |
| 119 | .fields = (const VMStateField[]) { |
| 120 | VMSTATE_UINT8(wcycle, PFlashCFI01), |
| 121 | VMSTATE_UINT8(cmd, PFlashCFI01), |
| 122 | VMSTATE_UINT8(status, PFlashCFI01), |
| 123 | VMSTATE_UINT64(counter, PFlashCFI01), |
| 124 | VMSTATE_END_OF_LIST() |
| 125 | }, |
| 126 | .subsections = (const VMStateDescription * const []) { |
| 127 | &vmstate_pflash_blk_write, |
| 128 | NULL |
| 129 | } |
| 130 | }; |
| 131 | |
| 132 | /* |
| 133 | * Perform a CFI query based on the bank width of the flash. |
| 134 | * If this code is called we know we have a device_width set for |
| 135 | * this flash. |
| 136 | */ |
| 137 | static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset) |
| 138 | { |
| 139 | int i; |
| 140 | uint32_t resp = 0; |
| 141 | hwaddr boff; |
| 142 | |
| 143 | /* |
| 144 | * Adjust incoming offset to match expected device-width |
| 145 | * addressing. CFI query addresses are always specified in terms of |
| 146 | * the maximum supported width of the device. This means that x8 |
| 147 | * devices and x8/x16 devices in x8 mode behave differently. For |
| 148 | * devices that are not used at their max width, we will be |
| 149 | * provided with addresses that use higher address bits than |
| 150 | * expected (based on the max width), so we will shift them lower |
| 151 | * so that they will match the addresses used when |
| 152 | * device_width==max_device_width. |
| 153 | */ |
| 154 | boff = offset >> (ctz32(pfl->bank_width) + |
| 155 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); |
| 156 | |
| 157 | if (boff >= sizeof(pfl->cfi_table)) { |
| 158 | return 0; |
| 159 | } |
| 160 | /* |
| 161 | * Now we will construct the CFI response generated by a single |
| 162 | * device, then replicate that for all devices that make up the |
| 163 | * bus. For wide parts used in x8 mode, CFI query responses |
| 164 | * are different than native byte-wide parts. |
| 165 | */ |
| 166 | resp = pfl->cfi_table[boff]; |
| 167 | if (pfl->device_width != pfl->max_device_width) { |
| 168 | /* The only case currently supported is x8 mode for a |
| 169 | * wider part. |
| 170 | */ |
| 171 | if (pfl->device_width != 1 || pfl->bank_width > 4) { |
| 172 | trace_pflash_unsupported_device_configuration(pfl->name, |
| 173 | pfl->device_width, pfl->max_device_width); |
| 174 | return 0; |
| 175 | } |
| 176 | /* CFI query data is repeated, rather than zero padded for |
| 177 | * wide devices used in x8 mode. |
| 178 | */ |
| 179 | for (i = 1; i < pfl->max_device_width; i++) { |
| 180 | resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]); |
| 181 | } |
| 182 | } |
| 183 | /* Replicate responses for each device in bank. */ |
| 184 | if (pfl->device_width < pfl->bank_width) { |
| 185 | for (i = pfl->device_width; |
| 186 | i < pfl->bank_width; i += pfl->device_width) { |
| 187 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | return resp; |
| 192 | } |
| 193 | |
| 194 | |
| 195 | |
| 196 | /* Perform a device id query based on the bank width of the flash. */ |
| 197 | static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset) |
| 198 | { |
| 199 | int i; |
| 200 | uint32_t resp; |
| 201 | hwaddr boff; |
| 202 | |
| 203 | /* |
| 204 | * Adjust incoming offset to match expected device-width |
| 205 | * addressing. Device ID read addresses are always specified in |
| 206 | * terms of the maximum supported width of the device. This means |
| 207 | * that x8 devices and x8/x16 devices in x8 mode behave |
| 208 | * differently. For devices that are not used at their max width, |
| 209 | * we will be provided with addresses that use higher address bits |
| 210 | * than expected (based on the max width), so we will shift them |
| 211 | * lower so that they will match the addresses used when |
| 212 | * device_width==max_device_width. |
| 213 | */ |
| 214 | boff = offset >> (ctz32(pfl->bank_width) + |
| 215 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); |
| 216 | |
| 217 | /* |
| 218 | * Mask off upper bits which may be used in to query block |
| 219 | * or sector lock status at other addresses. |
| 220 | * Offsets 2/3 are block lock status, is not emulated. |
| 221 | */ |
| 222 | switch (boff & 0xFF) { |
| 223 | case 0: |
| 224 | resp = pfl->ident0; |
| 225 | trace_pflash_manufacturer_id(pfl->name, resp); |
| 226 | break; |
| 227 | case 1: |
| 228 | resp = pfl->ident1; |
| 229 | trace_pflash_device_id(pfl->name, resp); |
| 230 | break; |
| 231 | default: |
| 232 | trace_pflash_device_info(pfl->name, offset); |
| 233 | return 0; |
| 234 | } |
| 235 | /* Replicate responses for each device in bank. */ |
| 236 | if (pfl->device_width < pfl->bank_width) { |
| 237 | for (i = pfl->device_width; |
| 238 | i < pfl->bank_width; i += pfl->device_width) { |
| 239 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | return resp; |
| 244 | } |
| 245 | |
| 246 | static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset, |
| 247 | int width, int be) |
| 248 | { |
| 249 | uint8_t *p; |
| 250 | uint32_t ret; |
| 251 | |
| 252 | p = pfl->storage; |
| 253 | if (be) { |
| 254 | ret = ldn_be_p(p + offset, width); |
| 255 | } else { |
| 256 | ret = ldn_le_p(p + offset, width); |
| 257 | } |
| 258 | trace_pflash_data_read(pfl->name, offset, width, ret); |
| 259 | return ret; |
| 260 | } |
| 261 | |
| 262 | static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset, |
| 263 | int width, int be) |
| 264 | { |
| 265 | hwaddr boff; |
| 266 | uint32_t ret; |
| 267 | |
| 268 | ret = -1; |
| 269 | switch (pfl->cmd) { |
| 270 | default: |
| 271 | /* This should never happen : reset state & treat it as a read */ |
| 272 | trace_pflash_read_unknown_state(pfl->name, pfl->cmd); |
| 273 | pfl->wcycle = 0; |
| 274 | /* |
| 275 | * The command 0x00 is not assigned by the CFI open standard, |
| 276 | * but QEMU historically uses it for the READ_ARRAY command (0xff). |
| 277 | */ |
| 278 | pfl->cmd = 0x00; |
| 279 | /* fall through to read code */ |
| 280 | case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */ |
| 281 | /* Flash area read */ |
| 282 | ret = pflash_data_read(pfl, offset, width, be); |
| 283 | break; |
| 284 | case 0x10: /* Single byte program */ |
| 285 | case 0x20: /* Block erase */ |
| 286 | case 0x28: /* Block erase */ |
| 287 | case 0x40: /* single byte program */ |
| 288 | case 0x50: /* Clear status register */ |
| 289 | case 0x60: /* Block /un)lock */ |
| 290 | case 0x70: /* Status Register */ |
| 291 | case 0xe8: /* Write block */ |
| 292 | /* |
| 293 | * Status register read. Return status from each device in |
| 294 | * bank. |
| 295 | */ |
| 296 | ret = pfl->status; |
| 297 | if (pfl->device_width && width > pfl->device_width) { |
| 298 | int shift = pfl->device_width * 8; |
| 299 | while (shift + pfl->device_width * 8 <= width * 8) { |
| 300 | ret |= pfl->status << shift; |
| 301 | shift += pfl->device_width * 8; |
| 302 | } |
| 303 | } else if (!pfl->device_width && width > 2) { |
| 304 | /* |
| 305 | * Handle 32 bit flash cases where device width is not |
| 306 | * set. (Existing behavior before device width added.) |
| 307 | */ |
| 308 | ret |= pfl->status << 16; |
| 309 | } |
| 310 | trace_pflash_read_status(pfl->name, ret); |
| 311 | break; |
| 312 | case 0x90: |
| 313 | if (!pfl->device_width) { |
| 314 | /* Preserve old behavior if device width not specified */ |
| 315 | boff = offset & 0xFF; |
| 316 | if (pfl->bank_width == 2) { |
| 317 | boff = boff >> 1; |
| 318 | } else if (pfl->bank_width == 4) { |
| 319 | boff = boff >> 2; |
| 320 | } |
| 321 | |
| 322 | switch (boff) { |
| 323 | case 0: |
| 324 | ret = pfl->ident0 << 8 | pfl->ident1; |
| 325 | trace_pflash_manufacturer_id(pfl->name, ret); |
| 326 | break; |
| 327 | case 1: |
| 328 | ret = pfl->ident2 << 8 | pfl->ident3; |
| 329 | trace_pflash_device_id(pfl->name, ret); |
| 330 | break; |
| 331 | default: |
| 332 | trace_pflash_device_info(pfl->name, boff); |
| 333 | ret = 0; |
| 334 | break; |
| 335 | } |
| 336 | } else { |
| 337 | /* |
| 338 | * If we have a read larger than the bank_width, combine multiple |
| 339 | * manufacturer/device ID queries into a single response. |
| 340 | */ |
| 341 | int i; |
| 342 | for (i = 0; i < width; i += pfl->bank_width) { |
| 343 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, |
| 344 | pflash_devid_query(pfl, |
| 345 | offset + i * pfl->bank_width)); |
| 346 | } |
| 347 | } |
| 348 | break; |
| 349 | case 0x98: /* Query mode */ |
| 350 | if (!pfl->device_width) { |
| 351 | /* Preserve old behavior if device width not specified */ |
| 352 | boff = offset & 0xFF; |
| 353 | if (pfl->bank_width == 2) { |
| 354 | boff = boff >> 1; |
| 355 | } else if (pfl->bank_width == 4) { |
| 356 | boff = boff >> 2; |
| 357 | } |
| 358 | |
| 359 | if (boff < sizeof(pfl->cfi_table)) { |
| 360 | ret = pfl->cfi_table[boff]; |
| 361 | } else { |
| 362 | ret = 0; |
| 363 | } |
| 364 | } else { |
| 365 | /* |
| 366 | * If we have a read larger than the bank_width, combine multiple |
| 367 | * CFI queries into a single response. |
| 368 | */ |
| 369 | int i; |
| 370 | for (i = 0; i < width; i += pfl->bank_width) { |
| 371 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, |
| 372 | pflash_cfi_query(pfl, |
| 373 | offset + i * pfl->bank_width)); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | break; |
| 378 | } |
| 379 | trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle); |
| 380 | |
| 381 | return ret; |
| 382 | } |
| 383 | |
| 384 | /* update flash content on disk */ |
| 385 | static void pflash_update(PFlashCFI01 *pfl, int offset, |
| 386 | int size) |
| 387 | { |
| 388 | int offset_end; |
| 389 | int ret; |
| 390 | if (pfl->blk) { |
| 391 | offset_end = offset + size; |
| 392 | /* widen to sector boundaries */ |
| 393 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); |
| 394 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); |
| 395 | ret = blk_pwrite(pfl->blk, offset, offset_end - offset, |
| 396 | pfl->storage + offset, 0); |
| 397 | if (ret < 0) { |
| 398 | /* TODO set error bit in status */ |
| 399 | error_report("Could not update PFLASH: %s", strerror(-ret)); |
| 400 | } |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | /* copy current flash content to block update buffer */ |
| 405 | static void pflash_blk_write_start(PFlashCFI01 *pfl, hwaddr offset) |
| 406 | { |
| 407 | hwaddr mask = ~(pfl->writeblock_size - 1); |
| 408 | |
| 409 | trace_pflash_write_block_start(pfl->name, pfl->counter); |
| 410 | pfl->blk_offset = offset & mask; |
| 411 | memcpy(pfl->blk_bytes, pfl->storage + pfl->blk_offset, |
| 412 | pfl->writeblock_size); |
| 413 | } |
| 414 | |
| 415 | /* commit block update buffer changes */ |
| 416 | static void pflash_blk_write_flush(PFlashCFI01 *pfl) |
| 417 | { |
| 418 | g_assert(pfl->blk_offset != -1); |
| 419 | trace_pflash_write_block_flush(pfl->name); |
| 420 | memcpy(pfl->storage + pfl->blk_offset, pfl->blk_bytes, |
| 421 | pfl->writeblock_size); |
| 422 | pflash_update(pfl, pfl->blk_offset, pfl->writeblock_size); |
| 423 | pfl->blk_offset = -1; |
| 424 | } |
| 425 | |
| 426 | /* discard block update buffer changes */ |
| 427 | static void pflash_blk_write_abort(PFlashCFI01 *pfl) |
| 428 | { |
| 429 | trace_pflash_write_block_abort(pfl->name); |
| 430 | pfl->blk_offset = -1; |
| 431 | } |
| 432 | |
| 433 | static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, |
| 434 | uint32_t value, int width, int be) |
| 435 | { |
| 436 | uint8_t *p; |
| 437 | |
| 438 | if (pfl->blk_offset != -1) { |
| 439 | /* block write: redirect writes to block update buffer */ |
| 440 | if ((offset < pfl->blk_offset) || |
| 441 | (offset + width > pfl->blk_offset + pfl->writeblock_size)) { |
| 442 | pfl->status |= 0x10; /* Programming error */ |
| 443 | return; |
| 444 | } |
| 445 | trace_pflash_data_write_block(pfl->name, offset, width, value, |
| 446 | pfl->counter); |
| 447 | p = pfl->blk_bytes + (offset - pfl->blk_offset); |
| 448 | } else { |
| 449 | /* write directly to storage */ |
| 450 | trace_pflash_data_write(pfl->name, offset, width, value); |
| 451 | p = pfl->storage + offset; |
| 452 | } |
| 453 | |
| 454 | if (be) { |
| 455 | stn_be_p(p, width, value); |
| 456 | } else { |
| 457 | stn_le_p(p, width, value); |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, |
| 462 | uint32_t value, int width, int be) |
| 463 | { |
| 464 | uint8_t *p; |
| 465 | uint8_t cmd; |
| 466 | |
| 467 | cmd = value; |
| 468 | |
| 469 | trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle); |
| 470 | if (!pfl->wcycle) { |
| 471 | /* Set the device in I/O access mode */ |
| 472 | memory_region_rom_device_set_romd(&pfl->mem, false); |
| 473 | } |
| 474 | |
| 475 | switch (pfl->wcycle) { |
| 476 | case 0: |
| 477 | /* read mode */ |
| 478 | switch (cmd) { |
| 479 | case 0x00: /* This model reset value for READ_ARRAY (not CFI) */ |
| 480 | goto mode_read_array; |
| 481 | case 0x10: /* Single Byte Program */ |
| 482 | case 0x40: /* Single Byte Program */ |
| 483 | trace_pflash_write(pfl->name, "single byte program (0)"); |
| 484 | break; |
| 485 | case 0x20: /* Block erase */ |
| 486 | p = pfl->storage; |
| 487 | offset &= ~(pfl->sector_len - 1); |
| 488 | |
| 489 | trace_pflash_write_block_erase(pfl->name, offset, pfl->sector_len); |
| 490 | |
| 491 | if (!pfl->ro) { |
| 492 | memset(p + offset, 0xff, pfl->sector_len); |
| 493 | pflash_update(pfl, offset, pfl->sector_len); |
| 494 | } else { |
| 495 | pfl->status |= 0x20; /* Block erase error */ |
| 496 | } |
| 497 | pfl->status |= 0x80; /* Ready! */ |
| 498 | break; |
| 499 | case 0x50: /* Clear status bits */ |
| 500 | trace_pflash_write(pfl->name, "clear status bits"); |
| 501 | pfl->status = 0x0; |
| 502 | goto mode_read_array; |
| 503 | case 0x60: /* Block (un)lock */ |
| 504 | trace_pflash_write(pfl->name, "block unlock"); |
| 505 | break; |
| 506 | case 0x70: /* Status Register */ |
| 507 | trace_pflash_write(pfl->name, "read status register"); |
| 508 | pfl->cmd = cmd; |
| 509 | return; |
| 510 | case 0x90: /* Read Device ID */ |
| 511 | trace_pflash_write(pfl->name, "read device information"); |
| 512 | pfl->cmd = cmd; |
| 513 | return; |
| 514 | case 0x98: /* CFI query */ |
| 515 | trace_pflash_write(pfl->name, "CFI query"); |
| 516 | break; |
| 517 | case 0xe8: /* Write to buffer */ |
| 518 | trace_pflash_write(pfl->name, "write to buffer"); |
| 519 | pfl->status |= 0x80; /* Ready! */ |
| 520 | break; |
| 521 | case 0xf0: /* Probe for AMD flash */ |
| 522 | trace_pflash_write(pfl->name, "probe for AMD flash"); |
| 523 | goto mode_read_array; |
| 524 | case 0xff: /* Read Array */ |
| 525 | trace_pflash_write(pfl->name, "read array mode"); |
| 526 | goto mode_read_array; |
| 527 | default: |
| 528 | goto error_flash; |
| 529 | } |
| 530 | pfl->wcycle++; |
| 531 | pfl->cmd = cmd; |
| 532 | break; |
| 533 | case 1: |
| 534 | switch (pfl->cmd) { |
| 535 | case 0x10: /* Single Byte Program */ |
| 536 | case 0x40: /* Single Byte Program */ |
| 537 | trace_pflash_write(pfl->name, "single byte program (1)"); |
| 538 | if (!pfl->ro) { |
| 539 | pflash_data_write(pfl, offset, value, width, be); |
| 540 | pflash_update(pfl, offset, width); |
| 541 | } else { |
| 542 | pfl->status |= 0x10; /* Programming error */ |
| 543 | } |
| 544 | pfl->status |= 0x80; /* Ready! */ |
| 545 | pfl->wcycle = 0; |
| 546 | break; |
| 547 | case 0x20: /* Block erase */ |
| 548 | case 0x28: |
| 549 | if (cmd == 0xd0) { /* confirm */ |
| 550 | pfl->wcycle = 0; |
| 551 | pfl->status |= 0x80; |
| 552 | } else if (cmd == 0xff) { /* Read Array */ |
| 553 | goto mode_read_array; |
| 554 | } else |
| 555 | goto error_flash; |
| 556 | |
| 557 | break; |
| 558 | case 0xe8: |
| 559 | /* |
| 560 | * Mask writeblock size based on device width, or bank width if |
| 561 | * device width not specified. |
| 562 | */ |
| 563 | /* FIXME check @offset, @width */ |
| 564 | if (pfl->device_width) { |
| 565 | value = extract32(value, 0, pfl->device_width * 8); |
| 566 | } else { |
| 567 | value = extract32(value, 0, pfl->bank_width * 8); |
| 568 | } |
| 569 | pfl->counter = value; |
| 570 | pfl->wcycle++; |
| 571 | break; |
| 572 | case 0x60: |
| 573 | if (cmd == 0xd0) { |
| 574 | pfl->wcycle = 0; |
| 575 | pfl->status |= 0x80; |
| 576 | } else if (cmd == 0x01) { |
| 577 | pfl->wcycle = 0; |
| 578 | pfl->status |= 0x80; |
| 579 | } else if (cmd == 0xff) { /* Read Array */ |
| 580 | goto mode_read_array; |
| 581 | } else { |
| 582 | trace_pflash_write(pfl->name, "unknown (un)locking command"); |
| 583 | goto mode_read_array; |
| 584 | } |
| 585 | break; |
| 586 | case 0x98: |
| 587 | if (cmd == 0xff) { /* Read Array */ |
| 588 | goto mode_read_array; |
| 589 | } else { |
| 590 | trace_pflash_write(pfl->name, "leaving query mode"); |
| 591 | } |
| 592 | break; |
| 593 | default: |
| 594 | goto error_flash; |
| 595 | } |
| 596 | break; |
| 597 | case 2: |
| 598 | switch (pfl->cmd) { |
| 599 | case 0xe8: /* Block write */ |
| 600 | /* FIXME check @offset, @width */ |
| 601 | if (pfl->blk_offset == -1 && pfl->counter) { |
| 602 | pflash_blk_write_start(pfl, offset); |
| 603 | } |
| 604 | if (!pfl->ro && (pfl->blk_offset != -1)) { |
| 605 | pflash_data_write(pfl, offset, value, width, be); |
| 606 | } else { |
| 607 | pfl->status |= 0x10; /* Programming error */ |
| 608 | } |
| 609 | |
| 610 | pfl->status |= 0x80; |
| 611 | |
| 612 | if (!pfl->counter) { |
| 613 | trace_pflash_write(pfl->name, "block write finished"); |
| 614 | pfl->wcycle++; |
| 615 | break; |
| 616 | } |
| 617 | |
| 618 | pfl->counter--; |
| 619 | break; |
| 620 | default: |
| 621 | goto error_flash; |
| 622 | } |
| 623 | break; |
| 624 | case 3: /* Confirm mode */ |
| 625 | switch (pfl->cmd) { |
| 626 | case 0xe8: /* Block write */ |
| 627 | if ((cmd == 0xd0) && !(pfl->status & 0x10)) { |
| 628 | pflash_blk_write_flush(pfl); |
| 629 | pfl->wcycle = 0; |
| 630 | pfl->status |= 0x80; |
| 631 | } else { |
| 632 | pflash_blk_write_abort(pfl); |
| 633 | goto mode_read_array; |
| 634 | } |
| 635 | break; |
| 636 | default: |
| 637 | pflash_blk_write_abort(pfl); |
| 638 | goto error_flash; |
| 639 | } |
| 640 | break; |
| 641 | default: |
| 642 | /* Should never happen */ |
| 643 | trace_pflash_write(pfl->name, "invalid write state"); |
| 644 | goto mode_read_array; |
| 645 | } |
| 646 | return; |
| 647 | |
| 648 | error_flash: |
| 649 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " |
| 650 | "(offset " HWADDR_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" |
| 651 | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); |
| 652 | |
| 653 | mode_read_array: |
| 654 | trace_pflash_mode_read_array(pfl->name); |
| 655 | memory_region_rom_device_set_romd(&pfl->mem, true); |
| 656 | pfl->wcycle = 0; |
| 657 | pfl->cmd = 0x00; /* This model reset value for READ_ARRAY (not CFI) */ |
| 658 | } |
| 659 | |
| 660 | |
| 661 | static MemTxResult pflash_mem_read_with_attrs(void *opaque, hwaddr addr, uint64_t *value, |
| 662 | unsigned len, MemTxAttrs attrs) |
| 663 | { |
| 664 | PFlashCFI01 *pfl = opaque; |
| 665 | bool be = !!(pfl->features & (1 << PFLASH_BE)); |
| 666 | |
| 667 | if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) { |
| 668 | *value = pflash_data_read(opaque, addr, len, be); |
| 669 | } else { |
| 670 | *value = pflash_read(opaque, addr, len, be); |
| 671 | } |
| 672 | return MEMTX_OK; |
| 673 | } |
| 674 | |
| 675 | static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64_t value, |
| 676 | unsigned len, MemTxAttrs attrs) |
| 677 | { |
| 678 | PFlashCFI01 *pfl = opaque; |
| 679 | bool be = !!(pfl->features & (1 << PFLASH_BE)); |
| 680 | |
| 681 | if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) { |
| 682 | return MEMTX_ERROR; |
| 683 | } else { |
| 684 | pflash_write(opaque, addr, value, len, be); |
| 685 | return MEMTX_OK; |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | static const MemoryRegionOps pflash_cfi01_ops = { |
| 690 | .read_with_attrs = pflash_mem_read_with_attrs, |
| 691 | .write_with_attrs = pflash_mem_write_with_attrs, |
| 692 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 693 | }; |
| 694 | |
| 695 | static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl) |
| 696 | { |
| 697 | uint64_t blocks_per_device, sector_len_per_device, device_len; |
| 698 | int num_devices; |
| 699 | |
| 700 | /* |
| 701 | * These are only used to expose the parameters of each device |
| 702 | * in the cfi_table[]. |
| 703 | */ |
| 704 | num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1; |
| 705 | blocks_per_device = pfl->nb_blocs; |
| 706 | sector_len_per_device = pfl->sector_len / num_devices; |
| 707 | device_len = sector_len_per_device * blocks_per_device; |
| 708 | |
| 709 | /* Hardcoded CFI table */ |
| 710 | /* Standard "QRY" string */ |
| 711 | pfl->cfi_table[0x10] = 'Q'; |
| 712 | pfl->cfi_table[0x11] = 'R'; |
| 713 | pfl->cfi_table[0x12] = 'Y'; |
| 714 | /* Command set (Intel) */ |
| 715 | pfl->cfi_table[0x13] = 0x01; |
| 716 | pfl->cfi_table[0x14] = 0x00; |
| 717 | /* Primary extended table address (none) */ |
| 718 | pfl->cfi_table[0x15] = 0x31; |
| 719 | pfl->cfi_table[0x16] = 0x00; |
| 720 | /* Alternate command set (none) */ |
| 721 | pfl->cfi_table[0x17] = 0x00; |
| 722 | pfl->cfi_table[0x18] = 0x00; |
| 723 | /* Alternate extended table (none) */ |
| 724 | pfl->cfi_table[0x19] = 0x00; |
| 725 | pfl->cfi_table[0x1A] = 0x00; |
| 726 | /* Vcc min */ |
| 727 | pfl->cfi_table[0x1B] = 0x45; |
| 728 | /* Vcc max */ |
| 729 | pfl->cfi_table[0x1C] = 0x55; |
| 730 | /* Vpp min (no Vpp pin) */ |
| 731 | pfl->cfi_table[0x1D] = 0x00; |
| 732 | /* Vpp max (no Vpp pin) */ |
| 733 | pfl->cfi_table[0x1E] = 0x00; |
| 734 | /* Reserved */ |
| 735 | pfl->cfi_table[0x1F] = 0x07; |
| 736 | /* Timeout for min size buffer write */ |
| 737 | pfl->cfi_table[0x20] = 0x07; |
| 738 | /* Typical timeout for block erase */ |
| 739 | pfl->cfi_table[0x21] = 0x0a; |
| 740 | /* Typical timeout for full chip erase (4096 ms) */ |
| 741 | pfl->cfi_table[0x22] = 0x00; |
| 742 | /* Reserved */ |
| 743 | pfl->cfi_table[0x23] = 0x04; |
| 744 | /* Max timeout for buffer write */ |
| 745 | pfl->cfi_table[0x24] = 0x04; |
| 746 | /* Max timeout for block erase */ |
| 747 | pfl->cfi_table[0x25] = 0x04; |
| 748 | /* Max timeout for chip erase */ |
| 749 | pfl->cfi_table[0x26] = 0x00; |
| 750 | /* Device size */ |
| 751 | pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */ |
| 752 | /* Flash device interface (8 & 16 bits) */ |
| 753 | pfl->cfi_table[0x28] = 0x02; |
| 754 | pfl->cfi_table[0x29] = 0x00; |
| 755 | /* Max number of bytes in multi-bytes write */ |
| 756 | if (pfl->bank_width == 1) { |
| 757 | pfl->cfi_table[0x2A] = 0x08; |
| 758 | } else { |
| 759 | pfl->cfi_table[0x2A] = 0x0B; |
| 760 | } |
| 761 | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
| 762 | if (num_devices > 1) { |
| 763 | pfl->writeblock_size *= num_devices; |
| 764 | } |
| 765 | |
| 766 | pfl->cfi_table[0x2B] = 0x00; |
| 767 | /* Number of erase block regions (uniform) */ |
| 768 | pfl->cfi_table[0x2C] = 0x01; |
| 769 | /* Erase block region 1 */ |
| 770 | pfl->cfi_table[0x2D] = blocks_per_device - 1; |
| 771 | pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8; |
| 772 | pfl->cfi_table[0x2F] = sector_len_per_device >> 8; |
| 773 | pfl->cfi_table[0x30] = sector_len_per_device >> 16; |
| 774 | |
| 775 | /* Extended */ |
| 776 | pfl->cfi_table[0x31] = 'P'; |
| 777 | pfl->cfi_table[0x32] = 'R'; |
| 778 | pfl->cfi_table[0x33] = 'I'; |
| 779 | |
| 780 | pfl->cfi_table[0x34] = '1'; |
| 781 | pfl->cfi_table[0x35] = '0'; |
| 782 | |
| 783 | pfl->cfi_table[0x36] = 0x00; |
| 784 | pfl->cfi_table[0x37] = 0x00; |
| 785 | pfl->cfi_table[0x38] = 0x00; |
| 786 | pfl->cfi_table[0x39] = 0x00; |
| 787 | |
| 788 | pfl->cfi_table[0x3a] = 0x00; |
| 789 | |
| 790 | pfl->cfi_table[0x3b] = 0x00; |
| 791 | pfl->cfi_table[0x3c] = 0x00; |
| 792 | |
| 793 | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
| 794 | } |
| 795 | |
| 796 | static void pflash_cfi01_realize(DeviceState *dev, Error **errp) |
| 797 | { |
| 798 | ERRP_GUARD(); |
| 799 | PFlashCFI01 *pfl = PFLASH_CFI01(dev); |
| 800 | uint64_t total_len; |
| 801 | int ret; |
| 802 | |
| 803 | if (pfl->sector_len == 0) { |
| 804 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); |
| 805 | return; |
| 806 | } |
| 807 | if (pfl->nb_blocs == 0) { |
| 808 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); |
| 809 | return; |
| 810 | } |
| 811 | if (pfl->name == NULL) { |
| 812 | error_setg(errp, "attribute \"name\" not specified."); |
| 813 | return; |
| 814 | } |
| 815 | |
| 816 | total_len = pfl->sector_len * pfl->nb_blocs; |
| 817 | |
| 818 | memory_region_init_rom_device( |
| 819 | &pfl->mem, OBJECT(dev), |
| 820 | &pflash_cfi01_ops, |
| 821 | pfl, |
| 822 | pfl->name, total_len, errp); |
| 823 | if (*errp) { |
| 824 | return; |
| 825 | } |
| 826 | |
| 827 | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
| 828 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
| 829 | |
| 830 | if (pfl->blk) { |
| 831 | uint64_t perm; |
| 832 | pfl->ro = !blk_supports_write_perm(pfl->blk); |
| 833 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); |
| 834 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); |
| 835 | if (ret < 0) { |
| 836 | return; |
| 837 | } |
| 838 | } else { |
| 839 | pfl->ro = false; |
| 840 | } |
| 841 | |
| 842 | if (pfl->blk) { |
| 843 | if (!blk_check_size_and_read_all(pfl->blk, dev, pfl->storage, |
| 844 | total_len, errp)) { |
| 845 | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
| 846 | return; |
| 847 | } |
| 848 | } |
| 849 | |
| 850 | /* |
| 851 | * Default to devices being used at their maximum device width. This was |
| 852 | * assumed before the device_width support was added. |
| 853 | */ |
| 854 | if (!pfl->max_device_width) { |
| 855 | pfl->max_device_width = pfl->device_width; |
| 856 | } |
| 857 | |
| 858 | pfl->wcycle = 0; |
| 859 | /* |
| 860 | * The command 0x00 is not assigned by the CFI open standard, |
| 861 | * but QEMU historically uses it for the READ_ARRAY command (0xff). |
| 862 | */ |
| 863 | pfl->cmd = 0x00; |
| 864 | pfl->status = 0x80; /* WSM ready */ |
| 865 | pflash_cfi01_fill_cfi_table(pfl); |
| 866 | |
| 867 | pfl->blk_bytes = g_malloc(pfl->writeblock_size); |
| 868 | pfl->blk_offset = -1; |
| 869 | } |
| 870 | |
| 871 | static void pflash_cfi01_system_reset(DeviceState *dev) |
| 872 | { |
| 873 | PFlashCFI01 *pfl = PFLASH_CFI01(dev); |
| 874 | |
| 875 | trace_pflash_reset(pfl->name); |
| 876 | /* |
| 877 | * The command 0x00 is not assigned by the CFI open standard, |
| 878 | * but QEMU historically uses it for the READ_ARRAY command (0xff). |
| 879 | */ |
| 880 | pfl->cmd = 0x00; |
| 881 | pfl->wcycle = 0; |
| 882 | memory_region_rom_device_set_romd(&pfl->mem, true); |
| 883 | /* |
| 884 | * The WSM ready timer occurs at most 150ns after system reset. |
| 885 | * This model deliberately ignores this delay. |
| 886 | */ |
| 887 | pfl->status = 0x80; |
| 888 | |
| 889 | pfl->blk_offset = -1; |
| 890 | } |
| 891 | |
| 892 | static const Property pflash_cfi01_properties[] = { |
| 893 | DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk), |
| 894 | /* num-blocks is the number of blocks actually visible to the guest, |
| 895 | * ie the total size of the device divided by the sector length. |
| 896 | * If we're emulating flash devices wired in parallel the actual |
| 897 | * number of blocks per individual device will differ. |
| 898 | */ |
| 899 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0), |
| 900 | DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0), |
| 901 | /* width here is the overall width of this QEMU device in bytes. |
| 902 | * The QEMU device may be emulating a number of flash devices |
| 903 | * wired up in parallel; the width of each individual flash |
| 904 | * device should be specified via device-width. If the individual |
| 905 | * devices have a maximum width which is greater than the width |
| 906 | * they are being used for, this maximum width should be set via |
| 907 | * max-device-width (which otherwise defaults to device-width). |
| 908 | * So for instance a 32-bit wide QEMU flash device made from four |
| 909 | * 16-bit flash devices used in 8-bit wide mode would be configured |
| 910 | * with width = 4, device-width = 1, max-device-width = 2. |
| 911 | * |
| 912 | * If device-width is not specified we default to backwards |
| 913 | * compatible behaviour which is a bad emulation of two |
| 914 | * 16 bit devices making up a 32 bit wide QEMU device. This |
| 915 | * is deprecated for new uses of this device. |
| 916 | */ |
| 917 | DEFINE_PROP_UINT8("width", PFlashCFI01, bank_width, 0), |
| 918 | DEFINE_PROP_UINT8("device-width", PFlashCFI01, device_width, 0), |
| 919 | DEFINE_PROP_UINT8("max-device-width", PFlashCFI01, max_device_width, 0), |
| 920 | DEFINE_PROP_BIT("big-endian", PFlashCFI01, features, PFLASH_BE, 0), |
| 921 | DEFINE_PROP_BIT("secure", PFlashCFI01, features, PFLASH_SECURE, 0), |
| 922 | DEFINE_PROP_UINT16("id0", PFlashCFI01, ident0, 0), |
| 923 | DEFINE_PROP_UINT16("id1", PFlashCFI01, ident1, 0), |
| 924 | DEFINE_PROP_UINT16("id2", PFlashCFI01, ident2, 0), |
| 925 | DEFINE_PROP_UINT16("id3", PFlashCFI01, ident3, 0), |
| 926 | DEFINE_PROP_STRING("name", PFlashCFI01, name), |
| 927 | }; |
| 928 | |
| 929 | static void pflash_cfi01_class_init(ObjectClass *klass, const void *data) |
| 930 | { |
| 931 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 932 | |
| 933 | device_class_set_legacy_reset(dc, pflash_cfi01_system_reset); |
| 934 | dc->realize = pflash_cfi01_realize; |
| 935 | device_class_set_props(dc, pflash_cfi01_properties); |
| 936 | dc->vmsd = &vmstate_pflash; |
| 937 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 938 | } |
| 939 | |
| 940 | static const TypeInfo pflash_cfi01_types[] = { |
| 941 | { |
| 942 | .name = TYPE_PFLASH_CFI01, |
| 943 | .parent = TYPE_SYS_BUS_DEVICE, |
| 944 | .instance_size = sizeof(PFlashCFI01), |
| 945 | .class_init = pflash_cfi01_class_init, |
| 946 | }, |
| 947 | }; |
| 948 | |
| 949 | DEFINE_TYPES(pflash_cfi01_types) |
| 950 | |
| 951 | PFlashCFI01 *pflash_cfi01_register(hwaddr base, |
| 952 | const char *name, |
| 953 | hwaddr size, |
| 954 | BlockBackend *blk, |
| 955 | uint32_t sector_len, |
| 956 | int bank_width, |
| 957 | uint16_t id0, uint16_t id1, |
| 958 | uint16_t id2, uint16_t id3, |
| 959 | int be) |
| 960 | { |
| 961 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 962 | |
| 963 | if (blk) { |
| 964 | qdev_prop_set_drive(dev, "drive", blk); |
| 965 | } |
| 966 | assert(QEMU_IS_ALIGNED(size, sector_len)); |
| 967 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); |
| 968 | qdev_prop_set_uint64(dev, "sector-length", sector_len); |
| 969 | qdev_prop_set_uint8(dev, "width", bank_width); |
| 970 | qdev_prop_set_bit(dev, "big-endian", !!be); |
| 971 | qdev_prop_set_uint16(dev, "id0", id0); |
| 972 | qdev_prop_set_uint16(dev, "id1", id1); |
| 973 | qdev_prop_set_uint16(dev, "id2", id2); |
| 974 | qdev_prop_set_uint16(dev, "id3", id3); |
| 975 | qdev_prop_set_string(dev, "name", name); |
| 976 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 977 | |
| 978 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 979 | return PFLASH_CFI01(dev); |
| 980 | } |
| 981 | |
| 982 | BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl) |
| 983 | { |
| 984 | return fl->blk; |
| 985 | } |
| 986 | |
| 987 | MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl) |
| 988 | { |
| 989 | return &fl->mem; |
| 990 | } |
| 991 | |
| 992 | /* |
| 993 | * Handle -drive if=pflash for machines that use properties. |
| 994 | * If @dinfo is null, do nothing. |
| 995 | * Else if @fl's property "drive" is already set, fatal error. |
| 996 | * Else set it to the BlockBackend with @dinfo. |
| 997 | */ |
| 998 | void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) |
| 999 | { |
| 1000 | Location loc; |
| 1001 | |
| 1002 | if (!dinfo) { |
| 1003 | return; |
| 1004 | } |
| 1005 | |
| 1006 | loc_push_none(&loc); |
| 1007 | qemu_opts_loc_restore(dinfo->opts); |
| 1008 | if (fl->blk) { |
| 1009 | error_report("clashes with -machine"); |
| 1010 | exit(1); |
| 1011 | } |
| 1012 | qdev_prop_set_drive_err(DEVICE(fl), "drive", blk_by_legacy_dinfo(dinfo), |
| 1013 | &error_fatal); |
| 1014 | loc_pop(&loc); |
| 1015 | } |
| 1016 | |
| 1017 | static void postload_update_cb(void *opaque, bool running, RunState state) |
| 1018 | { |
| 1019 | PFlashCFI01 *pfl = opaque; |
| 1020 | |
| 1021 | /* This is called after bdrv_activate_all. */ |
| 1022 | qemu_del_vm_change_state_handler(pfl->vmstate); |
| 1023 | pfl->vmstate = NULL; |
| 1024 | |
| 1025 | trace_pflash_postload_cb(pfl->name); |
| 1026 | pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs); |
| 1027 | } |
| 1028 | |
| 1029 | static int pflash_post_load(void *opaque, int version_id) |
| 1030 | { |
| 1031 | PFlashCFI01 *pfl = opaque; |
| 1032 | |
| 1033 | /* |
| 1034 | * ROMD mode is not in the VMState; derive it from the migrated |
| 1035 | * cmd and wcycle. Only (wcycle == 0, cmd == 0x00) is read-array. |
| 1036 | */ |
| 1037 | if (pfl->wcycle == 0 && pfl->cmd == 0x00) { |
| 1038 | memory_region_rom_device_set_romd(&pfl->mem, true); |
| 1039 | } else { |
| 1040 | memory_region_rom_device_set_romd(&pfl->mem, false); |
| 1041 | } |
| 1042 | |
| 1043 | if (!pfl->ro) { |
| 1044 | pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, |
| 1045 | pfl); |
| 1046 | } |
| 1047 | return 0; |
| 1048 | } |