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1 /*
2 * ARM CMSDK APB UART emulation
3 *
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /* This is a model of the "APB UART" which is part of the Cortex-M
13 * System Design Kit (CMSDK) and documented in the Cortex-M System
14 * Design Kit Technical Reference Manual (ARM DDI0479C):
15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "qapi/error.h"
22 #include "trace.h"
23 #include "hw/core/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "hw/core/registerfields.h"
26 #include "chardev/char-fe.h"
27 #include "chardev/char-serial.h"
28 #include "hw/char/cmsdk-apb-uart.h"
29 #include "hw/core/irq.h"
30 #include "hw/core/qdev-properties-system.h"
31
32 REG32(DATA, 0)
33 REG32(STATE, 4)
34 FIELD(STATE, TXFULL, 0, 1)
35 FIELD(STATE, RXFULL, 1, 1)
36 FIELD(STATE, TXOVERRUN, 2, 1)
37 FIELD(STATE, RXOVERRUN, 3, 1)
38 REG32(CTRL, 8)
39 FIELD(CTRL, TX_EN, 0, 1)
40 FIELD(CTRL, RX_EN, 1, 1)
41 FIELD(CTRL, TX_INTEN, 2, 1)
42 FIELD(CTRL, RX_INTEN, 3, 1)
43 FIELD(CTRL, TXO_INTEN, 4, 1)
44 FIELD(CTRL, RXO_INTEN, 5, 1)
45 FIELD(CTRL, HSTEST, 6, 1)
46 REG32(INTSTATUS, 0xc)
47 FIELD(INTSTATUS, TX, 0, 1)
48 FIELD(INTSTATUS, RX, 1, 1)
49 FIELD(INTSTATUS, TXO, 2, 1)
50 FIELD(INTSTATUS, RXO, 3, 1)
51 REG32(BAUDDIV, 0x10)
52 REG32(PID4, 0xFD0)
53 REG32(PID5, 0xFD4)
54 REG32(PID6, 0xFD8)
55 REG32(PID7, 0xFDC)
56 REG32(PID0, 0xFE0)
57 REG32(PID1, 0xFE4)
58 REG32(PID2, 0xFE8)
59 REG32(PID3, 0xFEC)
60 REG32(CID0, 0xFF0)
61 REG32(CID1, 0xFF4)
62 REG32(CID2, 0xFF8)
63 REG32(CID3, 0xFFC)
64
65 /* PID/CID values */
66 static const int uart_id[] = {
67 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
68 0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
69 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
70 };
71
72 static bool uart_baudrate_ok(CMSDKAPBUART *s)
73 {
74 /* The minimum permitted bauddiv setting is 16, so we just ignore
75 * settings below that (usually this means the device has just
76 * been reset and not yet programmed).
77 */
78 return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq;
79 }
80
81 static void uart_update_parameters(CMSDKAPBUART *s)
82 {
83 QEMUSerialSetParams ssp;
84
85 /* This UART is always 8N1 but the baud rate is programmable. */
86 if (!uart_baudrate_ok(s)) {
87 return;
88 }
89
90 ssp.data_bits = 8;
91 ssp.parity = 'N';
92 ssp.stop_bits = 1;
93 ssp.speed = s->pclk_frq / s->bauddiv;
94 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
95 trace_cmsdk_apb_uart_set_params(ssp.speed);
96 }
97
98 static void cmsdk_apb_uart_update(CMSDKAPBUART *s)
99 {
100 /* update outbound irqs, including handling the way the rxo and txo
101 * interrupt status bits are just logical AND of the overrun bit in
102 * STATE and the overrun interrupt enable bit in CTRL.
103 */
104 uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK);
105 s->intstatus &= ~omask;
106 s->intstatus |= (s->state & (s->ctrl >> 2) & omask);
107
108 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK));
109 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK));
110 qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK));
111 qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK));
112 qemu_set_irq(s->uartint, !!(s->intstatus));
113 }
114
115 static int uart_can_receive(void *opaque)
116 {
117 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
118
119 /* We can take a char if RX is enabled and the buffer is empty */
120 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) {
121 return 1;
122 }
123 return 0;
124 }
125
126 static void uart_receive(void *opaque, const uint8_t *buf, int size)
127 {
128 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
129
130 trace_cmsdk_apb_uart_receive(*buf);
131
132 /* In fact uart_can_receive() ensures that we can't be
133 * called unless RX is enabled and the buffer is empty,
134 * but we include this logic as documentation of what the
135 * hardware does if a character arrives in these circumstances.
136 */
137 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) {
138 /* Just drop the character on the floor */
139 return;
140 }
141
142 if (s->state & R_STATE_RXFULL_MASK) {
143 s->state |= R_STATE_RXOVERRUN_MASK;
144 }
145
146 s->rxbuf = *buf;
147 s->state |= R_STATE_RXFULL_MASK;
148 if (s->ctrl & R_CTRL_RX_INTEN_MASK) {
149 s->intstatus |= R_INTSTATUS_RX_MASK;
150 }
151 cmsdk_apb_uart_update(s);
152 }
153
154 static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size)
155 {
156 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
157 uint64_t r;
158
159 switch (offset) {
160 case A_DATA:
161 r = s->rxbuf;
162 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) {
163 qemu_log_mask(LOG_GUEST_ERROR,
164 "CMSDK APB UART: receive data read with Rx disabled\n");
165 }
166 s->state &= ~R_STATE_RXFULL_MASK;
167 cmsdk_apb_uart_update(s);
168 qemu_chr_fe_accept_input(&s->chr);
169 break;
170 case A_STATE:
171 r = s->state;
172 break;
173 case A_CTRL:
174 r = s->ctrl;
175 break;
176 case A_INTSTATUS:
177 r = s->intstatus;
178 break;
179 case A_BAUDDIV:
180 r = s->bauddiv;
181 break;
182 case A_PID4 ... A_CID3:
183 r = uart_id[(offset - A_PID4) / 4];
184 break;
185 default:
186 qemu_log_mask(LOG_GUEST_ERROR,
187 "CMSDK APB UART read: bad offset %x\n", (int) offset);
188 r = 0;
189 break;
190 }
191 trace_cmsdk_apb_uart_read(offset, r, size);
192 return r;
193 }
194
195 /* Try to send tx data, and arrange to be called back later if
196 * we can't (ie the char backend is busy/blocking).
197 */
198 static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
199 {
200 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
201 int ret;
202
203 s->watch_tag = 0;
204
205 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) {
206 return G_SOURCE_REMOVE;
207 }
208
209 ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1);
210 if (ret <= 0) {
211 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
212 uart_transmit, s);
213 if (!s->watch_tag) {
214 /* Most common reason to be here is "no chardev backend":
215 * just insta-drain the buffer, so the serial output
216 * goes into a void, rather than blocking the guest.
217 */
218 goto buffer_drained;
219 }
220 /* Transmit pending */
221 trace_cmsdk_apb_uart_tx_pending();
222 return G_SOURCE_REMOVE;
223 }
224
225 buffer_drained:
226 /* Character successfully sent */
227 trace_cmsdk_apb_uart_tx(s->txbuf);
228 s->state &= ~R_STATE_TXFULL_MASK;
229 /* Going from TXFULL set to clear triggers the tx interrupt */
230 if (s->ctrl & R_CTRL_TX_INTEN_MASK) {
231 s->intstatus |= R_INTSTATUS_TX_MASK;
232 }
233 cmsdk_apb_uart_update(s);
234 return G_SOURCE_REMOVE;
235 }
236
237 static void uart_cancel_transmit(CMSDKAPBUART *s)
238 {
239 g_clear_handle_id(&s->watch_tag, g_source_remove);
240 }
241
242 static void uart_write(void *opaque, hwaddr offset, uint64_t value,
243 unsigned size)
244 {
245 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
246
247 trace_cmsdk_apb_uart_write(offset, value, size);
248
249 switch (offset) {
250 case A_DATA:
251 s->txbuf = value;
252 if (!(s->ctrl & R_CTRL_TX_EN_MASK)) {
253 qemu_log_mask(LOG_GUEST_ERROR,
254 "CMSDK APB UART: transmit data write with Tx disabled\n");
255 }
256 if (s->state & R_STATE_TXFULL_MASK) {
257 /* Buffer already full -- note the overrun and let the
258 * existing pending transmit callback handle the new char.
259 */
260 s->state |= R_STATE_TXOVERRUN_MASK;
261 cmsdk_apb_uart_update(s);
262 } else {
263 s->state |= R_STATE_TXFULL_MASK;
264 uart_transmit(NULL, G_IO_OUT, s);
265 }
266 break;
267 case A_STATE:
268 /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */
269 s->state &= ~(value &
270 (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK));
271 cmsdk_apb_uart_update(s);
272 break;
273 case A_CTRL:
274 s->ctrl = value & 0x7f;
275 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) {
276 qemu_log_mask(LOG_GUEST_ERROR,
277 "CMSDK APB UART: Tx enabled with invalid baudrate\n");
278 }
279 cmsdk_apb_uart_update(s);
280 break;
281 case A_INTSTATUS:
282 /* All bits are W1C. Clearing the overrun interrupt bits really
283 * clears the overrun status bits in the STATE register (which
284 * is then reflected into the intstatus value by the update function).
285 */
286 s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK));
287 s->intstatus &= ~value;
288 cmsdk_apb_uart_update(s);
289 break;
290 case A_BAUDDIV:
291 s->bauddiv = value & 0xFFFFF;
292 uart_update_parameters(s);
293 break;
294 case A_PID4 ... A_CID3:
295 qemu_log_mask(LOG_GUEST_ERROR,
296 "CMSDK APB UART write: write to RO offset 0x%x\n",
297 (int)offset);
298 break;
299 default:
300 qemu_log_mask(LOG_GUEST_ERROR,
301 "CMSDK APB UART write: bad offset 0x%x\n", (int) offset);
302 break;
303 }
304 }
305
306 static const MemoryRegionOps uart_ops = {
307 .read = uart_read,
308 .write = uart_write,
309 .endianness = DEVICE_LITTLE_ENDIAN,
310 };
311
312 static void cmsdk_apb_uart_reset(DeviceState *dev)
313 {
314 CMSDKAPBUART *s = CMSDK_APB_UART(dev);
315
316 trace_cmsdk_apb_uart_reset();
317 uart_cancel_transmit(s);
318 s->state = 0;
319 s->ctrl = 0;
320 s->intstatus = 0;
321 s->bauddiv = 0;
322 s->txbuf = 0;
323 s->rxbuf = 0;
324 }
325
326 static void cmsdk_apb_uart_init(Object *obj)
327 {
328 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
329 CMSDKAPBUART *s = CMSDK_APB_UART(obj);
330
331 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
332 sysbus_init_mmio(sbd, &s->iomem);
333 sysbus_init_irq(sbd, &s->txint);
334 sysbus_init_irq(sbd, &s->rxint);
335 sysbus_init_irq(sbd, &s->txovrint);
336 sysbus_init_irq(sbd, &s->rxovrint);
337 sysbus_init_irq(sbd, &s->uartint);
338 }
339
340 static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp)
341 {
342 CMSDKAPBUART *s = CMSDK_APB_UART(dev);
343
344 if (s->pclk_frq == 0) {
345 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set");
346 return;
347 }
348
349 /* This UART has no flow control, so we do not need to register
350 * an event handler to deal with CHR_EVENT_BREAK.
351 */
352 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
353 NULL, NULL, s, NULL, true);
354 }
355
356 static int cmsdk_apb_uart_post_load(void *opaque, int version_id)
357 {
358 CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
359
360 /* If we have a pending character, arrange to resend it. */
361 if (s->state & R_STATE_TXFULL_MASK) {
362 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
363 uart_transmit, s);
364 }
365 uart_update_parameters(s);
366 return 0;
367 }
368
369 static const VMStateDescription cmsdk_apb_uart_vmstate = {
370 .name = "cmsdk-apb-uart",
371 .version_id = 1,
372 .minimum_version_id = 1,
373 .post_load = cmsdk_apb_uart_post_load,
374 .fields = (const VMStateField[]) {
375 VMSTATE_UINT32(state, CMSDKAPBUART),
376 VMSTATE_UINT32(ctrl, CMSDKAPBUART),
377 VMSTATE_UINT32(intstatus, CMSDKAPBUART),
378 VMSTATE_UINT32(bauddiv, CMSDKAPBUART),
379 VMSTATE_UINT8(txbuf, CMSDKAPBUART),
380 VMSTATE_UINT8(rxbuf, CMSDKAPBUART),
381 VMSTATE_END_OF_LIST()
382 }
383 };
384
385 static const Property cmsdk_apb_uart_properties[] = {
386 DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr),
387 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0),
388 };
389
390 static void cmsdk_apb_uart_class_init(ObjectClass *klass, const void *data)
391 {
392 DeviceClass *dc = DEVICE_CLASS(klass);
393
394 dc->realize = cmsdk_apb_uart_realize;
395 dc->vmsd = &cmsdk_apb_uart_vmstate;
396 device_class_set_legacy_reset(dc, cmsdk_apb_uart_reset);
397 device_class_set_props(dc, cmsdk_apb_uart_properties);
398 }
399
400 static const TypeInfo cmsdk_apb_uart_info = {
401 .name = TYPE_CMSDK_APB_UART,
402 .parent = TYPE_SYS_BUS_DEVICE,
403 .instance_size = sizeof(CMSDKAPBUART),
404 .instance_init = cmsdk_apb_uart_init,
405 .class_init = cmsdk_apb_uart_class_init,
406 };
407
408 static void cmsdk_apb_uart_register_types(void)
409 {
410 type_register_static(&cmsdk_apb_uart_info);
411 }
412
413 type_init(cmsdk_apb_uart_register_types);