| 1 | /* |
| 2 | * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/core/irq.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "hw/core/qdev-properties-system.h" |
| 29 | #include "hw/core/sysbus.h" |
| 30 | #include "migration/vmstate.h" |
| 31 | #include "qemu/module.h" |
| 32 | #include "hw/char/escc.h" |
| 33 | #include "standard-headers/linux/input-event-codes.h" |
| 34 | #include "ui/console.h" |
| 35 | |
| 36 | #include "qemu/cutils.h" |
| 37 | #include "trace.h" |
| 38 | |
| 39 | /* |
| 40 | * Chipset docs: |
| 41 | * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual", |
| 42 | * http://www.zilog.com/docs/serial/scc_escc_um.pdf |
| 43 | * |
| 44 | * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001 |
| 45 | * (Slave I/O), also produced as NCR89C105. See |
| 46 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
| 47 | * |
| 48 | * The serial ports implement full AMD AM8530 or Zilog Z8530 chips, |
| 49 | * mouse and keyboard ports don't implement all functions and they are |
| 50 | * only asynchronous. There is no DMA. |
| 51 | * |
| 52 | * Z85C30 is also used on PowerMacs and m68k Macs. |
| 53 | * |
| 54 | * There are some small differences between Sparc version (sunzilog) |
| 55 | * and PowerMac (pmac): |
| 56 | * Offset between control and data registers |
| 57 | * There is some kind of lockup bug, but we can ignore it |
| 58 | * CTS is inverted |
| 59 | * DMA on pmac using DBDMA chip |
| 60 | * pmac can do IRDA and faster rates, sunzilog can only do 38400 |
| 61 | * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz |
| 62 | * |
| 63 | * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), |
| 64 | * but registers are grouped by type and not by channel: |
| 65 | * channel is selected by bit 0 of the address (instead of bit 1) |
| 66 | * and register is selected by bit 1 of the address (instead of bit 0). |
| 67 | */ |
| 68 | |
| 69 | /* |
| 70 | * Modifications: |
| 71 | * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented |
| 72 | * serial mouse queue. |
| 73 | * Implemented serial mouse protocol. |
| 74 | * |
| 75 | * 2010-May-23 Artyom Tarasenko: Reworked IUS logic |
| 76 | */ |
| 77 | |
| 78 | #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a') |
| 79 | |
| 80 | #define SERIAL_CTRL 0 |
| 81 | #define SERIAL_DATA 1 |
| 82 | |
| 83 | #define W_CMD 0 |
| 84 | #define CMD_PTR_MASK 0x07 |
| 85 | #define CMD_CMD_MASK 0x38 |
| 86 | #define CMD_HI 0x08 |
| 87 | #define CMD_CLR_TXINT 0x28 |
| 88 | #define CMD_CLR_IUS 0x38 |
| 89 | #define W_INTR 1 |
| 90 | #define INTR_INTALL 0x01 |
| 91 | #define INTR_TXINT 0x02 |
| 92 | #define INTR_PAR_SPEC 0x04 |
| 93 | #define INTR_RXMODEMSK 0x18 |
| 94 | #define INTR_RXINT1ST 0x08 |
| 95 | #define INTR_RXINTALL 0x10 |
| 96 | #define INTR_WTRQ_TXRX 0x20 |
| 97 | #define W_IVEC 2 |
| 98 | #define W_RXCTRL 3 |
| 99 | #define RXCTRL_RXEN 0x01 |
| 100 | #define RXCTRL_HUNT 0x10 |
| 101 | #define W_TXCTRL1 4 |
| 102 | #define TXCTRL1_PAREN 0x01 |
| 103 | #define TXCTRL1_PAREV 0x02 |
| 104 | #define TXCTRL1_1STOP 0x04 |
| 105 | #define TXCTRL1_1HSTOP 0x08 |
| 106 | #define TXCTRL1_2STOP 0x0c |
| 107 | #define TXCTRL1_STPMSK 0x0c |
| 108 | #define TXCTRL1_CLK1X 0x00 |
| 109 | #define TXCTRL1_CLK16X 0x40 |
| 110 | #define TXCTRL1_CLK32X 0x80 |
| 111 | #define TXCTRL1_CLK64X 0xc0 |
| 112 | #define TXCTRL1_CLKMSK 0xc0 |
| 113 | #define W_TXCTRL2 5 |
| 114 | #define TXCTRL2_TXCRC 0x01 |
| 115 | #define TXCTRL2_TXEN 0x08 |
| 116 | #define TXCTRL2_BITMSK 0x60 |
| 117 | #define TXCTRL2_5BITS 0x00 |
| 118 | #define TXCTRL2_7BITS 0x20 |
| 119 | #define TXCTRL2_6BITS 0x40 |
| 120 | #define TXCTRL2_8BITS 0x60 |
| 121 | #define W_SYNC1 6 |
| 122 | #define W_SYNC2 7 |
| 123 | #define W_TXBUF 8 |
| 124 | #define W_MINTR 9 |
| 125 | #define MINTR_VIS 0x01 |
| 126 | #define MINTR_NV 0x02 |
| 127 | #define MINTR_STATUSHI 0x10 |
| 128 | #define MINTR_SOFTIACK 0x20 |
| 129 | #define MINTR_RST_MASK 0xc0 |
| 130 | #define MINTR_RST_B 0x40 |
| 131 | #define MINTR_RST_A 0x80 |
| 132 | #define MINTR_RST_ALL 0xc0 |
| 133 | #define W_MISC1 10 |
| 134 | #define MISC1_ENC_MASK 0x60 |
| 135 | #define W_CLOCK 11 |
| 136 | #define CLOCK_TRXC 0x08 |
| 137 | #define W_BRGLO 12 |
| 138 | #define W_BRGHI 13 |
| 139 | #define W_MISC2 14 |
| 140 | #define MISC2_BRG_EN 0x01 |
| 141 | #define MISC2_BRG_SRC 0x02 |
| 142 | #define MISC2_LCL_LOOP 0x10 |
| 143 | #define MISC2_PLLCMD0 0x20 |
| 144 | #define MISC2_PLLCMD1 0x40 |
| 145 | #define MISC2_PLLCMD2 0x80 |
| 146 | #define W_EXTINT 15 |
| 147 | #define EXTINT_DCD 0x08 |
| 148 | #define EXTINT_SYNCINT 0x10 |
| 149 | #define EXTINT_CTSINT 0x20 |
| 150 | #define EXTINT_TXUNDRN 0x40 |
| 151 | #define EXTINT_BRKINT 0x80 |
| 152 | |
| 153 | #define R_STATUS 0 |
| 154 | #define STATUS_RXAV 0x01 |
| 155 | #define STATUS_ZERO 0x02 |
| 156 | #define STATUS_TXEMPTY 0x04 |
| 157 | #define STATUS_DCD 0x08 |
| 158 | #define STATUS_SYNC 0x10 |
| 159 | #define STATUS_CTS 0x20 |
| 160 | #define STATUS_TXUNDRN 0x40 |
| 161 | #define STATUS_BRK 0x80 |
| 162 | #define R_SPEC 1 |
| 163 | #define SPEC_ALLSENT 0x01 |
| 164 | #define SPEC_BITS8 0x06 |
| 165 | #define R_IVEC 2 |
| 166 | #define IVEC_TXINTB 0x00 |
| 167 | #define IVEC_LONOINT 0x06 |
| 168 | #define IVEC_LORXINTA 0x0c |
| 169 | #define IVEC_LORXINTB 0x04 |
| 170 | #define IVEC_LOTXINTA 0x08 |
| 171 | #define IVEC_HINOINT 0x60 |
| 172 | #define IVEC_HIRXINTA 0x30 |
| 173 | #define IVEC_HIRXINTB 0x20 |
| 174 | #define IVEC_HITXINTA 0x10 |
| 175 | #define R_INTR 3 |
| 176 | #define INTR_EXTINTB 0x01 |
| 177 | #define INTR_TXINTB 0x02 |
| 178 | #define INTR_RXINTB 0x04 |
| 179 | #define INTR_EXTINTA 0x08 |
| 180 | #define INTR_TXINTA 0x10 |
| 181 | #define INTR_RXINTA 0x20 |
| 182 | #define R_IPEN 4 |
| 183 | #define R_TXCTRL1 5 |
| 184 | #define R_TXCTRL2 6 |
| 185 | #define R_BC 7 |
| 186 | #define R_RXBUF 8 |
| 187 | #define R_RXCTRL 9 |
| 188 | #define R_MISC 10 |
| 189 | #define MISC_2CLKMISS 0x40 |
| 190 | #define R_MISC1 11 |
| 191 | #define R_BRGLO 12 |
| 192 | #define R_BRGHI 13 |
| 193 | #define R_MISC1I 14 |
| 194 | #define R_EXTINT 15 |
| 195 | |
| 196 | static uint8_t sunkbd_layout_dip_switch(const char *sunkbd_layout); |
| 197 | static void handle_kbd_command(ESCCChannelState *s, int val); |
| 198 | static int serial_can_receive(void *opaque); |
| 199 | static void serial_receive_byte(ESCCChannelState *s, int ch); |
| 200 | |
| 201 | static int reg_shift(ESCCState *s) |
| 202 | { |
| 203 | return s->bit_swap ? s->it_shift + 1 : s->it_shift; |
| 204 | } |
| 205 | |
| 206 | static int chn_shift(ESCCState *s) |
| 207 | { |
| 208 | return s->bit_swap ? s->it_shift : s->it_shift + 1; |
| 209 | } |
| 210 | |
| 211 | static void clear_queue(void *opaque) |
| 212 | { |
| 213 | ESCCChannelState *s = opaque; |
| 214 | ESCCSERIOQueue *q = &s->queue; |
| 215 | q->rptr = q->wptr = q->count = 0; |
| 216 | } |
| 217 | |
| 218 | static void put_queue(void *opaque, int b) |
| 219 | { |
| 220 | ESCCChannelState *s = opaque; |
| 221 | ESCCSERIOQueue *q = &s->queue; |
| 222 | |
| 223 | trace_escc_put_queue(CHN_C(s), b); |
| 224 | if (q->count >= ESCC_SERIO_QUEUE_SIZE) { |
| 225 | return; |
| 226 | } |
| 227 | q->data[q->wptr] = b; |
| 228 | if (++q->wptr == ESCC_SERIO_QUEUE_SIZE) { |
| 229 | q->wptr = 0; |
| 230 | } |
| 231 | q->count++; |
| 232 | serial_receive_byte(s, 0); |
| 233 | } |
| 234 | |
| 235 | static uint32_t get_queue(void *opaque) |
| 236 | { |
| 237 | ESCCChannelState *s = opaque; |
| 238 | ESCCSERIOQueue *q = &s->queue; |
| 239 | int val; |
| 240 | |
| 241 | if (q->count == 0) { |
| 242 | return 0; |
| 243 | } else { |
| 244 | val = q->data[q->rptr]; |
| 245 | if (++q->rptr == ESCC_SERIO_QUEUE_SIZE) { |
| 246 | q->rptr = 0; |
| 247 | } |
| 248 | q->count--; |
| 249 | } |
| 250 | trace_escc_get_queue(CHN_C(s), val); |
| 251 | if (q->count > 0) { |
| 252 | serial_receive_byte(s, 0); |
| 253 | } |
| 254 | return val; |
| 255 | } |
| 256 | |
| 257 | static int escc_update_irq_chn(ESCCChannelState *s) |
| 258 | { |
| 259 | if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || |
| 260 | /* tx ints enabled, pending */ |
| 261 | ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || |
| 262 | ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && |
| 263 | s->rxint == 1) || |
| 264 | /* rx ints enabled, pending */ |
| 265 | ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && |
| 266 | (s->rregs[R_STATUS] & STATUS_BRK)))) { |
| 267 | /* break int e&p */ |
| 268 | return 1; |
| 269 | } |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static void escc_update_irq(ESCCChannelState *s) |
| 274 | { |
| 275 | int irq; |
| 276 | |
| 277 | irq = escc_update_irq_chn(s); |
| 278 | irq |= escc_update_irq_chn(s->otherchn); |
| 279 | |
| 280 | trace_escc_update_irq(irq); |
| 281 | qemu_set_irq(s->irq, irq); |
| 282 | } |
| 283 | |
| 284 | static void escc_reset_chn(ESCCChannelState *s) |
| 285 | { |
| 286 | s->reg = 0; |
| 287 | s->rx = s->tx = 0; |
| 288 | s->rxint = s->txint = 0; |
| 289 | s->rxint_under_svc = s->txint_under_svc = 0; |
| 290 | s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; |
| 291 | s->sunmouse_dx = s->sunmouse_dy = s->sunmouse_buttons = 0; |
| 292 | clear_queue(s); |
| 293 | } |
| 294 | |
| 295 | static void escc_soft_reset_chn(ESCCChannelState *s) |
| 296 | { |
| 297 | escc_reset_chn(s); |
| 298 | |
| 299 | s->wregs[W_CMD] = 0; |
| 300 | s->wregs[W_INTR] &= INTR_PAR_SPEC | INTR_WTRQ_TXRX; |
| 301 | s->wregs[W_RXCTRL] &= ~RXCTRL_RXEN; |
| 302 | /* 1 stop bit */ |
| 303 | s->wregs[W_TXCTRL1] |= TXCTRL1_1STOP; |
| 304 | s->wregs[W_TXCTRL2] &= TXCTRL2_TXCRC | TXCTRL2_8BITS; |
| 305 | s->wregs[W_MINTR] &= ~MINTR_SOFTIACK; |
| 306 | s->wregs[W_MISC1] &= MISC1_ENC_MASK; |
| 307 | /* PLL disabled */ |
| 308 | s->wregs[W_MISC2] &= MISC2_BRG_EN | MISC2_BRG_SRC | |
| 309 | MISC2_PLLCMD1 | MISC2_PLLCMD2; |
| 310 | s->wregs[W_MISC2] |= MISC2_PLLCMD0; |
| 311 | /* Enable most interrupts */ |
| 312 | s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | |
| 313 | EXTINT_TXUNDRN | EXTINT_BRKINT; |
| 314 | |
| 315 | s->rregs[R_STATUS] &= STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS_BRK; |
| 316 | s->rregs[R_STATUS] |= STATUS_TXEMPTY | STATUS_TXUNDRN; |
| 317 | if (s->disabled) { |
| 318 | s->rregs[R_STATUS] |= STATUS_DCD | STATUS_SYNC | STATUS_CTS; |
| 319 | } |
| 320 | s->rregs[R_SPEC] &= SPEC_ALLSENT; |
| 321 | s->rregs[R_SPEC] |= SPEC_BITS8; |
| 322 | s->rregs[R_INTR] = 0; |
| 323 | s->rregs[R_MISC] &= MISC_2CLKMISS; |
| 324 | } |
| 325 | |
| 326 | static void escc_hard_reset_chn(ESCCChannelState *s) |
| 327 | { |
| 328 | escc_soft_reset_chn(s); |
| 329 | |
| 330 | /* |
| 331 | * Hard reset is almost identical to soft reset above, except that the |
| 332 | * values of WR9 (W_MINTR), WR10 (W_MISC1), WR11 (W_CLOCK) and WR14 |
| 333 | * (W_MISC2) have extra bits forced to 0/1 |
| 334 | */ |
| 335 | s->wregs[W_MINTR] &= MINTR_VIS | MINTR_NV; |
| 336 | s->wregs[W_MINTR] |= MINTR_RST_B | MINTR_RST_A; |
| 337 | s->wregs[W_MISC1] = 0; |
| 338 | s->wregs[W_CLOCK] = CLOCK_TRXC; |
| 339 | s->wregs[W_MISC2] &= MISC2_PLLCMD1 | MISC2_PLLCMD2; |
| 340 | s->wregs[W_MISC2] |= MISC2_LCL_LOOP | MISC2_PLLCMD0; |
| 341 | } |
| 342 | |
| 343 | static void escc_reset(DeviceState *d) |
| 344 | { |
| 345 | ESCCState *s = ESCC(d); |
| 346 | int i, j; |
| 347 | |
| 348 | for (i = 0; i < 2; i++) { |
| 349 | ESCCChannelState *cs = &s->chn[i]; |
| 350 | |
| 351 | /* |
| 352 | * According to the ESCC datasheet "Miscellaneous Questions" section |
| 353 | * on page 384, the values of the ESCC registers are not guaranteed on |
| 354 | * power-on until an explicit hardware or software reset has been |
| 355 | * issued. For now we zero the registers so that a device reset always |
| 356 | * returns the emulated device to a fixed state. |
| 357 | */ |
| 358 | for (j = 0; j < ESCC_SERIAL_REGS; j++) { |
| 359 | cs->rregs[j] = 0; |
| 360 | cs->wregs[j] = 0; |
| 361 | } |
| 362 | |
| 363 | /* |
| 364 | * ...but there is an exception. The "Transmit Interrupts and Transmit |
| 365 | * Buffer Empty Bit" section on page 50 of the ESCC datasheet says of |
| 366 | * the STATUS_TXEMPTY bit in R_STATUS: "After a hardware reset |
| 367 | * (including a hardware reset by software), or a channel reset, this |
| 368 | * bit is set to 1". The Sun PROM checks this bit early on startup and |
| 369 | * gets stuck in an infinite loop if it is not set. |
| 370 | */ |
| 371 | cs->rregs[R_STATUS] |= STATUS_TXEMPTY; |
| 372 | |
| 373 | escc_reset_chn(cs); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | static inline void set_rxint(ESCCChannelState *s) |
| 378 | { |
| 379 | s->rxint = 1; |
| 380 | /* |
| 381 | * XXX: missing daisy chaining: escc_chn_b rx should have a lower priority |
| 382 | * than chn_a rx/tx/special_condition service |
| 383 | */ |
| 384 | s->rxint_under_svc = 1; |
| 385 | if (s->chn == escc_chn_a) { |
| 386 | s->rregs[R_INTR] |= INTR_RXINTA; |
| 387 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 388 | s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; |
| 389 | } else { |
| 390 | s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; |
| 391 | } |
| 392 | } else { |
| 393 | s->otherchn->rregs[R_INTR] |= INTR_RXINTB; |
| 394 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 395 | s->rregs[R_IVEC] = IVEC_HIRXINTB; |
| 396 | } else { |
| 397 | s->rregs[R_IVEC] = IVEC_LORXINTB; |
| 398 | } |
| 399 | } |
| 400 | escc_update_irq(s); |
| 401 | } |
| 402 | |
| 403 | static inline void set_txint(ESCCChannelState *s) |
| 404 | { |
| 405 | s->txint = 1; |
| 406 | if (!s->rxint_under_svc) { |
| 407 | s->txint_under_svc = 1; |
| 408 | if (s->chn == escc_chn_a) { |
| 409 | if (s->wregs[W_INTR] & INTR_TXINT) { |
| 410 | s->rregs[R_INTR] |= INTR_TXINTA; |
| 411 | } |
| 412 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 413 | s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; |
| 414 | } else { |
| 415 | s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; |
| 416 | } |
| 417 | } else { |
| 418 | s->rregs[R_IVEC] = IVEC_TXINTB; |
| 419 | if (s->wregs[W_INTR] & INTR_TXINT) { |
| 420 | s->otherchn->rregs[R_INTR] |= INTR_TXINTB; |
| 421 | } |
| 422 | } |
| 423 | escc_update_irq(s); |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | static inline void clr_rxint(ESCCChannelState *s) |
| 428 | { |
| 429 | s->rxint = 0; |
| 430 | s->rxint_under_svc = 0; |
| 431 | if (s->chn == escc_chn_a) { |
| 432 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 433 | s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
| 434 | } else { |
| 435 | s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
| 436 | } |
| 437 | s->rregs[R_INTR] &= ~INTR_RXINTA; |
| 438 | } else { |
| 439 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 440 | s->rregs[R_IVEC] = IVEC_HINOINT; |
| 441 | } else { |
| 442 | s->rregs[R_IVEC] = IVEC_LONOINT; |
| 443 | } |
| 444 | s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; |
| 445 | } |
| 446 | if (s->txint) { |
| 447 | set_txint(s); |
| 448 | } |
| 449 | escc_update_irq(s); |
| 450 | } |
| 451 | |
| 452 | static inline void clr_txint(ESCCChannelState *s) |
| 453 | { |
| 454 | s->txint = 0; |
| 455 | s->txint_under_svc = 0; |
| 456 | if (s->chn == escc_chn_a) { |
| 457 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 458 | s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
| 459 | } else { |
| 460 | s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
| 461 | } |
| 462 | s->rregs[R_INTR] &= ~INTR_TXINTA; |
| 463 | } else { |
| 464 | s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
| 465 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) { |
| 466 | s->rregs[R_IVEC] = IVEC_HINOINT; |
| 467 | } else { |
| 468 | s->rregs[R_IVEC] = IVEC_LONOINT; |
| 469 | } |
| 470 | s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
| 471 | } |
| 472 | if (s->rxint) { |
| 473 | set_rxint(s); |
| 474 | } |
| 475 | escc_update_irq(s); |
| 476 | } |
| 477 | |
| 478 | static void escc_update_parameters(ESCCChannelState *s) |
| 479 | { |
| 480 | int speed, parity, data_bits, stop_bits; |
| 481 | QEMUSerialSetParams ssp; |
| 482 | |
| 483 | if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != escc_serial) { |
| 484 | return; |
| 485 | } |
| 486 | |
| 487 | if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { |
| 488 | if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) { |
| 489 | parity = 'E'; |
| 490 | } else { |
| 491 | parity = 'O'; |
| 492 | } |
| 493 | } else { |
| 494 | parity = 'N'; |
| 495 | } |
| 496 | if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) { |
| 497 | stop_bits = 2; |
| 498 | } else { |
| 499 | stop_bits = 1; |
| 500 | } |
| 501 | switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { |
| 502 | case TXCTRL2_5BITS: |
| 503 | data_bits = 5; |
| 504 | break; |
| 505 | case TXCTRL2_7BITS: |
| 506 | data_bits = 7; |
| 507 | break; |
| 508 | case TXCTRL2_6BITS: |
| 509 | data_bits = 6; |
| 510 | break; |
| 511 | default: |
| 512 | case TXCTRL2_8BITS: |
| 513 | data_bits = 8; |
| 514 | break; |
| 515 | } |
| 516 | speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); |
| 517 | switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { |
| 518 | case TXCTRL1_CLK1X: |
| 519 | break; |
| 520 | case TXCTRL1_CLK16X: |
| 521 | speed /= 16; |
| 522 | break; |
| 523 | case TXCTRL1_CLK32X: |
| 524 | speed /= 32; |
| 525 | break; |
| 526 | default: |
| 527 | case TXCTRL1_CLK64X: |
| 528 | speed /= 64; |
| 529 | break; |
| 530 | } |
| 531 | ssp.speed = speed; |
| 532 | ssp.parity = parity; |
| 533 | ssp.data_bits = data_bits; |
| 534 | ssp.stop_bits = stop_bits; |
| 535 | trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); |
| 536 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 537 | } |
| 538 | |
| 539 | static void escc_mem_write(void *opaque, hwaddr addr, |
| 540 | uint64_t val, unsigned size) |
| 541 | { |
| 542 | ESCCState *serial = opaque; |
| 543 | ESCCChannelState *s; |
| 544 | uint32_t saddr; |
| 545 | int newreg, channel; |
| 546 | |
| 547 | val &= 0xff; |
| 548 | saddr = (addr >> reg_shift(serial)) & 1; |
| 549 | channel = (addr >> chn_shift(serial)) & 1; |
| 550 | s = &serial->chn[channel]; |
| 551 | switch (saddr) { |
| 552 | case SERIAL_CTRL: |
| 553 | trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); |
| 554 | newreg = 0; |
| 555 | switch (s->reg) { |
| 556 | case W_CMD: |
| 557 | newreg = val & CMD_PTR_MASK; |
| 558 | val &= CMD_CMD_MASK; |
| 559 | switch (val) { |
| 560 | case CMD_HI: |
| 561 | newreg |= CMD_HI; |
| 562 | break; |
| 563 | case CMD_CLR_TXINT: |
| 564 | clr_txint(s); |
| 565 | break; |
| 566 | case CMD_CLR_IUS: |
| 567 | if (s->rxint_under_svc) { |
| 568 | s->rxint_under_svc = 0; |
| 569 | if (s->txint) { |
| 570 | set_txint(s); |
| 571 | } |
| 572 | } else if (s->txint_under_svc) { |
| 573 | s->txint_under_svc = 0; |
| 574 | } |
| 575 | escc_update_irq(s); |
| 576 | break; |
| 577 | default: |
| 578 | break; |
| 579 | } |
| 580 | break; |
| 581 | case W_RXCTRL: |
| 582 | s->wregs[s->reg] = val; |
| 583 | if (val & RXCTRL_HUNT) { |
| 584 | s->rregs[R_STATUS] |= STATUS_SYNC; |
| 585 | } |
| 586 | break; |
| 587 | case W_INTR ... W_IVEC: |
| 588 | case W_SYNC1 ... W_TXBUF: |
| 589 | case W_MISC1 ... W_CLOCK: |
| 590 | case W_MISC2 ... W_EXTINT: |
| 591 | s->wregs[s->reg] = val; |
| 592 | break; |
| 593 | case W_TXCTRL1: |
| 594 | s->wregs[s->reg] = val; |
| 595 | /* |
| 596 | * The ESCC datasheet states that SPEC_ALLSENT is always set in |
| 597 | * sync mode, and set in async mode when all characters have |
| 598 | * cleared the transmitter. Since writes to SERIAL_DATA use the |
| 599 | * blocking qemu_chr_fe_write_all() function to write each |
| 600 | * character, the guest can never see the state when async data |
| 601 | * is in the process of being transmitted so we can set this bit |
| 602 | * unconditionally regardless of the state of the W_TXCTRL1 mode |
| 603 | * bits. |
| 604 | */ |
| 605 | s->rregs[R_SPEC] |= SPEC_ALLSENT; |
| 606 | escc_update_parameters(s); |
| 607 | break; |
| 608 | case W_TXCTRL2: |
| 609 | s->wregs[s->reg] = val; |
| 610 | escc_update_parameters(s); |
| 611 | break; |
| 612 | case W_BRGLO: |
| 613 | case W_BRGHI: |
| 614 | s->wregs[s->reg] = val; |
| 615 | s->rregs[s->reg] = val; |
| 616 | escc_update_parameters(s); |
| 617 | break; |
| 618 | case W_MINTR: |
| 619 | switch (val & MINTR_RST_MASK) { |
| 620 | case 0: |
| 621 | default: |
| 622 | break; |
| 623 | case MINTR_RST_B: |
| 624 | trace_escc_soft_reset_chn(CHN_C(&serial->chn[0])); |
| 625 | escc_soft_reset_chn(&serial->chn[0]); |
| 626 | return; |
| 627 | case MINTR_RST_A: |
| 628 | trace_escc_soft_reset_chn(CHN_C(&serial->chn[1])); |
| 629 | escc_soft_reset_chn(&serial->chn[1]); |
| 630 | return; |
| 631 | case MINTR_RST_ALL: |
| 632 | trace_escc_hard_reset(); |
| 633 | escc_hard_reset_chn(&serial->chn[0]); |
| 634 | escc_hard_reset_chn(&serial->chn[1]); |
| 635 | return; |
| 636 | } |
| 637 | break; |
| 638 | default: |
| 639 | break; |
| 640 | } |
| 641 | if (s->reg == 0) { |
| 642 | s->reg = newreg; |
| 643 | } else { |
| 644 | s->reg = 0; |
| 645 | } |
| 646 | break; |
| 647 | case SERIAL_DATA: |
| 648 | trace_escc_mem_writeb_data(CHN_C(s), val); |
| 649 | /* |
| 650 | * Lower the irq when data is written to the Tx buffer and no other |
| 651 | * interrupts are currently pending. The irq will be raised again once |
| 652 | * the Tx buffer becomes empty below. |
| 653 | */ |
| 654 | s->txint = 0; |
| 655 | escc_update_irq(s); |
| 656 | s->tx = val; |
| 657 | if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */ |
| 658 | if (s->wregs[W_MISC2] & MISC2_LCL_LOOP) { |
| 659 | serial_receive_byte(s, s->tx); |
| 660 | } else if (qemu_chr_fe_backend_connected(&s->chr)) { |
| 661 | /* |
| 662 | * XXX this blocks entire thread. Rewrite to use |
| 663 | * qemu_chr_fe_write and background I/O callbacks |
| 664 | */ |
| 665 | qemu_chr_fe_write_all(&s->chr, &s->tx, 1); |
| 666 | } else if (s->type == escc_kbd && !s->disabled) { |
| 667 | handle_kbd_command(s, val); |
| 668 | } |
| 669 | } |
| 670 | s->rregs[R_STATUS] |= STATUS_TXEMPTY; /* Tx buffer empty */ |
| 671 | s->rregs[R_SPEC] |= SPEC_ALLSENT; /* All sent */ |
| 672 | set_txint(s); |
| 673 | break; |
| 674 | default: |
| 675 | break; |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | static uint64_t escc_mem_read(void *opaque, hwaddr addr, |
| 680 | unsigned size) |
| 681 | { |
| 682 | ESCCState *serial = opaque; |
| 683 | ESCCChannelState *s; |
| 684 | uint32_t saddr; |
| 685 | uint32_t ret; |
| 686 | int channel; |
| 687 | |
| 688 | saddr = (addr >> reg_shift(serial)) & 1; |
| 689 | channel = (addr >> chn_shift(serial)) & 1; |
| 690 | s = &serial->chn[channel]; |
| 691 | switch (saddr) { |
| 692 | case SERIAL_CTRL: |
| 693 | trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); |
| 694 | ret = s->rregs[s->reg]; |
| 695 | s->reg = 0; |
| 696 | return ret; |
| 697 | case SERIAL_DATA: |
| 698 | s->rregs[R_STATUS] &= ~STATUS_RXAV; |
| 699 | clr_rxint(s); |
| 700 | if (s->type == escc_kbd || s->type == escc_mouse) { |
| 701 | ret = get_queue(s); |
| 702 | } else { |
| 703 | ret = s->rx; |
| 704 | } |
| 705 | trace_escc_mem_readb_data(CHN_C(s), ret); |
| 706 | qemu_chr_fe_accept_input(&s->chr); |
| 707 | return ret; |
| 708 | default: |
| 709 | break; |
| 710 | } |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | static const MemoryRegionOps escc_mem_ops = { |
| 715 | .read = escc_mem_read, |
| 716 | .write = escc_mem_write, |
| 717 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 718 | .valid = { |
| 719 | .min_access_size = 1, |
| 720 | .max_access_size = 1, |
| 721 | }, |
| 722 | }; |
| 723 | |
| 724 | static int serial_can_receive(void *opaque) |
| 725 | { |
| 726 | ESCCChannelState *s = opaque; |
| 727 | int ret; |
| 728 | |
| 729 | if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) /* Rx not enabled */ |
| 730 | || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) { |
| 731 | /* char already available */ |
| 732 | ret = 0; |
| 733 | } else { |
| 734 | ret = 1; |
| 735 | } |
| 736 | return ret; |
| 737 | } |
| 738 | |
| 739 | static void serial_receive_byte(ESCCChannelState *s, int ch) |
| 740 | { |
| 741 | trace_escc_serial_receive_byte(CHN_C(s), ch); |
| 742 | s->rregs[R_STATUS] |= STATUS_RXAV; |
| 743 | s->rx = ch; |
| 744 | set_rxint(s); |
| 745 | } |
| 746 | |
| 747 | static void serial_receive_break(ESCCChannelState *s) |
| 748 | { |
| 749 | s->rregs[R_STATUS] |= STATUS_BRK; |
| 750 | escc_update_irq(s); |
| 751 | } |
| 752 | |
| 753 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
| 754 | { |
| 755 | ESCCChannelState *s = opaque; |
| 756 | serial_receive_byte(s, buf[0]); |
| 757 | } |
| 758 | |
| 759 | static void serial_event(void *opaque, QEMUChrEvent event) |
| 760 | { |
| 761 | ESCCChannelState *s = opaque; |
| 762 | if (event == CHR_EVENT_BREAK) { |
| 763 | serial_receive_break(s); |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | static const VMStateDescription vmstate_escc_chn = { |
| 768 | .name = "escc_chn", |
| 769 | .version_id = 2, |
| 770 | .minimum_version_id = 1, |
| 771 | .fields = (const VMStateField[]) { |
| 772 | VMSTATE_UINT32(vmstate_dummy, ESCCChannelState), |
| 773 | VMSTATE_UINT32(reg, ESCCChannelState), |
| 774 | VMSTATE_UINT32(rxint, ESCCChannelState), |
| 775 | VMSTATE_UINT32(txint, ESCCChannelState), |
| 776 | VMSTATE_UINT32(rxint_under_svc, ESCCChannelState), |
| 777 | VMSTATE_UINT32(txint_under_svc, ESCCChannelState), |
| 778 | VMSTATE_UINT8(rx, ESCCChannelState), |
| 779 | VMSTATE_UINT8(tx, ESCCChannelState), |
| 780 | VMSTATE_BUFFER(wregs, ESCCChannelState), |
| 781 | VMSTATE_BUFFER(rregs, ESCCChannelState), |
| 782 | VMSTATE_END_OF_LIST() |
| 783 | } |
| 784 | }; |
| 785 | |
| 786 | static const VMStateDescription vmstate_escc = { |
| 787 | .name = "escc", |
| 788 | .version_id = 2, |
| 789 | .minimum_version_id = 1, |
| 790 | .fields = (const VMStateField[]) { |
| 791 | VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn, |
| 792 | ESCCChannelState), |
| 793 | VMSTATE_END_OF_LIST() |
| 794 | } |
| 795 | }; |
| 796 | |
| 797 | static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src, |
| 798 | QemuInputEvent *evt) |
| 799 | { |
| 800 | ESCCChannelState *s = (ESCCChannelState *)dev; |
| 801 | int qcode, keycode; |
| 802 | |
| 803 | assert(evt->type == INPUT_EVENT_KIND_KEY); |
| 804 | qcode = qemu_input_linux_to_qcode(evt->key.key); |
| 805 | trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode), |
| 806 | evt->key.down); |
| 807 | |
| 808 | if (evt->key.key == KEY_CAPSLOCK) { |
| 809 | if (evt->key.down) { |
| 810 | s->caps_lock_mode ^= 1; |
| 811 | if (s->caps_lock_mode == 2) { |
| 812 | return; /* Drop second press */ |
| 813 | } |
| 814 | } else { |
| 815 | s->caps_lock_mode ^= 2; |
| 816 | if (s->caps_lock_mode == 3) { |
| 817 | return; /* Drop first release */ |
| 818 | } |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | if (evt->key.key == KEY_NUMLOCK) { |
| 823 | if (evt->key.down) { |
| 824 | s->num_lock_mode ^= 1; |
| 825 | if (s->num_lock_mode == 2) { |
| 826 | return; /* Drop second press */ |
| 827 | } |
| 828 | } else { |
| 829 | s->num_lock_mode ^= 2; |
| 830 | if (s->num_lock_mode == 3) { |
| 831 | return; /* Drop first release */ |
| 832 | } |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | if (evt->key.key >= qemu_input_map_linux_to_sun_len) { |
| 837 | return; |
| 838 | } |
| 839 | |
| 840 | keycode = qemu_input_map_linux_to_sun[evt->key.key]; |
| 841 | if (!evt->key.down) { |
| 842 | keycode |= 0x80; |
| 843 | } |
| 844 | trace_escc_sunkbd_event_out(keycode); |
| 845 | put_queue(s, keycode); |
| 846 | } |
| 847 | |
| 848 | static const QemuInputHandler sunkbd_handler = { |
| 849 | .name = "sun keyboard", |
| 850 | .mask = INPUT_EVENT_MASK_KEY, |
| 851 | .event = sunkbd_handle_event, |
| 852 | }; |
| 853 | |
| 854 | static uint8_t sunkbd_layout_dip_switch(const char *kbd_layout) |
| 855 | { |
| 856 | /* Return the value of the dip-switches in a SUN Type 5 keyboard */ |
| 857 | static uint8_t ret = 0xff; |
| 858 | |
| 859 | if ((ret == 0xff) && kbd_layout) { |
| 860 | int i; |
| 861 | struct layout_values { |
| 862 | const char *lang; |
| 863 | uint8_t dip; |
| 864 | } languages[] = |
| 865 | /* |
| 866 | * Dip values from table 3-16 Layouts for Type 4, 5 and 5c Keyboards |
| 867 | */ |
| 868 | { |
| 869 | {"en-us", 0x21}, /* U.S.A. (US5.kt) */ |
| 870 | /* 0x22 is some other US (US_UNIX5.kt) */ |
| 871 | {"fr", 0x23}, /* France (France5.kt) */ |
| 872 | {"da", 0x24}, /* Denmark (Denmark5.kt) */ |
| 873 | {"de", 0x25}, /* Germany (Germany5.kt) */ |
| 874 | {"it", 0x26}, /* Italy (Italy5.kt) */ |
| 875 | {"nl", 0x27}, /* The Netherlands (Netherland5.kt) */ |
| 876 | {"no", 0x28}, /* Norway (Norway.kt) */ |
| 877 | {"pt", 0x29}, /* Portugal (Portugal5.kt) */ |
| 878 | {"es", 0x2a}, /* Spain (Spain5.kt) */ |
| 879 | {"sv", 0x2b}, /* Sweden (Sweden5.kt) */ |
| 880 | {"fr-ch", 0x2c}, /* Switzerland/French (Switzer_Fr5.kt) */ |
| 881 | {"de-ch", 0x2d}, /* Switzerland/German (Switzer_Ge5.kt) */ |
| 882 | {"en-gb", 0x2e}, /* Great Britain (UK5.kt) */ |
| 883 | {"ko", 0x2f}, /* Korea (Korea5.kt) */ |
| 884 | {"tw", 0x30}, /* Taiwan (Taiwan5.kt) */ |
| 885 | {"ja", 0x31}, /* Japan (Japan5.kt) */ |
| 886 | {"fr-ca", 0x32}, /* Canada/French (Canada_Fr5.kt) */ |
| 887 | {"hu", 0x33}, /* Hungary (Hungary5.kt) */ |
| 888 | {"pl", 0x34}, /* Poland (Poland5.kt) */ |
| 889 | {"cz", 0x35}, /* Czech (Czech5.kt) */ |
| 890 | {"ru", 0x36}, /* Russia (Russia5.kt) */ |
| 891 | {"lv", 0x37}, /* Latvia (Latvia5.kt) */ |
| 892 | {"tr", 0x38}, /* Turkey-Q5 (TurkeyQ5.kt) */ |
| 893 | {"gr", 0x39}, /* Greece (Greece5.kt) */ |
| 894 | {"ar", 0x3a}, /* Arabic (Arabic5.kt) */ |
| 895 | {"lt", 0x3b}, /* Lithuania (Lithuania5.kt) */ |
| 896 | {"nl-be", 0x3c}, /* Belgium (Belgian5.kt) */ |
| 897 | {"be", 0x3c}, /* Belgium (Belgian5.kt) */ |
| 898 | }; |
| 899 | |
| 900 | for (i = 0; |
| 901 | i < sizeof(languages) / sizeof(struct layout_values); |
| 902 | i++) { |
| 903 | if (!strcmp(kbd_layout, languages[i].lang)) { |
| 904 | ret = languages[i].dip; |
| 905 | return ret; |
| 906 | } |
| 907 | } |
| 908 | |
| 909 | /* Found no known language code */ |
| 910 | if ((kbd_layout[0] >= '0') && (kbd_layout[0] <= '9')) { |
| 911 | unsigned int tmp; |
| 912 | |
| 913 | /* As a fallback we also accept numeric dip switch value */ |
| 914 | if (!qemu_strtoui(kbd_layout, NULL, 0, &tmp)) { |
| 915 | ret = tmp; |
| 916 | } |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | if (ret == 0xff) { |
| 921 | /* Final fallback if keyboard_layout was not set or recognized */ |
| 922 | ret = 0x21; /* en-us layout */ |
| 923 | } |
| 924 | return ret; |
| 925 | } |
| 926 | |
| 927 | static void handle_kbd_command(ESCCChannelState *s, int val) |
| 928 | { |
| 929 | trace_escc_kbd_command(val); |
| 930 | if (s->led_mode) { /* Ignore led byte */ |
| 931 | s->led_mode = 0; |
| 932 | return; |
| 933 | } |
| 934 | switch (val) { |
| 935 | case 1: /* Reset, return type code */ |
| 936 | clear_queue(s); |
| 937 | put_queue(s, 0xff); |
| 938 | put_queue(s, 4); /* Type 4 */ |
| 939 | put_queue(s, 0x7f); |
| 940 | break; |
| 941 | case 0xe: /* Set leds */ |
| 942 | s->led_mode = 1; |
| 943 | break; |
| 944 | case 7: /* Query layout */ |
| 945 | case 0xf: |
| 946 | clear_queue(s); |
| 947 | put_queue(s, 0xfe); |
| 948 | put_queue(s, sunkbd_layout_dip_switch(s->sunkbd_layout)); |
| 949 | break; |
| 950 | default: |
| 951 | break; |
| 952 | } |
| 953 | } |
| 954 | |
| 955 | static void sunmouse_handle_event(DeviceState *dev, QemuConsole *src, |
| 956 | QemuInputEvent *evt) |
| 957 | { |
| 958 | ESCCChannelState *s = (ESCCChannelState *)dev; |
| 959 | static const int bmap[INPUT_BUTTON__MAX] = { |
| 960 | [INPUT_BUTTON_LEFT] = 0x4, |
| 961 | [INPUT_BUTTON_MIDDLE] = 0x2, |
| 962 | [INPUT_BUTTON_RIGHT] = 0x1, |
| 963 | }; |
| 964 | |
| 965 | switch (evt->type) { |
| 966 | case INPUT_EVENT_KIND_REL: |
| 967 | if (evt->rel.axis == INPUT_AXIS_X) { |
| 968 | s->sunmouse_dx += evt->rel.value; |
| 969 | } else if (evt->rel.axis == INPUT_AXIS_Y) { |
| 970 | s->sunmouse_dy -= evt->rel.value; |
| 971 | } |
| 972 | break; |
| 973 | |
| 974 | case INPUT_EVENT_KIND_BTN: |
| 975 | if (bmap[evt->btn.button]) { |
| 976 | if (evt->btn.down) { |
| 977 | s->sunmouse_buttons |= bmap[evt->btn.button]; |
| 978 | } else { |
| 979 | s->sunmouse_buttons &= ~bmap[evt->btn.button]; |
| 980 | } |
| 981 | /* Indicate we have a supported button event */ |
| 982 | s->sunmouse_buttons |= 0x80; |
| 983 | } |
| 984 | break; |
| 985 | |
| 986 | default: |
| 987 | /* keep gcc happy */ |
| 988 | break; |
| 989 | } |
| 990 | } |
| 991 | |
| 992 | static void sunmouse_sync(DeviceState *dev) |
| 993 | { |
| 994 | ESCCChannelState *s = (ESCCChannelState *)dev; |
| 995 | int ch; |
| 996 | |
| 997 | if (s->sunmouse_dx == 0 && s->sunmouse_dy == 0 && |
| 998 | (s->sunmouse_buttons & 0x80) == 0) { |
| 999 | /* Nothing to do after button event filter */ |
| 1000 | return; |
| 1001 | } |
| 1002 | |
| 1003 | /* Clear our button event flag */ |
| 1004 | s->sunmouse_buttons &= ~0x80; |
| 1005 | trace_escc_sunmouse_event(s->sunmouse_dx, s->sunmouse_dy, |
| 1006 | s->sunmouse_buttons); |
| 1007 | ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ |
| 1008 | ch ^= s->sunmouse_buttons; |
| 1009 | put_queue(s, ch); |
| 1010 | |
| 1011 | ch = s->sunmouse_dx; |
| 1012 | if (ch > 127) { |
| 1013 | ch = 127; |
| 1014 | } else if (ch < -127) { |
| 1015 | ch = -127; |
| 1016 | } |
| 1017 | put_queue(s, ch & 0xff); |
| 1018 | s->sunmouse_dx -= ch; |
| 1019 | |
| 1020 | ch = s->sunmouse_dy; |
| 1021 | if (ch > 127) { |
| 1022 | ch = 127; |
| 1023 | } else if (ch < -127) { |
| 1024 | ch = -127; |
| 1025 | } |
| 1026 | put_queue(s, ch & 0xff); |
| 1027 | s->sunmouse_dy -= ch; |
| 1028 | |
| 1029 | /* MSC protocol specifies two extra motion bytes */ |
| 1030 | put_queue(s, 0); |
| 1031 | put_queue(s, 0); |
| 1032 | } |
| 1033 | |
| 1034 | static const QemuInputHandler sunmouse_handler = { |
| 1035 | .name = "QEMU Sun Mouse", |
| 1036 | .mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL, |
| 1037 | .event = sunmouse_handle_event, |
| 1038 | .sync = sunmouse_sync, |
| 1039 | }; |
| 1040 | |
| 1041 | static void escc_init1(Object *obj) |
| 1042 | { |
| 1043 | ESCCState *s = ESCC(obj); |
| 1044 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
| 1045 | unsigned int i; |
| 1046 | |
| 1047 | for (i = 0; i < 2; i++) { |
| 1048 | sysbus_init_irq(dev, &s->chn[i].irq); |
| 1049 | s->chn[i].chn = 1 - i; |
| 1050 | } |
| 1051 | s->chn[0].otherchn = &s->chn[1]; |
| 1052 | s->chn[1].otherchn = &s->chn[0]; |
| 1053 | |
| 1054 | sysbus_init_mmio(dev, &s->mmio); |
| 1055 | } |
| 1056 | |
| 1057 | static void escc_realize(DeviceState *dev, Error **errp) |
| 1058 | { |
| 1059 | ESCCState *s = ESCC(dev); |
| 1060 | unsigned int i; |
| 1061 | |
| 1062 | s->chn[0].disabled = s->disabled; |
| 1063 | s->chn[1].disabled = s->disabled; |
| 1064 | |
| 1065 | memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc", |
| 1066 | ESCC_SIZE << s->it_shift); |
| 1067 | |
| 1068 | for (i = 0; i < 2; i++) { |
| 1069 | if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) { |
| 1070 | s->chn[i].clock = s->frequency / 2; |
| 1071 | qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive, |
| 1072 | serial_receive1, serial_event, NULL, |
| 1073 | &s->chn[i], NULL, true); |
| 1074 | } |
| 1075 | } |
| 1076 | |
| 1077 | if (s->chn[0].type == escc_mouse) { |
| 1078 | s->chn[0].hs = qemu_input_handler_register((DeviceState *)(&s->chn[0]), |
| 1079 | &sunmouse_handler); |
| 1080 | } |
| 1081 | if (s->chn[1].type == escc_kbd) { |
| 1082 | s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]), |
| 1083 | &sunkbd_handler); |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | static const Property escc_properties[] = { |
| 1088 | DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), |
| 1089 | DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), |
| 1090 | DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), |
| 1091 | DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), |
| 1092 | DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), |
| 1093 | DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), |
| 1094 | DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr), |
| 1095 | DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr), |
| 1096 | DEFINE_PROP_STRING("chnA-sunkbd-layout", ESCCState, chn[1].sunkbd_layout), |
| 1097 | }; |
| 1098 | |
| 1099 | static void escc_class_init(ObjectClass *klass, const void *data) |
| 1100 | { |
| 1101 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1102 | |
| 1103 | device_class_set_legacy_reset(dc, escc_reset); |
| 1104 | dc->realize = escc_realize; |
| 1105 | dc->vmsd = &vmstate_escc; |
| 1106 | device_class_set_props(dc, escc_properties); |
| 1107 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
| 1108 | } |
| 1109 | |
| 1110 | static const TypeInfo escc_info = { |
| 1111 | .name = TYPE_ESCC, |
| 1112 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1113 | .instance_size = sizeof(ESCCState), |
| 1114 | .instance_init = escc_init1, |
| 1115 | .class_init = escc_class_init, |
| 1116 | }; |
| 1117 | |
| 1118 | static void escc_register_types(void) |
| 1119 | { |
| 1120 | type_register_static(&escc_info); |
| 1121 | } |
| 1122 | |
| 1123 | type_init(escc_register_types) |