| 1 | /* |
| 2 | * IMX31 UARTS |
| 3 | * |
| 4 | * Copyright (c) 2008 OKL |
| 5 | * Originally Written by Hans Jiang |
| 6 | * Copyright (c) 2011 NICTA Pty Ltd. |
| 7 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
| 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | * |
| 12 | * This is a `bare-bones' implementation of the IMX series serial ports. |
| 13 | * TODO: |
| 14 | * -- implement FIFOs. The real hardware has 32 word transmit |
| 15 | * and receive FIFOs; we currently use a 1-char buffer |
| 16 | * -- implement DMA |
| 17 | * -- implement BAUD-rate and modem lines, for when the backend |
| 18 | * is a real serial device. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "hw/char/imx_serial.h" |
| 23 | #include "hw/core/irq.h" |
| 24 | #include "hw/core/qdev-properties.h" |
| 25 | #include "hw/core/qdev-properties-system.h" |
| 26 | #include "migration/vmstate.h" |
| 27 | #include "qemu/log.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "qemu/fifo32.h" |
| 30 | #include "trace.h" |
| 31 | |
| 32 | #ifndef DEBUG_IMX_UART |
| 33 | #define DEBUG_IMX_UART 0 |
| 34 | #endif |
| 35 | |
| 36 | #define DPRINTF(fmt, args...) \ |
| 37 | do { \ |
| 38 | if (DEBUG_IMX_UART) { \ |
| 39 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ |
| 40 | __func__, ##args); \ |
| 41 | } \ |
| 42 | } while (0) |
| 43 | |
| 44 | static const VMStateDescription vmstate_imx_serial = { |
| 45 | .name = TYPE_IMX_SERIAL, |
| 46 | .version_id = 4, |
| 47 | .minimum_version_id = 4, |
| 48 | .fields = (const VMStateField[]) { |
| 49 | VMSTATE_FIFO32(rx_fifo, IMXSerialState), |
| 50 | VMSTATE_TIMER(ageing_timer, IMXSerialState), |
| 51 | VMSTATE_UINT32(usr1, IMXSerialState), |
| 52 | VMSTATE_UINT32(usr2, IMXSerialState), |
| 53 | VMSTATE_UINT32(ucr1, IMXSerialState), |
| 54 | VMSTATE_UINT32(ucr2, IMXSerialState), |
| 55 | VMSTATE_UINT32(uts1, IMXSerialState), |
| 56 | VMSTATE_UINT32(onems, IMXSerialState), |
| 57 | VMSTATE_UINT32(ufcr, IMXSerialState), |
| 58 | VMSTATE_UINT32(ubmr, IMXSerialState), |
| 59 | VMSTATE_UINT32(ubrc, IMXSerialState), |
| 60 | VMSTATE_UINT32(ucr3, IMXSerialState), |
| 61 | VMSTATE_UINT32(ucr4, IMXSerialState), |
| 62 | VMSTATE_END_OF_LIST() |
| 63 | }, |
| 64 | }; |
| 65 | |
| 66 | static void imx_update(IMXSerialState *s) |
| 67 | { |
| 68 | uint32_t usr1; |
| 69 | uint32_t usr2; |
| 70 | uint32_t mask; |
| 71 | |
| 72 | /* |
| 73 | * Lucky for us TRDY and RRDY has the same offset in both USR1 and |
| 74 | * UCR1, so we can get away with something as simple as the |
| 75 | * following: |
| 76 | */ |
| 77 | usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); |
| 78 | /* |
| 79 | * Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO) |
| 80 | */ |
| 81 | usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; |
| 82 | /* |
| 83 | * Bits that we want in USR2 are not as conveniently laid out, |
| 84 | * unfortunately. |
| 85 | */ |
| 86 | mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; |
| 87 | /* |
| 88 | * TCEN and TXDC are both bit 3 |
| 89 | * ORE and OREN are both bit 1 |
| 90 | * RDR and DREN are both bit 0 |
| 91 | */ |
| 92 | mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN); |
| 93 | |
| 94 | usr2 = s->usr2 & mask; |
| 95 | |
| 96 | qemu_set_irq(s->irq, usr1 || usr2); |
| 97 | } |
| 98 | |
| 99 | static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value) |
| 100 | { |
| 101 | uint32_t pushed_value = value; |
| 102 | if (fifo32_is_full(&s->rx_fifo)) { |
| 103 | /* Set ORE if FIFO is already full */ |
| 104 | s->usr2 |= USR2_ORE; |
| 105 | } else { |
| 106 | if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) { |
| 107 | /* Set OVRRUN on 32nd character in FIFO */ |
| 108 | pushed_value |= URXD_ERR | URXD_OVRRUN; |
| 109 | } |
| 110 | fifo32_push(&s->rx_fifo, pushed_value); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s) |
| 115 | { |
| 116 | if (fifo32_is_empty(&s->rx_fifo)) { |
| 117 | return 0; |
| 118 | } |
| 119 | return fifo32_pop(&s->rx_fifo); |
| 120 | } |
| 121 | |
| 122 | static void imx_serial_rx_fifo_ageing_timer_int(void *opaque) |
| 123 | { |
| 124 | IMXSerialState *s = (IMXSerialState *) opaque; |
| 125 | s->usr1 |= USR1_AGTIM; |
| 126 | imx_update(s); |
| 127 | } |
| 128 | |
| 129 | static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque) |
| 130 | { |
| 131 | /* |
| 132 | * Ageing timer starts ticking when |
| 133 | * RX FIFO is non empty and below trigger level. |
| 134 | * Timer is reset if new character is received or |
| 135 | * a FIFO read occurs. |
| 136 | * Timer triggers an interrupt when duration of |
| 137 | * 8 characters has passed (assuming 115200 baudrate). |
| 138 | */ |
| 139 | IMXSerialState *s = (IMXSerialState *) opaque; |
| 140 | |
| 141 | if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) { |
| 142 | timer_mod_ns(&s->ageing_timer, |
| 143 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS); |
| 144 | } else { |
| 145 | timer_del(&s->ageing_timer); |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | static void imx_serial_reset(IMXSerialState *s) |
| 150 | { |
| 151 | |
| 152 | s->usr1 = USR1_TRDY | USR1_RXDS; |
| 153 | /* |
| 154 | * Fake attachment of a terminal: assert RTS. |
| 155 | */ |
| 156 | s->usr1 |= USR1_RTSS; |
| 157 | s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; |
| 158 | s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; |
| 159 | s->ucr1 = 0; |
| 160 | s->ucr2 = UCR2_SRST; |
| 161 | s->ucr3 = 0x700; |
| 162 | s->ubmr = 0; |
| 163 | s->ubrc = 4; |
| 164 | s->ufcr = BIT(11) | BIT(0); |
| 165 | |
| 166 | fifo32_reset(&s->rx_fifo); |
| 167 | timer_del(&s->ageing_timer); |
| 168 | } |
| 169 | |
| 170 | static void imx_serial_reset_at_boot(DeviceState *dev) |
| 171 | { |
| 172 | IMXSerialState *s = IMX_SERIAL(dev); |
| 173 | |
| 174 | imx_serial_reset(s); |
| 175 | |
| 176 | /* |
| 177 | * enable the uart on boot, so messages from the linux decompressor |
| 178 | * are visible. On real hardware this is done by the boot rom |
| 179 | * before anything else is loaded. |
| 180 | */ |
| 181 | s->ucr1 = UCR1_UARTEN; |
| 182 | s->ucr2 = UCR2_TXEN; |
| 183 | |
| 184 | } |
| 185 | |
| 186 | static uint64_t imx_serial_read(void *opaque, hwaddr offset, |
| 187 | unsigned size) |
| 188 | { |
| 189 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 190 | Chardev *chr = qemu_chr_fe_get_driver(&s->chr); |
| 191 | uint32_t c, rx_used; |
| 192 | uint8_t rxtl = s->ufcr & TL_MASK; |
| 193 | uint64_t value; |
| 194 | |
| 195 | switch (offset >> 2) { |
| 196 | case 0x0: /* URXD */ |
| 197 | c = imx_serial_rx_fifo_pop(s); |
| 198 | if (!(s->uts1 & UTS1_RXEMPTY)) { |
| 199 | /* Character is valid */ |
| 200 | c |= URXD_CHARRDY; |
| 201 | rx_used = fifo32_num_used(&s->rx_fifo); |
| 202 | /* Clear RRDY if below threshold */ |
| 203 | if (rx_used < rxtl) { |
| 204 | s->usr1 &= ~USR1_RRDY; |
| 205 | } |
| 206 | if (rx_used == 0) { |
| 207 | s->usr2 &= ~USR2_RDR; |
| 208 | s->uts1 |= UTS1_RXEMPTY; |
| 209 | } |
| 210 | imx_update(s); |
| 211 | imx_serial_rx_fifo_ageing_timer_restart(s); |
| 212 | qemu_chr_fe_accept_input(&s->chr); |
| 213 | } |
| 214 | value = c; |
| 215 | break; |
| 216 | |
| 217 | case 0x20: /* UCR1 */ |
| 218 | value = s->ucr1; |
| 219 | break; |
| 220 | |
| 221 | case 0x21: /* UCR2 */ |
| 222 | value = s->ucr2; |
| 223 | break; |
| 224 | |
| 225 | case 0x25: /* USR1 */ |
| 226 | value = s->usr1; |
| 227 | break; |
| 228 | |
| 229 | case 0x26: /* USR2 */ |
| 230 | value = s->usr2; |
| 231 | break; |
| 232 | |
| 233 | case 0x2A: /* BRM Modulator */ |
| 234 | value = s->ubmr; |
| 235 | break; |
| 236 | |
| 237 | case 0x2B: /* Baud Rate Count */ |
| 238 | value = s->ubrc; |
| 239 | break; |
| 240 | |
| 241 | case 0x2d: /* Test register */ |
| 242 | value = s->uts1; |
| 243 | break; |
| 244 | |
| 245 | case 0x24: /* UFCR */ |
| 246 | value = s->ufcr; |
| 247 | break; |
| 248 | |
| 249 | case 0x2c: |
| 250 | value = s->onems; |
| 251 | break; |
| 252 | |
| 253 | case 0x22: /* UCR3 */ |
| 254 | value = s->ucr3; |
| 255 | break; |
| 256 | |
| 257 | case 0x23: /* UCR4 */ |
| 258 | value = s->ucr4; |
| 259 | break; |
| 260 | |
| 261 | case 0x29: /* BRM Incremental */ |
| 262 | value = 0x0; /* TODO */ |
| 263 | break; |
| 264 | |
| 265 | default: |
| 266 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 267 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
| 268 | value = 0; |
| 269 | break; |
| 270 | } |
| 271 | |
| 272 | trace_imx_serial_read(chr ? chr->label : "NODEV", offset, value); |
| 273 | |
| 274 | return value; |
| 275 | } |
| 276 | |
| 277 | static void imx_serial_write(void *opaque, hwaddr offset, |
| 278 | uint64_t value, unsigned size) |
| 279 | { |
| 280 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 281 | g_autofree char *label = qemu_chr_fe_backend_name(&s->chr); |
| 282 | unsigned char ch; |
| 283 | |
| 284 | trace_imx_serial_write(label ? label : "NODEV", offset, value); |
| 285 | |
| 286 | switch (offset >> 2) { |
| 287 | case 0x10: /* UTXD */ |
| 288 | ch = value; |
| 289 | if (s->ucr2 & UCR2_TXEN) { |
| 290 | /* XXX this blocks entire thread. Rewrite to use |
| 291 | * qemu_chr_fe_write and background I/O callbacks */ |
| 292 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
| 293 | s->usr1 &= ~USR1_TRDY; |
| 294 | s->usr2 &= ~USR2_TXDC; |
| 295 | imx_update(s); |
| 296 | s->usr1 |= USR1_TRDY; |
| 297 | s->usr2 |= USR2_TXDC; |
| 298 | imx_update(s); |
| 299 | } |
| 300 | break; |
| 301 | |
| 302 | case 0x20: /* UCR1 */ |
| 303 | s->ucr1 = value & 0xffff; |
| 304 | |
| 305 | DPRINTF("write(ucr1=%x)\n", (unsigned int)value); |
| 306 | |
| 307 | imx_update(s); |
| 308 | break; |
| 309 | |
| 310 | case 0x21: /* UCR2 */ |
| 311 | /* |
| 312 | * Only a few bits in control register 2 are implemented as yet. |
| 313 | * If it's intended to use a real serial device as a back-end, this |
| 314 | * register will have to be implemented more fully. |
| 315 | */ |
| 316 | if (!(value & UCR2_SRST)) { |
| 317 | imx_serial_reset(s); |
| 318 | imx_update(s); |
| 319 | value |= UCR2_SRST; |
| 320 | } |
| 321 | if (value & UCR2_RXEN) { |
| 322 | if (!(s->ucr2 & UCR2_RXEN)) { |
| 323 | qemu_chr_fe_accept_input(&s->chr); |
| 324 | } |
| 325 | } |
| 326 | s->ucr2 = value & 0xffff; |
| 327 | break; |
| 328 | |
| 329 | case 0x25: /* USR1 */ |
| 330 | value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | |
| 331 | USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; |
| 332 | s->usr1 &= ~value; |
| 333 | break; |
| 334 | |
| 335 | case 0x26: /* USR2 */ |
| 336 | /* |
| 337 | * Writing 1 to some bits clears them; all other |
| 338 | * values are ignored |
| 339 | */ |
| 340 | value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | |
| 341 | USR2_RIDELT | USR2_IRINT | USR2_WAKE | |
| 342 | USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; |
| 343 | s->usr2 &= ~value; |
| 344 | break; |
| 345 | |
| 346 | /* |
| 347 | * Linux expects to see what it writes to these registers |
| 348 | * We don't currently alter the baud rate |
| 349 | */ |
| 350 | case 0x29: /* UBIR */ |
| 351 | s->ubrc = value & 0xffff; |
| 352 | break; |
| 353 | |
| 354 | case 0x2a: /* UBMR */ |
| 355 | s->ubmr = value & 0xffff; |
| 356 | break; |
| 357 | |
| 358 | case 0x2c: /* One ms reg */ |
| 359 | s->onems = value & 0xffff; |
| 360 | break; |
| 361 | |
| 362 | case 0x24: /* FIFO control register */ |
| 363 | s->ufcr = value & 0xffff; |
| 364 | break; |
| 365 | |
| 366 | case 0x22: /* UCR3 */ |
| 367 | s->ucr3 = value & 0xffff; |
| 368 | break; |
| 369 | |
| 370 | case 0x23: /* UCR4 */ |
| 371 | s->ucr4 = value & 0xffff; |
| 372 | imx_update(s); |
| 373 | break; |
| 374 | |
| 375 | case 0x2d: /* UTS1 */ |
| 376 | qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" |
| 377 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
| 378 | /* TODO */ |
| 379 | break; |
| 380 | |
| 381 | default: |
| 382 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 383 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | static int imx_can_receive(void *opaque) |
| 388 | { |
| 389 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 390 | |
| 391 | return s->ucr2 & UCR2_RXEN ? fifo32_num_free(&s->rx_fifo) : 0; |
| 392 | } |
| 393 | |
| 394 | static void imx_put_data(void *opaque, uint32_t value) |
| 395 | { |
| 396 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 397 | Chardev *chr = qemu_chr_fe_get_driver(&s->chr); |
| 398 | uint8_t rxtl = s->ufcr & TL_MASK; |
| 399 | |
| 400 | trace_imx_serial_put_data(chr ? chr->label : "NODEV", value); |
| 401 | |
| 402 | imx_serial_rx_fifo_push(s, value); |
| 403 | if (fifo32_num_used(&s->rx_fifo) >= rxtl) { |
| 404 | s->usr1 |= USR1_RRDY; |
| 405 | } |
| 406 | s->usr2 |= USR2_RDR; |
| 407 | s->uts1 &= ~UTS1_RXEMPTY; |
| 408 | if (value & URXD_BRK) { |
| 409 | s->usr2 |= USR2_BRCD; |
| 410 | } |
| 411 | |
| 412 | imx_serial_rx_fifo_ageing_timer_restart(s); |
| 413 | |
| 414 | imx_update(s); |
| 415 | } |
| 416 | |
| 417 | static void imx_receive(void *opaque, const uint8_t *buf, int size) |
| 418 | { |
| 419 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 420 | |
| 421 | s->usr2 |= USR2_WAKE; |
| 422 | |
| 423 | for (int i = 0; i < size; i++) { |
| 424 | imx_put_data(opaque, buf[i]); |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | static void imx_event(void *opaque, QEMUChrEvent event) |
| 429 | { |
| 430 | if (event == CHR_EVENT_BREAK) { |
| 431 | imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | |
| 436 | static const struct MemoryRegionOps imx_serial_ops = { |
| 437 | .read = imx_serial_read, |
| 438 | .write = imx_serial_write, |
| 439 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 440 | }; |
| 441 | |
| 442 | static void imx_serial_realize(DeviceState *dev, Error **errp) |
| 443 | { |
| 444 | IMXSerialState *s = IMX_SERIAL(dev); |
| 445 | |
| 446 | fifo32_create(&s->rx_fifo, FIFO_SIZE); |
| 447 | timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, |
| 448 | imx_serial_rx_fifo_ageing_timer_int, s); |
| 449 | |
| 450 | DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); |
| 451 | |
| 452 | qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, |
| 453 | imx_event, NULL, s, NULL, true); |
| 454 | } |
| 455 | |
| 456 | static void imx_serial_init(Object *obj) |
| 457 | { |
| 458 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 459 | IMXSerialState *s = IMX_SERIAL(obj); |
| 460 | |
| 461 | memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, |
| 462 | TYPE_IMX_SERIAL, 0x1000); |
| 463 | sysbus_init_mmio(sbd, &s->iomem); |
| 464 | sysbus_init_irq(sbd, &s->irq); |
| 465 | } |
| 466 | |
| 467 | static const Property imx_serial_properties[] = { |
| 468 | DEFINE_PROP_CHR("chardev", IMXSerialState, chr), |
| 469 | }; |
| 470 | |
| 471 | static void imx_serial_class_init(ObjectClass *klass, const void *data) |
| 472 | { |
| 473 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 474 | |
| 475 | dc->realize = imx_serial_realize; |
| 476 | dc->vmsd = &vmstate_imx_serial; |
| 477 | device_class_set_legacy_reset(dc, imx_serial_reset_at_boot); |
| 478 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
| 479 | dc->desc = "i.MX series UART"; |
| 480 | device_class_set_props(dc, imx_serial_properties); |
| 481 | } |
| 482 | |
| 483 | static const TypeInfo imx_serial_info = { |
| 484 | .name = TYPE_IMX_SERIAL, |
| 485 | .parent = TYPE_SYS_BUS_DEVICE, |
| 486 | .instance_size = sizeof(IMXSerialState), |
| 487 | .instance_init = imx_serial_init, |
| 488 | .class_init = imx_serial_class_init, |
| 489 | }; |
| 490 | |
| 491 | static void imx_serial_register_types(void) |
| 492 | { |
| 493 | type_register_static(&imx_serial_info); |
| 494 | } |
| 495 | |
| 496 | type_init(imx_serial_register_types) |