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1 /*
2 * nRF51 SoC UART emulation
3 *
4 * See nRF51 Series Reference Manual, "29 Universal Asynchronous
5 * Receiver/Transmitter" for hardware specifications:
6 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
7 *
8 * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 or
12 * (at your option) any later version.
13 */
14
15 #include "qemu/osdep.h"
16 #include "qemu/log.h"
17 #include "qemu/module.h"
18 #include "hw/char/nrf51_uart.h"
19 #include "hw/core/irq.h"
20 #include "hw/core/qdev-properties.h"
21 #include "hw/core/qdev-properties-system.h"
22 #include "migration/vmstate.h"
23 #include "trace.h"
24
25 static void nrf51_uart_update_irq(NRF51UARTState *s)
26 {
27 bool irq = false;
28
29 irq |= (s->reg[R_UART_RXDRDY] &&
30 (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
31 irq |= (s->reg[R_UART_TXDRDY] &&
32 (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
33 irq |= (s->reg[R_UART_ERROR] &&
34 (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
35 irq |= (s->reg[R_UART_RXTO] &&
36 (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
37
38 qemu_set_irq(s->irq, irq);
39 }
40
41 static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
42 {
43 NRF51UARTState *s = NRF51_UART(opaque);
44 uint64_t r;
45
46 if (!s->enabled) {
47 return 0;
48 }
49
50 switch (addr) {
51 case A_UART_RXD:
52 r = s->rx_fifo[s->rx_fifo_pos];
53 if (s->rx_started && s->rx_fifo_len) {
54 s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
55 s->rx_fifo_len--;
56 if (s->rx_fifo_len) {
57 s->reg[R_UART_RXDRDY] = 1;
58 nrf51_uart_update_irq(s);
59 }
60 qemu_chr_fe_accept_input(&s->chr);
61 }
62 break;
63 case A_UART_INTENSET:
64 case A_UART_INTENCLR:
65 case A_UART_INTEN:
66 r = s->reg[R_UART_INTEN];
67 break;
68 default:
69 r = s->reg[addr / 4];
70 break;
71 }
72
73 trace_nrf51_uart_read(addr, r, size);
74
75 return r;
76 }
77
78 static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
79 {
80 NRF51UARTState *s = NRF51_UART(opaque);
81 int r;
82 uint8_t c = s->reg[R_UART_TXD];
83
84 s->watch_tag = 0;
85
86 r = qemu_chr_fe_write(&s->chr, &c, 1);
87 if (r <= 0) {
88 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
89 uart_transmit, s);
90 if (!s->watch_tag) {
91 /* The hardware has no transmit error reporting,
92 * so silently drop the byte
93 */
94 goto buffer_drained;
95 }
96 return G_SOURCE_REMOVE;
97 }
98
99 buffer_drained:
100 s->reg[R_UART_TXDRDY] = 1;
101 s->pending_tx_byte = false;
102 return G_SOURCE_REMOVE;
103 }
104
105 static void uart_cancel_transmit(NRF51UARTState *s)
106 {
107 g_clear_handle_id(&s->watch_tag, g_source_remove);
108 }
109
110 static void uart_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned int size)
112 {
113 NRF51UARTState *s = NRF51_UART(opaque);
114
115 trace_nrf51_uart_write(addr, value, size);
116
117 if (!s->enabled && (addr != A_UART_ENABLE)) {
118 return;
119 }
120
121 switch (addr) {
122 case A_UART_TXD:
123 if (!s->pending_tx_byte && s->tx_started) {
124 s->reg[R_UART_TXD] = value;
125 s->pending_tx_byte = true;
126 uart_transmit(NULL, G_IO_OUT, s);
127 }
128 break;
129 case A_UART_INTEN:
130 s->reg[R_UART_INTEN] = value;
131 break;
132 case A_UART_INTENSET:
133 s->reg[R_UART_INTEN] |= value;
134 break;
135 case A_UART_INTENCLR:
136 s->reg[R_UART_INTEN] &= ~value;
137 break;
138 case A_UART_TXDRDY ... A_UART_RXTO:
139 s->reg[addr / 4] = value;
140 break;
141 case A_UART_ERRORSRC:
142 s->reg[addr / 4] &= ~value;
143 break;
144 case A_UART_RXD:
145 break;
146 case A_UART_RXDRDY:
147 if (value == 0) {
148 s->reg[R_UART_RXDRDY] = 0;
149 }
150 break;
151 case A_UART_STARTTX:
152 if (value == 1) {
153 s->tx_started = true;
154 }
155 break;
156 case A_UART_STARTRX:
157 if (value == 1) {
158 s->rx_started = true;
159 }
160 break;
161 case A_UART_ENABLE:
162 if (value) {
163 if (value == 4) {
164 s->enabled = true;
165 }
166 break;
167 }
168 s->enabled = false;
169 value = 1;
170 /* fall through */
171 case A_UART_SUSPEND:
172 case A_UART_STOPTX:
173 if (value == 1) {
174 s->tx_started = false;
175 }
176 /* fall through */
177 case A_UART_STOPRX:
178 if (addr != A_UART_STOPTX && value == 1) {
179 s->rx_started = false;
180 s->reg[R_UART_RXTO] = 1;
181 }
182 break;
183 default:
184 s->reg[addr / 4] = value;
185 break;
186 }
187 nrf51_uart_update_irq(s);
188 }
189
190 static const MemoryRegionOps uart_ops = {
191 .read = uart_read,
192 .write = uart_write,
193 .endianness = DEVICE_LITTLE_ENDIAN,
194 };
195
196 static void nrf51_uart_reset(DeviceState *dev)
197 {
198 NRF51UARTState *s = NRF51_UART(dev);
199
200 s->pending_tx_byte = 0;
201
202 uart_cancel_transmit(s);
203
204 memset(s->reg, 0, sizeof(s->reg));
205
206 s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
207 s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
208 s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
209 s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
210 s->reg[R_UART_BAUDRATE] = 0x4000000;
211
212 s->rx_fifo_len = 0;
213 s->rx_fifo_pos = 0;
214 s->rx_started = false;
215 s->tx_started = false;
216 s->enabled = false;
217 }
218
219 static void uart_receive(void *opaque, const uint8_t *buf, int size)
220 {
221
222 NRF51UARTState *s = NRF51_UART(opaque);
223 int i;
224
225 if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
226 return;
227 }
228
229 for (i = 0; i < size; i++) {
230 uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
231 s->rx_fifo[pos] = buf[i];
232 s->rx_fifo_len++;
233 }
234
235 s->reg[R_UART_RXDRDY] = 1;
236 nrf51_uart_update_irq(s);
237 }
238
239 static int uart_can_receive(void *opaque)
240 {
241 NRF51UARTState *s = NRF51_UART(opaque);
242
243 return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
244 }
245
246 static void uart_event(void *opaque, QEMUChrEvent event)
247 {
248 NRF51UARTState *s = NRF51_UART(opaque);
249
250 if (event == CHR_EVENT_BREAK) {
251 s->reg[R_UART_ERRORSRC] |= 3;
252 s->reg[R_UART_ERROR] = 1;
253 nrf51_uart_update_irq(s);
254 }
255 }
256
257 static void nrf51_uart_realize(DeviceState *dev, Error **errp)
258 {
259 NRF51UARTState *s = NRF51_UART(dev);
260
261 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
262 uart_event, NULL, s, NULL, true);
263 }
264
265 static void nrf51_uart_init(Object *obj)
266 {
267 NRF51UARTState *s = NRF51_UART(obj);
268 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
269
270 memory_region_init_io(&s->iomem, obj, &uart_ops, s,
271 "nrf51_soc.uart", UART_SIZE);
272 sysbus_init_mmio(sbd, &s->iomem);
273 sysbus_init_irq(sbd, &s->irq);
274 }
275
276 static int nrf51_uart_post_load(void *opaque, int version_id)
277 {
278 NRF51UARTState *s = NRF51_UART(opaque);
279
280 if (s->pending_tx_byte) {
281 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
282 uart_transmit, s);
283 }
284
285 return 0;
286 }
287
288 static const VMStateDescription nrf51_uart_vmstate = {
289 .name = "nrf51_soc.uart",
290 .post_load = nrf51_uart_post_load,
291 .fields = (const VMStateField[]) {
292 VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
293 VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
294 VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
295 VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
296 VMSTATE_BOOL(rx_started, NRF51UARTState),
297 VMSTATE_BOOL(tx_started, NRF51UARTState),
298 VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
299 VMSTATE_BOOL(enabled, NRF51UARTState),
300 VMSTATE_END_OF_LIST()
301 }
302 };
303
304 static const Property nrf51_uart_properties[] = {
305 DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
306 };
307
308 static void nrf51_uart_class_init(ObjectClass *klass, const void *data)
309 {
310 DeviceClass *dc = DEVICE_CLASS(klass);
311
312 device_class_set_legacy_reset(dc, nrf51_uart_reset);
313 dc->realize = nrf51_uart_realize;
314 device_class_set_props(dc, nrf51_uart_properties);
315 dc->vmsd = &nrf51_uart_vmstate;
316 }
317
318 static const TypeInfo nrf51_uart_info = {
319 .name = TYPE_NRF51_UART,
320 .parent = TYPE_SYS_BUS_DEVICE,
321 .instance_size = sizeof(NRF51UARTState),
322 .instance_init = nrf51_uart_init,
323 .class_init = nrf51_uart_class_init
324 };
325
326 static void nrf51_uart_register_types(void)
327 {
328 type_register_static(&nrf51_uart_info);
329 }
330
331 type_init(nrf51_uart_register_types)