| 1 | /* |
| 2 | * QEMU 16550A UART emulation |
| 3 | * |
| 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 5 | * Copyright (c) 2008 Citrix Systems, Inc. |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "qemu/bitops.h" |
| 28 | #include "hw/char/serial.h" |
| 29 | #include "hw/core/irq.h" |
| 30 | #include "migration/vmstate.h" |
| 31 | #include "chardev/char-serial.h" |
| 32 | #include "qapi/error.h" |
| 33 | #include "qemu/timer.h" |
| 34 | #include "system/reset.h" |
| 35 | #include "system/runstate.h" |
| 36 | #include "qemu/error-report.h" |
| 37 | #include "trace.h" |
| 38 | #include "hw/core/qdev-properties.h" |
| 39 | #include "hw/core/qdev-properties-system.h" |
| 40 | |
| 41 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
| 42 | #define UART_LCR_SB 0x40 /* Set break */ |
| 43 | #define UART_LCR_EPS 0x10 /* Even parity select */ |
| 44 | #define UART_LCR_PEN 0x08 /* Parity enable */ |
| 45 | #define UART_LCR_NSTB 0x04 /* Number of stop bits */ |
| 46 | #define UART_LCR_WLS 0x03 /* Word length select */ |
| 47 | |
| 48 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| 49 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| 50 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| 51 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
| 52 | |
| 53 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
| 54 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
| 55 | |
| 56 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
| 57 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| 58 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
| 59 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
| 60 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
| 61 | |
| 62 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functioning */ |
| 63 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ |
| 64 | |
| 65 | /* |
| 66 | * These are the definitions for the Modem Control Register |
| 67 | */ |
| 68 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
| 69 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
| 70 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
| 71 | #define UART_MCR_RTS 0x02 /* RTS complement */ |
| 72 | #define UART_MCR_DTR 0x01 /* DTR complement */ |
| 73 | |
| 74 | /* |
| 75 | * These are the definitions for the Modem Status Register |
| 76 | */ |
| 77 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
| 78 | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
| 79 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
| 80 | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
| 81 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
| 82 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
| 83 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
| 84 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
| 85 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
| 86 | |
| 87 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
| 88 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
| 89 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
| 90 | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
| 91 | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
| 92 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
| 93 | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
| 94 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
| 95 | |
| 96 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ |
| 97 | |
| 98 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
| 99 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
| 100 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
| 101 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
| 102 | |
| 103 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
| 104 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
| 105 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
| 106 | #define UART_FCR_FE 0x01 /* FIFO Enable */ |
| 107 | |
| 108 | #define MAX_XMIT_RETRY 4 |
| 109 | |
| 110 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
| 111 | static void serial_xmit(SerialState *s); |
| 112 | |
| 113 | static inline void recv_fifo_put(SerialState *s, uint8_t chr) |
| 114 | { |
| 115 | /* Receive overruns do not overwrite FIFO contents. */ |
| 116 | if (!fifo8_is_full(&s->recv_fifo)) { |
| 117 | fifo8_push(&s->recv_fifo, chr); |
| 118 | } else { |
| 119 | s->lsr |= UART_LSR_OE; |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | static void serial_update_irq(SerialState *s) |
| 124 | { |
| 125 | uint8_t tmp_iir = UART_IIR_NO_INT; |
| 126 | |
| 127 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { |
| 128 | tmp_iir = UART_IIR_RLSI; |
| 129 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
| 130 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, |
| 131 | * this is not in the specification but is observed on existing |
| 132 | * hardware. */ |
| 133 | tmp_iir = UART_IIR_CTI; |
| 134 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
| 135 | (!(s->fcr & UART_FCR_FE) || |
| 136 | fifo8_num_used(&s->recv_fifo) >= s->recv_fifo_itl)) { |
| 137 | tmp_iir = UART_IIR_RDI; |
| 138 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
| 139 | tmp_iir = UART_IIR_THRI; |
| 140 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
| 141 | tmp_iir = UART_IIR_MSI; |
| 142 | } |
| 143 | |
| 144 | s->iir = tmp_iir | (s->iir & 0xF0); |
| 145 | |
| 146 | if (tmp_iir != UART_IIR_NO_INT) { |
| 147 | qemu_irq_raise(s->irq); |
| 148 | } else { |
| 149 | qemu_irq_lower(s->irq); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | static void serial_update_parameters(SerialState *s) |
| 154 | { |
| 155 | float speed; |
| 156 | int parity, data_bits, stop_bits, frame_size; |
| 157 | QEMUSerialSetParams ssp; |
| 158 | |
| 159 | /* Start bit. */ |
| 160 | frame_size = 1; |
| 161 | if (s->lcr & UART_LCR_PEN) { |
| 162 | /* Parity bit. */ |
| 163 | frame_size++; |
| 164 | if (s->lcr & UART_LCR_EPS) |
| 165 | parity = 'E'; |
| 166 | else |
| 167 | parity = 'O'; |
| 168 | } else { |
| 169 | parity = 'N'; |
| 170 | } |
| 171 | if (s->lcr & UART_LCR_NSTB) { |
| 172 | stop_bits = 2; |
| 173 | } else { |
| 174 | stop_bits = 1; |
| 175 | } |
| 176 | |
| 177 | data_bits = (s->lcr & UART_LCR_WLS) + 5; |
| 178 | frame_size += data_bits + stop_bits; |
| 179 | /* Zero divisor should give about 3500 baud */ |
| 180 | speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider; |
| 181 | ssp.speed = speed; |
| 182 | ssp.parity = parity; |
| 183 | ssp.data_bits = data_bits; |
| 184 | ssp.stop_bits = stop_bits; |
| 185 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; |
| 186 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 187 | trace_serial_update_parameters(speed, parity, data_bits, stop_bits); |
| 188 | } |
| 189 | |
| 190 | static void serial_update_msl(SerialState *s) |
| 191 | { |
| 192 | uint8_t omsr; |
| 193 | int flags; |
| 194 | |
| 195 | timer_del(s->modem_status_poll); |
| 196 | |
| 197 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, |
| 198 | &flags) == -ENOTSUP) { |
| 199 | s->poll_msl = -1; |
| 200 | return; |
| 201 | } |
| 202 | |
| 203 | omsr = s->msr; |
| 204 | |
| 205 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
| 206 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
| 207 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
| 208 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
| 209 | |
| 210 | if (s->msr != omsr) { |
| 211 | /* Set delta bits */ |
| 212 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
| 213 | /* UART_MSR_TERI only if change was from 1 -> 0 */ |
| 214 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) |
| 215 | s->msr &= ~UART_MSR_TERI; |
| 216 | serial_update_irq(s); |
| 217 | } |
| 218 | |
| 219 | /* The real 16550A apparently has a 250ns response latency to line status changes. |
| 220 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ |
| 221 | |
| 222 | if (s->poll_msl) { |
| 223 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 224 | NANOSECONDS_PER_SECOND / 100); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | static gboolean serial_watch_cb(void *do_not_use, GIOCondition cond, |
| 229 | void *opaque) |
| 230 | { |
| 231 | SerialState *s = opaque; |
| 232 | s->watch_tag = 0; |
| 233 | serial_xmit(s); |
| 234 | return G_SOURCE_REMOVE; |
| 235 | } |
| 236 | |
| 237 | static void serial_xmit(SerialState *s) |
| 238 | { |
| 239 | do { |
| 240 | assert(!(s->lsr & UART_LSR_TEMT)); |
| 241 | if (s->tsr_retry == 0) { |
| 242 | assert(!(s->lsr & UART_LSR_THRE)); |
| 243 | |
| 244 | if (s->fcr & UART_FCR_FE) { |
| 245 | assert(!fifo8_is_empty(&s->xmit_fifo)); |
| 246 | s->tsr = fifo8_pop(&s->xmit_fifo); |
| 247 | if (fifo8_is_empty(&s->xmit_fifo)) { |
| 248 | s->lsr |= UART_LSR_THRE; |
| 249 | } |
| 250 | } else { |
| 251 | s->tsr = s->thr; |
| 252 | s->lsr |= UART_LSR_THRE; |
| 253 | } |
| 254 | if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { |
| 255 | s->thr_ipending = 1; |
| 256 | serial_update_irq(s); |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | if (s->mcr & UART_MCR_LOOP) { |
| 261 | /* in loopback mode, say that we just received a char */ |
| 262 | serial_receive1(s, &s->tsr, 1); |
| 263 | } else { |
| 264 | int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1); |
| 265 | |
| 266 | if ((rc == 0 || |
| 267 | (rc == -1 && errno == EAGAIN)) && |
| 268 | s->tsr_retry < MAX_XMIT_RETRY) { |
| 269 | assert(s->watch_tag == 0); |
| 270 | s->watch_tag = |
| 271 | qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
| 272 | serial_watch_cb, s); |
| 273 | if (s->watch_tag > 0) { |
| 274 | s->tsr_retry++; |
| 275 | return; |
| 276 | } |
| 277 | } |
| 278 | } |
| 279 | s->tsr_retry = 0; |
| 280 | |
| 281 | /* Transmit another byte if it is already available. It is only |
| 282 | possible when FIFO is enabled and not empty. */ |
| 283 | } while (!(s->lsr & UART_LSR_THRE)); |
| 284 | |
| 285 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 286 | s->lsr |= UART_LSR_TEMT; |
| 287 | } |
| 288 | |
| 289 | static void serial_write_fcr(SerialState *s, uint8_t val) |
| 290 | { |
| 291 | /* Set fcr - val only has the bits that are supposed to "stick" */ |
| 292 | s->fcr = val; |
| 293 | |
| 294 | if (val & UART_FCR_FE) { |
| 295 | s->iir |= UART_IIR_FE; |
| 296 | /* Set recv_fifo trigger Level */ |
| 297 | switch (val & 0xC0) { |
| 298 | case UART_FCR_ITL_1: |
| 299 | s->recv_fifo_itl = 1; |
| 300 | break; |
| 301 | case UART_FCR_ITL_2: |
| 302 | s->recv_fifo_itl = 4; |
| 303 | break; |
| 304 | case UART_FCR_ITL_3: |
| 305 | s->recv_fifo_itl = 8; |
| 306 | break; |
| 307 | case UART_FCR_ITL_4: |
| 308 | s->recv_fifo_itl = 14; |
| 309 | break; |
| 310 | } |
| 311 | } else { |
| 312 | s->iir &= ~UART_IIR_FE; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | static void serial_update_tiocm(SerialState *s) |
| 317 | { |
| 318 | int flags; |
| 319 | |
| 320 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
| 321 | |
| 322 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
| 323 | |
| 324 | if (s->mcr & UART_MCR_RTS) { |
| 325 | flags |= CHR_TIOCM_RTS; |
| 326 | } |
| 327 | if (s->mcr & UART_MCR_DTR) { |
| 328 | flags |= CHR_TIOCM_DTR; |
| 329 | } |
| 330 | |
| 331 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
| 332 | } |
| 333 | |
| 334 | static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
| 335 | unsigned size) |
| 336 | { |
| 337 | SerialState *s = opaque; |
| 338 | |
| 339 | assert(size == 1 && addr < 8); |
| 340 | trace_serial_write(addr, val); |
| 341 | switch(addr) { |
| 342 | default: |
| 343 | case 0: |
| 344 | if (s->lcr & UART_LCR_DLAB) { |
| 345 | s->divider = deposit32(s->divider, 8 * addr, 8, val); |
| 346 | serial_update_parameters(s); |
| 347 | } else { |
| 348 | s->thr = (uint8_t) val; |
| 349 | if(s->fcr & UART_FCR_FE) { |
| 350 | /* xmit overruns overwrite data, so make space if needed */ |
| 351 | if (fifo8_is_full(&s->xmit_fifo)) { |
| 352 | fifo8_pop(&s->xmit_fifo); |
| 353 | } |
| 354 | fifo8_push(&s->xmit_fifo, s->thr); |
| 355 | } |
| 356 | s->thr_ipending = 0; |
| 357 | s->lsr &= ~UART_LSR_THRE; |
| 358 | s->lsr &= ~UART_LSR_TEMT; |
| 359 | serial_update_irq(s); |
| 360 | if (s->tsr_retry == 0) { |
| 361 | serial_xmit(s); |
| 362 | } |
| 363 | } |
| 364 | break; |
| 365 | case 1: |
| 366 | if (s->lcr & UART_LCR_DLAB) { |
| 367 | s->divider = deposit32(s->divider, 8 * addr, 8, val); |
| 368 | serial_update_parameters(s); |
| 369 | } else { |
| 370 | uint8_t changed = (s->ier ^ val) & 0x0f; |
| 371 | s->ier = val & 0x0f; |
| 372 | /* If the backend device is a real serial port, turn polling of the modem |
| 373 | * status lines on physical port on or off depending on UART_IER_MSI state. |
| 374 | */ |
| 375 | if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { |
| 376 | if (s->ier & UART_IER_MSI) { |
| 377 | s->poll_msl = 1; |
| 378 | serial_update_msl(s); |
| 379 | } else { |
| 380 | timer_del(s->modem_status_poll); |
| 381 | s->poll_msl = 0; |
| 382 | } |
| 383 | } |
| 384 | |
| 385 | /* Turning on the THRE interrupt on IER can trigger the interrupt |
| 386 | * if LSR.THRE=1, even if it had been masked before by reading IIR. |
| 387 | * This is not in the datasheet, but Windows relies on it. It is |
| 388 | * unclear if THRE has to be resampled every time THRI becomes |
| 389 | * 1, or only on the rising edge. Bochs does the latter, and Windows |
| 390 | * always toggles IER to all zeroes and back to all ones, so do the |
| 391 | * same. |
| 392 | * |
| 393 | * If IER.THRI is zero, thr_ipending is not used. Set it to zero |
| 394 | * so that the thr_ipending subsection is not migrated. |
| 395 | */ |
| 396 | if (changed & UART_IER_THRI) { |
| 397 | if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { |
| 398 | s->thr_ipending = 1; |
| 399 | } else { |
| 400 | s->thr_ipending = 0; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | if (changed) { |
| 405 | serial_update_irq(s); |
| 406 | } |
| 407 | } |
| 408 | break; |
| 409 | case 2: |
| 410 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ |
| 411 | if ((val ^ s->fcr) & UART_FCR_FE) { |
| 412 | val |= UART_FCR_XFR | UART_FCR_RFR; |
| 413 | } |
| 414 | |
| 415 | /* FIFO clear */ |
| 416 | |
| 417 | if (val & UART_FCR_RFR) { |
| 418 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
| 419 | timer_del(s->fifo_timeout_timer); |
| 420 | s->timeout_ipending = 0; |
| 421 | fifo8_reset(&s->recv_fifo); |
| 422 | } |
| 423 | |
| 424 | if (val & UART_FCR_XFR) { |
| 425 | s->lsr |= UART_LSR_THRE; |
| 426 | s->thr_ipending = 1; |
| 427 | fifo8_reset(&s->xmit_fifo); |
| 428 | } |
| 429 | |
| 430 | serial_write_fcr(s, val & 0xC9); |
| 431 | serial_update_irq(s); |
| 432 | break; |
| 433 | case 3: |
| 434 | { |
| 435 | int break_enable; |
| 436 | s->lcr = val; |
| 437 | serial_update_parameters(s); |
| 438 | break_enable = !!(val & UART_LCR_SB); |
| 439 | if (break_enable != s->last_break_enable) { |
| 440 | s->last_break_enable = break_enable; |
| 441 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
| 442 | &break_enable); |
| 443 | } |
| 444 | } |
| 445 | break; |
| 446 | case 4: |
| 447 | { |
| 448 | int old_mcr = s->mcr; |
| 449 | s->mcr = val & 0x1f; |
| 450 | if (val & UART_MCR_LOOP) |
| 451 | break; |
| 452 | |
| 453 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
| 454 | serial_update_tiocm(s); |
| 455 | /* Update the modem status after a one-character-send wait-time, since there may be a response |
| 456 | from the device/computer at the other end of the serial line */ |
| 457 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); |
| 458 | } |
| 459 | } |
| 460 | break; |
| 461 | case 5: |
| 462 | break; |
| 463 | case 6: |
| 464 | break; |
| 465 | case 7: |
| 466 | s->scr = val; |
| 467 | break; |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) |
| 472 | { |
| 473 | SerialState *s = opaque; |
| 474 | uint32_t ret; |
| 475 | |
| 476 | assert(size == 1 && addr < 8); |
| 477 | switch(addr) { |
| 478 | default: |
| 479 | case 0: |
| 480 | if (s->lcr & UART_LCR_DLAB) { |
| 481 | ret = extract16(s->divider, 8 * addr, 8); |
| 482 | } else { |
| 483 | if(s->fcr & UART_FCR_FE) { |
| 484 | ret = fifo8_is_empty(&s->recv_fifo) ? |
| 485 | 0 : fifo8_pop(&s->recv_fifo); |
| 486 | if (fifo8_is_empty(&s->recv_fifo)) { |
| 487 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
| 488 | } else { |
| 489 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
| 490 | } |
| 491 | s->timeout_ipending = 0; |
| 492 | } else { |
| 493 | ret = s->rbr; |
| 494 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
| 495 | } |
| 496 | serial_update_irq(s); |
| 497 | if (!(s->mcr & UART_MCR_LOOP)) { |
| 498 | /* in loopback mode, don't receive any data */ |
| 499 | qemu_chr_fe_accept_input(&s->chr); |
| 500 | } |
| 501 | } |
| 502 | break; |
| 503 | case 1: |
| 504 | if (s->lcr & UART_LCR_DLAB) { |
| 505 | ret = extract16(s->divider, 8 * addr, 8); |
| 506 | } else { |
| 507 | ret = s->ier; |
| 508 | } |
| 509 | break; |
| 510 | case 2: |
| 511 | ret = s->iir; |
| 512 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { |
| 513 | s->thr_ipending = 0; |
| 514 | serial_update_irq(s); |
| 515 | } |
| 516 | break; |
| 517 | case 3: |
| 518 | ret = s->lcr; |
| 519 | break; |
| 520 | case 4: |
| 521 | ret = s->mcr; |
| 522 | break; |
| 523 | case 5: |
| 524 | ret = s->lsr; |
| 525 | /* Clear break and overrun interrupts */ |
| 526 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { |
| 527 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); |
| 528 | serial_update_irq(s); |
| 529 | } |
| 530 | break; |
| 531 | case 6: |
| 532 | if (s->mcr & UART_MCR_LOOP) { |
| 533 | /* in loopback, the modem output pins are connected to the |
| 534 | inputs */ |
| 535 | ret = (s->mcr & 0x0c) << 4; |
| 536 | ret |= (s->mcr & 0x02) << 3; |
| 537 | ret |= (s->mcr & 0x01) << 5; |
| 538 | } else { |
| 539 | if (s->poll_msl >= 0) |
| 540 | serial_update_msl(s); |
| 541 | ret = s->msr; |
| 542 | /* Clear delta bits & msr int after read, if they were set */ |
| 543 | if (s->msr & UART_MSR_ANY_DELTA) { |
| 544 | s->msr &= 0xF0; |
| 545 | serial_update_irq(s); |
| 546 | } |
| 547 | } |
| 548 | break; |
| 549 | case 7: |
| 550 | ret = s->scr; |
| 551 | break; |
| 552 | } |
| 553 | trace_serial_read(addr, ret); |
| 554 | return ret; |
| 555 | } |
| 556 | |
| 557 | static int serial_can_receive(SerialState *s) |
| 558 | { |
| 559 | if(s->fcr & UART_FCR_FE) { |
| 560 | if (!fifo8_is_full(&s->recv_fifo)) { |
| 561 | /* |
| 562 | * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 |
| 563 | * if above. If UART_FIFO_LENGTH - fifo.count is advertised the |
| 564 | * effect will be to almost always fill the fifo completely before |
| 565 | * the guest has a chance to respond, effectively overriding the ITL |
| 566 | * that the guest has set. |
| 567 | */ |
| 568 | return (fifo8_num_used(&s->recv_fifo) <= s->recv_fifo_itl) ? |
| 569 | s->recv_fifo_itl - fifo8_num_used(&s->recv_fifo) : 1; |
| 570 | } else { |
| 571 | return 0; |
| 572 | } |
| 573 | } else { |
| 574 | return !(s->lsr & UART_LSR_DR); |
| 575 | } |
| 576 | } |
| 577 | |
| 578 | static void serial_receive_break(SerialState *s) |
| 579 | { |
| 580 | s->rbr = 0; |
| 581 | /* When the LSR_DR is set a null byte is pushed into the fifo */ |
| 582 | recv_fifo_put(s, '\0'); |
| 583 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
| 584 | serial_update_irq(s); |
| 585 | } |
| 586 | |
| 587 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ |
| 588 | static void fifo_timeout_int (void *opaque) { |
| 589 | SerialState *s = opaque; |
| 590 | if (!fifo8_is_empty(&s->recv_fifo)) { |
| 591 | s->timeout_ipending = 1; |
| 592 | serial_update_irq(s); |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | static int serial_can_receive1(void *opaque) |
| 597 | { |
| 598 | SerialState *s = opaque; |
| 599 | return serial_can_receive(s); |
| 600 | } |
| 601 | |
| 602 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
| 603 | { |
| 604 | SerialState *s = opaque; |
| 605 | |
| 606 | if (s->wakeup) { |
| 607 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL); |
| 608 | } |
| 609 | if(s->fcr & UART_FCR_FE) { |
| 610 | int i; |
| 611 | for (i = 0; i < size; i++) { |
| 612 | recv_fifo_put(s, buf[i]); |
| 613 | } |
| 614 | s->lsr |= UART_LSR_DR; |
| 615 | /* call the timeout receive callback in 4 char transmit time */ |
| 616 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
| 617 | } else { |
| 618 | if (s->lsr & UART_LSR_DR) |
| 619 | s->lsr |= UART_LSR_OE; |
| 620 | s->rbr = buf[0]; |
| 621 | s->lsr |= UART_LSR_DR; |
| 622 | } |
| 623 | serial_update_irq(s); |
| 624 | } |
| 625 | |
| 626 | static void serial_event(void *opaque, QEMUChrEvent event) |
| 627 | { |
| 628 | SerialState *s = opaque; |
| 629 | if (event == CHR_EVENT_BREAK) |
| 630 | serial_receive_break(s); |
| 631 | } |
| 632 | |
| 633 | static int serial_pre_save(void *opaque) |
| 634 | { |
| 635 | SerialState *s = opaque; |
| 636 | s->fcr_vmstate = s->fcr; |
| 637 | |
| 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | static int serial_pre_load(void *opaque) |
| 642 | { |
| 643 | SerialState *s = opaque; |
| 644 | s->thr_ipending = -1; |
| 645 | s->poll_msl = -1; |
| 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | static int serial_post_load(void *opaque, int version_id) |
| 650 | { |
| 651 | SerialState *s = opaque; |
| 652 | |
| 653 | if (version_id < 3) { |
| 654 | s->fcr_vmstate = 0; |
| 655 | } |
| 656 | if (s->thr_ipending == -1) { |
| 657 | s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); |
| 658 | } |
| 659 | |
| 660 | if (s->tsr_retry > 0) { |
| 661 | /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */ |
| 662 | if (s->lsr & UART_LSR_TEMT) { |
| 663 | error_report("inconsistent state in serial device " |
| 664 | "(tsr empty, tsr_retry=%d", s->tsr_retry); |
| 665 | return -1; |
| 666 | } |
| 667 | |
| 668 | if (s->tsr_retry > MAX_XMIT_RETRY) { |
| 669 | s->tsr_retry = MAX_XMIT_RETRY; |
| 670 | } |
| 671 | |
| 672 | assert(s->watch_tag == 0); |
| 673 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
| 674 | serial_watch_cb, s); |
| 675 | } else { |
| 676 | /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */ |
| 677 | if (!(s->lsr & UART_LSR_TEMT)) { |
| 678 | error_report("inconsistent state in serial device " |
| 679 | "(tsr not empty, tsr_retry=0"); |
| 680 | return -1; |
| 681 | } |
| 682 | } |
| 683 | |
| 684 | s->last_break_enable = !!(s->lcr & UART_LCR_SB); |
| 685 | /* Initialize fcr via setter to perform essential side-effects */ |
| 686 | serial_write_fcr(s, s->fcr_vmstate); |
| 687 | serial_update_parameters(s); |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | static bool serial_thr_ipending_needed(void *opaque) |
| 692 | { |
| 693 | SerialState *s = opaque; |
| 694 | |
| 695 | if (s->ier & UART_IER_THRI) { |
| 696 | bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); |
| 697 | return s->thr_ipending != expected_value; |
| 698 | } else { |
| 699 | /* LSR.THRE will be sampled again when the interrupt is |
| 700 | * enabled. thr_ipending is not used in this case, do |
| 701 | * not migrate it. |
| 702 | */ |
| 703 | return false; |
| 704 | } |
| 705 | } |
| 706 | |
| 707 | static const VMStateDescription vmstate_serial_thr_ipending = { |
| 708 | .name = "serial/thr_ipending", |
| 709 | .version_id = 1, |
| 710 | .minimum_version_id = 1, |
| 711 | .needed = serial_thr_ipending_needed, |
| 712 | .fields = (const VMStateField[]) { |
| 713 | VMSTATE_INT32(thr_ipending, SerialState), |
| 714 | VMSTATE_END_OF_LIST() |
| 715 | } |
| 716 | }; |
| 717 | |
| 718 | static bool serial_tsr_needed(void *opaque) |
| 719 | { |
| 720 | SerialState *s = opaque; |
| 721 | return s->tsr_retry != 0; |
| 722 | } |
| 723 | |
| 724 | static const VMStateDescription vmstate_serial_tsr = { |
| 725 | .name = "serial/tsr", |
| 726 | .version_id = 1, |
| 727 | .minimum_version_id = 1, |
| 728 | .needed = serial_tsr_needed, |
| 729 | .fields = (const VMStateField[]) { |
| 730 | VMSTATE_UINT32(tsr_retry, SerialState), |
| 731 | VMSTATE_UINT8(thr, SerialState), |
| 732 | VMSTATE_UINT8(tsr, SerialState), |
| 733 | VMSTATE_END_OF_LIST() |
| 734 | } |
| 735 | }; |
| 736 | |
| 737 | static bool serial_recv_fifo_needed(void *opaque) |
| 738 | { |
| 739 | SerialState *s = opaque; |
| 740 | return !fifo8_is_empty(&s->recv_fifo); |
| 741 | |
| 742 | } |
| 743 | |
| 744 | static const VMStateDescription vmstate_serial_recv_fifo = { |
| 745 | .name = "serial/recv_fifo", |
| 746 | .version_id = 1, |
| 747 | .minimum_version_id = 1, |
| 748 | .needed = serial_recv_fifo_needed, |
| 749 | .fields = (const VMStateField[]) { |
| 750 | VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), |
| 751 | VMSTATE_END_OF_LIST() |
| 752 | } |
| 753 | }; |
| 754 | |
| 755 | static bool serial_xmit_fifo_needed(void *opaque) |
| 756 | { |
| 757 | SerialState *s = opaque; |
| 758 | return !fifo8_is_empty(&s->xmit_fifo); |
| 759 | } |
| 760 | |
| 761 | static const VMStateDescription vmstate_serial_xmit_fifo = { |
| 762 | .name = "serial/xmit_fifo", |
| 763 | .version_id = 1, |
| 764 | .minimum_version_id = 1, |
| 765 | .needed = serial_xmit_fifo_needed, |
| 766 | .fields = (const VMStateField[]) { |
| 767 | VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), |
| 768 | VMSTATE_END_OF_LIST() |
| 769 | } |
| 770 | }; |
| 771 | |
| 772 | static bool serial_fifo_timeout_timer_needed(void *opaque) |
| 773 | { |
| 774 | SerialState *s = opaque; |
| 775 | return timer_pending(s->fifo_timeout_timer); |
| 776 | } |
| 777 | |
| 778 | static const VMStateDescription vmstate_serial_fifo_timeout_timer = { |
| 779 | .name = "serial/fifo_timeout_timer", |
| 780 | .version_id = 1, |
| 781 | .minimum_version_id = 1, |
| 782 | .needed = serial_fifo_timeout_timer_needed, |
| 783 | .fields = (const VMStateField[]) { |
| 784 | VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState), |
| 785 | VMSTATE_END_OF_LIST() |
| 786 | } |
| 787 | }; |
| 788 | |
| 789 | static bool serial_timeout_ipending_needed(void *opaque) |
| 790 | { |
| 791 | SerialState *s = opaque; |
| 792 | return s->timeout_ipending != 0; |
| 793 | } |
| 794 | |
| 795 | static const VMStateDescription vmstate_serial_timeout_ipending = { |
| 796 | .name = "serial/timeout_ipending", |
| 797 | .version_id = 1, |
| 798 | .minimum_version_id = 1, |
| 799 | .needed = serial_timeout_ipending_needed, |
| 800 | .fields = (const VMStateField[]) { |
| 801 | VMSTATE_INT32(timeout_ipending, SerialState), |
| 802 | VMSTATE_END_OF_LIST() |
| 803 | } |
| 804 | }; |
| 805 | |
| 806 | static bool serial_poll_needed(void *opaque) |
| 807 | { |
| 808 | SerialState *s = opaque; |
| 809 | return s->poll_msl >= 0; |
| 810 | } |
| 811 | |
| 812 | static const VMStateDescription vmstate_serial_poll = { |
| 813 | .name = "serial/poll", |
| 814 | .version_id = 1, |
| 815 | .needed = serial_poll_needed, |
| 816 | .minimum_version_id = 1, |
| 817 | .fields = (const VMStateField[]) { |
| 818 | VMSTATE_INT32(poll_msl, SerialState), |
| 819 | VMSTATE_TIMER_PTR(modem_status_poll, SerialState), |
| 820 | VMSTATE_END_OF_LIST() |
| 821 | } |
| 822 | }; |
| 823 | |
| 824 | const VMStateDescription vmstate_serial = { |
| 825 | .name = "serial", |
| 826 | .version_id = 3, |
| 827 | .minimum_version_id = 2, |
| 828 | .pre_save = serial_pre_save, |
| 829 | .pre_load = serial_pre_load, |
| 830 | .post_load = serial_post_load, |
| 831 | .fields = (const VMStateField[]) { |
| 832 | VMSTATE_UINT16_V(divider, SerialState, 2), |
| 833 | VMSTATE_UINT8(rbr, SerialState), |
| 834 | VMSTATE_UINT8(ier, SerialState), |
| 835 | VMSTATE_UINT8(iir, SerialState), |
| 836 | VMSTATE_UINT8(lcr, SerialState), |
| 837 | VMSTATE_UINT8(mcr, SerialState), |
| 838 | VMSTATE_UINT8(lsr, SerialState), |
| 839 | VMSTATE_UINT8(msr, SerialState), |
| 840 | VMSTATE_UINT8(scr, SerialState), |
| 841 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), |
| 842 | VMSTATE_END_OF_LIST() |
| 843 | }, |
| 844 | .subsections = (const VMStateDescription * const []) { |
| 845 | &vmstate_serial_thr_ipending, |
| 846 | &vmstate_serial_tsr, |
| 847 | &vmstate_serial_recv_fifo, |
| 848 | &vmstate_serial_xmit_fifo, |
| 849 | &vmstate_serial_fifo_timeout_timer, |
| 850 | &vmstate_serial_timeout_ipending, |
| 851 | &vmstate_serial_poll, |
| 852 | NULL |
| 853 | } |
| 854 | }; |
| 855 | |
| 856 | static void serial_reset(void *opaque) |
| 857 | { |
| 858 | SerialState *s = opaque; |
| 859 | g_clear_handle_id(&s->watch_tag, g_source_remove); |
| 860 | |
| 861 | s->rbr = 0; |
| 862 | s->ier = 0; |
| 863 | s->iir = UART_IIR_NO_INT; |
| 864 | s->lcr = 0; |
| 865 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
| 866 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
| 867 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ |
| 868 | s->divider = 0x0C; |
| 869 | s->mcr = UART_MCR_OUT2; |
| 870 | s->scr = 0; |
| 871 | s->tsr_retry = 0; |
| 872 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10; |
| 873 | s->poll_msl = 0; |
| 874 | |
| 875 | s->timeout_ipending = 0; |
| 876 | timer_del(s->fifo_timeout_timer); |
| 877 | timer_del(s->modem_status_poll); |
| 878 | |
| 879 | fifo8_reset(&s->recv_fifo); |
| 880 | fifo8_reset(&s->xmit_fifo); |
| 881 | |
| 882 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 883 | |
| 884 | s->thr_ipending = 0; |
| 885 | s->last_break_enable = 0; |
| 886 | qemu_irq_lower(s->irq); |
| 887 | |
| 888 | serial_update_msl(s); |
| 889 | s->msr &= ~UART_MSR_ANY_DELTA; |
| 890 | } |
| 891 | |
| 892 | static int serial_be_change(void *opaque) |
| 893 | { |
| 894 | SerialState *s = opaque; |
| 895 | |
| 896 | qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, |
| 897 | serial_event, serial_be_change, s, NULL, true); |
| 898 | |
| 899 | serial_update_parameters(s); |
| 900 | |
| 901 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
| 902 | &s->last_break_enable); |
| 903 | |
| 904 | s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0; |
| 905 | serial_update_msl(s); |
| 906 | |
| 907 | if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) { |
| 908 | serial_update_tiocm(s); |
| 909 | } |
| 910 | |
| 911 | if (s->watch_tag > 0) { |
| 912 | g_source_remove(s->watch_tag); |
| 913 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
| 914 | serial_watch_cb, s); |
| 915 | } |
| 916 | |
| 917 | return 0; |
| 918 | } |
| 919 | |
| 920 | static void serial_realize(DeviceState *dev, Error **errp) |
| 921 | { |
| 922 | SerialState *s = SERIAL(dev); |
| 923 | |
| 924 | s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); |
| 925 | |
| 926 | s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); |
| 927 | qemu_register_reset(serial_reset, s); |
| 928 | |
| 929 | qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, |
| 930 | serial_event, serial_be_change, s, NULL, true); |
| 931 | fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); |
| 932 | fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); |
| 933 | } |
| 934 | |
| 935 | static void serial_unrealize(DeviceState *dev) |
| 936 | { |
| 937 | SerialState *s = SERIAL(dev); |
| 938 | |
| 939 | g_clear_handle_id(&s->watch_tag, g_source_remove); |
| 940 | qemu_chr_fe_deinit(&s->chr, false); |
| 941 | |
| 942 | timer_free(s->modem_status_poll); |
| 943 | |
| 944 | timer_free(s->fifo_timeout_timer); |
| 945 | |
| 946 | fifo8_destroy(&s->recv_fifo); |
| 947 | fifo8_destroy(&s->xmit_fifo); |
| 948 | |
| 949 | qemu_unregister_reset(serial_reset, s); |
| 950 | } |
| 951 | |
| 952 | const MemoryRegionOps serial_io_ops = { |
| 953 | .read = serial_ioport_read, |
| 954 | .write = serial_ioport_write, |
| 955 | .valid = { |
| 956 | .unaligned = 1, |
| 957 | }, |
| 958 | .impl = { |
| 959 | .min_access_size = 1, |
| 960 | .max_access_size = 1, |
| 961 | }, |
| 962 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 963 | }; |
| 964 | |
| 965 | static const Property serial_properties[] = { |
| 966 | DEFINE_PROP_CHR("chardev", SerialState, chr), |
| 967 | DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200), |
| 968 | DEFINE_PROP_BOOL("wakeup", SerialState, wakeup, false), |
| 969 | }; |
| 970 | |
| 971 | static void serial_class_init(ObjectClass *klass, const void *data) |
| 972 | { |
| 973 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 974 | |
| 975 | /* internal device for serialio/serialmm, not user-creatable */ |
| 976 | dc->user_creatable = false; |
| 977 | dc->realize = serial_realize; |
| 978 | dc->unrealize = serial_unrealize; |
| 979 | device_class_set_props(dc, serial_properties); |
| 980 | } |
| 981 | |
| 982 | static const TypeInfo serial_info = { |
| 983 | .name = TYPE_SERIAL, |
| 984 | .parent = TYPE_DEVICE, |
| 985 | .instance_size = sizeof(SerialState), |
| 986 | .class_init = serial_class_init, |
| 987 | }; |
| 988 | |
| 989 | static void serial_register_types(void) |
| 990 | { |
| 991 | type_register_static(&serial_info); |
| 992 | } |
| 993 | |
| 994 | type_init(serial_register_types) |