| 1 | /* |
| 2 | * QEMU model of the UART on the SiFive E300 and U500 series SOCs. |
| 3 | * |
| 4 | * Copyright (c) 2016 Stefan O'Rear |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qapi/error.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "migration/vmstate.h" |
| 23 | #include "chardev/char.h" |
| 24 | #include "chardev/char-fe.h" |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "hw/char/sifive_uart.h" |
| 27 | #include "hw/core/qdev-properties-system.h" |
| 28 | |
| 29 | #define TX_INTERRUPT_TRIGGER_DELAY_NS 100 |
| 30 | |
| 31 | /* Returns the state of the IP (interrupt pending) register */ |
| 32 | static uint32_t sifive_uart_ip(SiFiveUARTState *s) |
| 33 | { |
| 34 | uint32_t ret = 0; |
| 35 | |
| 36 | uint32_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); |
| 37 | uint32_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); |
| 38 | |
| 39 | if (fifo8_num_used(&s->tx_fifo) < txcnt) { |
| 40 | ret |= SIFIVE_UART_IP_TXWM; |
| 41 | } |
| 42 | |
| 43 | if (s->rx_fifo_len > rxcnt) { |
| 44 | ret |= SIFIVE_UART_IP_RXWM; |
| 45 | } |
| 46 | |
| 47 | return ret; |
| 48 | } |
| 49 | |
| 50 | static void sifive_uart_update_irq(SiFiveUARTState *s) |
| 51 | { |
| 52 | int cond = 0; |
| 53 | uint32_t ip = sifive_uart_ip(s); |
| 54 | |
| 55 | if (((ip & SIFIVE_UART_IP_TXWM) && (s->ie & SIFIVE_UART_IE_TXWM)) || |
| 56 | ((ip & SIFIVE_UART_IP_RXWM) && (s->ie & SIFIVE_UART_IE_RXWM))) { |
| 57 | cond = 1; |
| 58 | } |
| 59 | |
| 60 | qemu_set_irq(s->irq, cond); |
| 61 | } |
| 62 | |
| 63 | static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond, |
| 64 | void *opaque) |
| 65 | { |
| 66 | SiFiveUARTState *s = opaque; |
| 67 | int ret; |
| 68 | const uint8_t *characters; |
| 69 | uint32_t numptr = 0; |
| 70 | |
| 71 | /* instant drain the fifo when there's no back-end */ |
| 72 | if (!qemu_chr_fe_backend_connected(&s->chr)) { |
| 73 | fifo8_reset(&s->tx_fifo); |
| 74 | return G_SOURCE_REMOVE; |
| 75 | } |
| 76 | |
| 77 | if (fifo8_is_empty(&s->tx_fifo)) { |
| 78 | return G_SOURCE_REMOVE; |
| 79 | } |
| 80 | |
| 81 | /* Don't pop the FIFO if transmit is disabled. */ |
| 82 | if (!SIFIVE_UART_TXEN(s->txctrl)) { |
| 83 | return G_SOURCE_REMOVE; |
| 84 | } |
| 85 | |
| 86 | /* Don't pop the FIFO in case the write fails */ |
| 87 | characters = fifo8_peek_bufptr(&s->tx_fifo, |
| 88 | fifo8_num_used(&s->tx_fifo), &numptr); |
| 89 | ret = qemu_chr_fe_write(&s->chr, characters, numptr); |
| 90 | |
| 91 | if (ret >= 0) { |
| 92 | /* We wrote the data, actually pop the fifo */ |
| 93 | fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); |
| 94 | } |
| 95 | |
| 96 | if (!fifo8_is_empty(&s->tx_fifo)) { |
| 97 | guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
| 98 | sifive_uart_xmit, s); |
| 99 | if (!r) { |
| 100 | fifo8_reset(&s->tx_fifo); |
| 101 | return G_SOURCE_REMOVE; |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | /* Clear the TX Full bit */ |
| 106 | if (!fifo8_is_full(&s->tx_fifo)) { |
| 107 | s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL; |
| 108 | } |
| 109 | |
| 110 | sifive_uart_update_irq(s); |
| 111 | return G_SOURCE_REMOVE; |
| 112 | } |
| 113 | |
| 114 | static void sifive_uart_trigger_tx_fifo(SiFiveUARTState *s) |
| 115 | { |
| 116 | uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 117 | |
| 118 | if (!timer_pending(s->fifo_trigger_handle)) { |
| 119 | timer_mod(s->fifo_trigger_handle, current_time + |
| 120 | TX_INTERRUPT_TRIGGER_DELAY_NS); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf, |
| 125 | int size) |
| 126 | { |
| 127 | uint32_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); |
| 128 | bool update_irq = false; |
| 129 | |
| 130 | if (size > fifo8_num_free(&s->tx_fifo)) { |
| 131 | size = fifo8_num_free(&s->tx_fifo); |
| 132 | qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow.\n"); |
| 133 | } |
| 134 | |
| 135 | if (size > 0) { |
| 136 | if (fifo8_num_used(&s->tx_fifo) < txcnt && |
| 137 | (fifo8_num_used(&s->tx_fifo) + size) >= txcnt) { |
| 138 | update_irq = true; |
| 139 | } |
| 140 | |
| 141 | fifo8_push_all(&s->tx_fifo, buf, size); |
| 142 | } |
| 143 | |
| 144 | if (fifo8_is_full(&s->tx_fifo)) { |
| 145 | s->txfifo |= SIFIVE_UART_TXFIFO_FULL; |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * Update txwm interrupt pending status when the number of entries |
| 150 | * in the transmit FIFO crosses or reaches the watermark. |
| 151 | */ |
| 152 | if (update_irq) { |
| 153 | sifive_uart_update_irq(s); |
| 154 | } |
| 155 | |
| 156 | sifive_uart_trigger_tx_fifo(s); |
| 157 | } |
| 158 | |
| 159 | static uint64_t |
| 160 | sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) |
| 161 | { |
| 162 | SiFiveUARTState *s = opaque; |
| 163 | unsigned char r; |
| 164 | switch (addr) { |
| 165 | case SIFIVE_UART_RXFIFO: |
| 166 | if (s->rx_fifo_len) { |
| 167 | r = s->rx_fifo[0]; |
| 168 | memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); |
| 169 | s->rx_fifo_len--; |
| 170 | qemu_chr_fe_accept_input(&s->chr); |
| 171 | sifive_uart_update_irq(s); |
| 172 | return r; |
| 173 | } |
| 174 | return 0x80000000; |
| 175 | |
| 176 | case SIFIVE_UART_TXFIFO: |
| 177 | return s->txfifo; |
| 178 | case SIFIVE_UART_IE: |
| 179 | return s->ie; |
| 180 | case SIFIVE_UART_IP: |
| 181 | return sifive_uart_ip(s); |
| 182 | case SIFIVE_UART_TXCTRL: |
| 183 | return s->txctrl; |
| 184 | case SIFIVE_UART_RXCTRL: |
| 185 | return s->rxctrl; |
| 186 | case SIFIVE_UART_DIV: |
| 187 | return s->div; |
| 188 | } |
| 189 | |
| 190 | qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", |
| 191 | __func__, (int)addr); |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static void |
| 196 | sifive_uart_write(void *opaque, hwaddr addr, |
| 197 | uint64_t val64, unsigned int size) |
| 198 | { |
| 199 | SiFiveUARTState *s = opaque; |
| 200 | uint32_t value = val64; |
| 201 | uint8_t ch = value; |
| 202 | |
| 203 | switch (addr) { |
| 204 | case SIFIVE_UART_TXFIFO: |
| 205 | sifive_uart_write_tx_fifo(s, &ch, 1); |
| 206 | return; |
| 207 | case SIFIVE_UART_IE: |
| 208 | s->ie = val64; |
| 209 | sifive_uart_update_irq(s); |
| 210 | return; |
| 211 | case SIFIVE_UART_TXCTRL: |
| 212 | s->txctrl = val64; |
| 213 | if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) { |
| 214 | sifive_uart_trigger_tx_fifo(s); |
| 215 | } |
| 216 | sifive_uart_update_irq(s); |
| 217 | return; |
| 218 | case SIFIVE_UART_RXCTRL: |
| 219 | s->rxctrl = val64; |
| 220 | sifive_uart_update_irq(s); |
| 221 | return; |
| 222 | case SIFIVE_UART_DIV: |
| 223 | s->div = val64; |
| 224 | return; |
| 225 | } |
| 226 | qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", |
| 227 | __func__, (int)addr, (int)value); |
| 228 | } |
| 229 | |
| 230 | static void fifo_trigger_update(void *opaque) |
| 231 | { |
| 232 | SiFiveUARTState *s = opaque; |
| 233 | |
| 234 | sifive_uart_xmit(NULL, G_IO_OUT, s); |
| 235 | } |
| 236 | |
| 237 | static const MemoryRegionOps sifive_uart_ops = { |
| 238 | .read = sifive_uart_read, |
| 239 | .write = sifive_uart_write, |
| 240 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 241 | .valid = { |
| 242 | .min_access_size = 4, |
| 243 | .max_access_size = 4 |
| 244 | } |
| 245 | }; |
| 246 | |
| 247 | static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size) |
| 248 | { |
| 249 | SiFiveUARTState *s = opaque; |
| 250 | |
| 251 | /* Got a byte. */ |
| 252 | if (s->rx_fifo_len >= sizeof(s->rx_fifo)) { |
| 253 | printf("WARNING: UART dropped char.\n"); |
| 254 | return; |
| 255 | } |
| 256 | s->rx_fifo[s->rx_fifo_len++] = *buf; |
| 257 | |
| 258 | sifive_uart_update_irq(s); |
| 259 | } |
| 260 | |
| 261 | static int sifive_uart_can_rx(void *opaque) |
| 262 | { |
| 263 | SiFiveUARTState *s = opaque; |
| 264 | |
| 265 | return SIFIVE_UART_RXEN(s->rxctrl) && (s->rx_fifo_len < sizeof(s->rx_fifo)); |
| 266 | } |
| 267 | |
| 268 | static void sifive_uart_event(void *opaque, QEMUChrEvent event) |
| 269 | { |
| 270 | } |
| 271 | |
| 272 | static int sifive_uart_be_change(void *opaque) |
| 273 | { |
| 274 | SiFiveUARTState *s = opaque; |
| 275 | |
| 276 | qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, |
| 277 | sifive_uart_event, sifive_uart_be_change, s, |
| 278 | NULL, true); |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static void sifive_uart_reset_enter(Object *obj, ResetType type) |
| 284 | { |
| 285 | SiFiveUARTState *s = SIFIVE_UART(obj); |
| 286 | |
| 287 | s->txfifo = 0; |
| 288 | s->ie = 0; |
| 289 | s->txctrl = 0; |
| 290 | s->rxctrl = 0; |
| 291 | s->div = 0; |
| 292 | |
| 293 | s->rx_fifo_len = 0; |
| 294 | |
| 295 | memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); |
| 296 | fifo8_reset(&s->tx_fifo); |
| 297 | } |
| 298 | |
| 299 | static const Property sifive_uart_properties[] = { |
| 300 | DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr), |
| 301 | }; |
| 302 | |
| 303 | static void sifive_uart_init(Object *obj) |
| 304 | { |
| 305 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 306 | SiFiveUARTState *s = SIFIVE_UART(obj); |
| 307 | |
| 308 | memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s, |
| 309 | TYPE_SIFIVE_UART, SIFIVE_UART_MAX); |
| 310 | sysbus_init_mmio(sbd, &s->mmio); |
| 311 | sysbus_init_irq(sbd, &s->irq); |
| 312 | } |
| 313 | |
| 314 | static void sifive_uart_realize(DeviceState *dev, Error **errp) |
| 315 | { |
| 316 | SiFiveUARTState *s = SIFIVE_UART(dev); |
| 317 | |
| 318 | fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE); |
| 319 | |
| 320 | s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 321 | fifo_trigger_update, s); |
| 322 | |
| 323 | if (qemu_chr_fe_backend_connected(&s->chr)) { |
| 324 | qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, |
| 325 | sifive_uart_event, sifive_uart_be_change, s, |
| 326 | NULL, true); |
| 327 | } |
| 328 | |
| 329 | } |
| 330 | |
| 331 | static void sifive_uart_unrealize(DeviceState *dev) |
| 332 | { |
| 333 | SiFiveUARTState *s = SIFIVE_UART(dev); |
| 334 | |
| 335 | fifo8_destroy(&s->tx_fifo); |
| 336 | } |
| 337 | |
| 338 | static void sifive_uart_reset_hold(Object *obj, ResetType type) |
| 339 | { |
| 340 | SiFiveUARTState *s = SIFIVE_UART(obj); |
| 341 | qemu_irq_lower(s->irq); |
| 342 | } |
| 343 | |
| 344 | static const VMStateDescription vmstate_sifive_uart = { |
| 345 | .name = TYPE_SIFIVE_UART, |
| 346 | .version_id = 3, |
| 347 | .minimum_version_id = 3, |
| 348 | .fields = (const VMStateField[]) { |
| 349 | VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState, |
| 350 | SIFIVE_UART_RX_FIFO_SIZE), |
| 351 | VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState), |
| 352 | VMSTATE_UINT32(ie, SiFiveUARTState), |
| 353 | VMSTATE_UINT32(txctrl, SiFiveUARTState), |
| 354 | VMSTATE_UINT32(rxctrl, SiFiveUARTState), |
| 355 | VMSTATE_UINT32(div, SiFiveUARTState), |
| 356 | VMSTATE_UINT32(txfifo, SiFiveUARTState), |
| 357 | VMSTATE_FIFO8(tx_fifo, SiFiveUARTState), |
| 358 | VMSTATE_TIMER_PTR(fifo_trigger_handle, SiFiveUARTState), |
| 359 | VMSTATE_END_OF_LIST() |
| 360 | }, |
| 361 | }; |
| 362 | |
| 363 | |
| 364 | static void sifive_uart_class_init(ObjectClass *oc, const void *data) |
| 365 | { |
| 366 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 367 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 368 | |
| 369 | dc->realize = sifive_uart_realize; |
| 370 | dc->unrealize = sifive_uart_unrealize; |
| 371 | dc->vmsd = &vmstate_sifive_uart; |
| 372 | rc->phases.enter = sifive_uart_reset_enter; |
| 373 | rc->phases.hold = sifive_uart_reset_hold; |
| 374 | device_class_set_props(dc, sifive_uart_properties); |
| 375 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
| 376 | } |
| 377 | |
| 378 | static const TypeInfo sifive_uart_info = { |
| 379 | .name = TYPE_SIFIVE_UART, |
| 380 | .parent = TYPE_SYS_BUS_DEVICE, |
| 381 | .instance_size = sizeof(SiFiveUARTState), |
| 382 | .instance_init = sifive_uart_init, |
| 383 | .class_init = sifive_uart_class_init, |
| 384 | }; |
| 385 | |
| 386 | static void sifive_uart_register_types(void) |
| 387 | { |
| 388 | type_register_static(&sifive_uart_info); |
| 389 | } |
| 390 | |
| 391 | type_init(sifive_uart_register_types) |
| 392 | |
| 393 | /* |
| 394 | * Create UART device. |
| 395 | */ |
| 396 | SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, |
| 397 | Chardev *chr, qemu_irq irq) |
| 398 | { |
| 399 | DeviceState *dev; |
| 400 | SysBusDevice *s; |
| 401 | |
| 402 | dev = qdev_new("riscv.sifive.uart"); |
| 403 | s = SYS_BUS_DEVICE(dev); |
| 404 | qdev_prop_set_chr(dev, "chardev", chr); |
| 405 | sysbus_realize_and_unref(s, &error_fatal); |
| 406 | memory_region_add_subregion(address_space, base, |
| 407 | sysbus_mmio_get_region(s, 0)); |
| 408 | sysbus_connect_irq(s, 0, irq); |
| 409 | |
| 410 | return SIFIVE_UART(dev); |
| 411 | } |