| 1 | /* |
| 2 | * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) |
| 3 | * |
| 4 | * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
| 5 | * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | * |
| 12 | * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart |
| 13 | * by Alistair Francis. |
| 14 | * The reference used is the STMicroElectronics RM0351 Reference manual |
| 15 | * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. |
| 16 | */ |
| 17 | |
| 18 | #include "qemu/osdep.h" |
| 19 | #include "qemu/log.h" |
| 20 | #include "qemu/module.h" |
| 21 | #include "qapi/error.h" |
| 22 | #include "chardev/char-fe.h" |
| 23 | #include "chardev/char-serial.h" |
| 24 | #include "migration/vmstate.h" |
| 25 | #include "hw/char/stm32l4x5_usart.h" |
| 26 | #include "hw/core/clock.h" |
| 27 | #include "hw/core/irq.h" |
| 28 | #include "hw/core/qdev-clock.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "hw/core/qdev-properties-system.h" |
| 31 | #include "hw/core/registerfields.h" |
| 32 | #include "trace.h" |
| 33 | |
| 34 | |
| 35 | REG32(CR1, 0x00) |
| 36 | FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ |
| 37 | FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ |
| 38 | FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ |
| 39 | FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ |
| 40 | FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ |
| 41 | FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ |
| 42 | FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ |
| 43 | FIELD(CR1, MME, 13, 1) /* Mute mode enable */ |
| 44 | FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ |
| 45 | FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ |
| 46 | FIELD(CR1, PCE, 10, 1) /* Parity control enable */ |
| 47 | FIELD(CR1, PS, 9, 1) /* Parity selection */ |
| 48 | FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ |
| 49 | FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ |
| 50 | FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ |
| 51 | FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ |
| 52 | FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ |
| 53 | FIELD(CR1, TE, 3, 1) /* Transmitter enable */ |
| 54 | FIELD(CR1, RE, 2, 1) /* Receiver enable */ |
| 55 | FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ |
| 56 | FIELD(CR1, UE, 0, 1) /* USART enable */ |
| 57 | REG32(CR2, 0x04) |
| 58 | FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ |
| 59 | FIELD(CR2, ADD_0, 24, 4) /* ADD[3:0] */ |
| 60 | FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ |
| 61 | FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ |
| 62 | FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ |
| 63 | FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ |
| 64 | FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ |
| 65 | FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ |
| 66 | FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ |
| 67 | FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ |
| 68 | FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ |
| 69 | FIELD(CR2, STOP, 12, 2) /* STOP bits */ |
| 70 | FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ |
| 71 | FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ |
| 72 | FIELD(CR2, CPHA, 9, 1) /* Clock phase */ |
| 73 | FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ |
| 74 | FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ |
| 75 | FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ |
| 76 | FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ |
| 77 | |
| 78 | REG32(CR3, 0x08) |
| 79 | /* TCBGTIE only on STM32L496xx/4A6xx devices */ |
| 80 | FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ |
| 81 | FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ |
| 82 | FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ |
| 83 | FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ |
| 84 | FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ |
| 85 | FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ |
| 86 | FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ |
| 87 | FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ |
| 88 | FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ |
| 89 | FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ |
| 90 | FIELD(CR3, CTSE, 9, 1) /* CTS enable */ |
| 91 | FIELD(CR3, RTSE, 8, 1) /* RTS enable */ |
| 92 | FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ |
| 93 | FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ |
| 94 | FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ |
| 95 | FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ |
| 96 | FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ |
| 97 | FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ |
| 98 | FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ |
| 99 | FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ |
| 100 | REG32(BRR, 0x0C) |
| 101 | FIELD(BRR, BRR, 0, 16) |
| 102 | REG32(GTPR, 0x10) |
| 103 | FIELD(GTPR, GT, 8, 8) /* Guard time value */ |
| 104 | FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ |
| 105 | REG32(RTOR, 0x14) |
| 106 | FIELD(RTOR, BLEN, 24, 8) /* Block Length */ |
| 107 | FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ |
| 108 | REG32(RQR, 0x18) |
| 109 | FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ |
| 110 | FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ |
| 111 | FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ |
| 112 | FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ |
| 113 | FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ |
| 114 | REG32(ISR, 0x1C) |
| 115 | /* TCBGT only for STM32L475xx/476xx/486xx devices */ |
| 116 | FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ |
| 117 | FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ |
| 118 | FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ |
| 119 | FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ |
| 120 | FIELD(ISR, SBKF, 18, 1) /* Send break flag */ |
| 121 | FIELD(ISR, CMF, 17, 1) /* Character match flag */ |
| 122 | FIELD(ISR, BUSY, 16, 1) /* Busy flag */ |
| 123 | FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ |
| 124 | FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ |
| 125 | FIELD(ISR, EOBF, 12, 1) /* End of block flag */ |
| 126 | FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ |
| 127 | FIELD(ISR, CTS, 10, 1) /* CTS flag */ |
| 128 | FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ |
| 129 | FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ |
| 130 | FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ |
| 131 | FIELD(ISR, TC, 6, 1) /* Transmission complete */ |
| 132 | FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ |
| 133 | FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ |
| 134 | FIELD(ISR, ORE, 3, 1) /* Overrun error */ |
| 135 | FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ |
| 136 | FIELD(ISR, FE, 1, 1) /* Framing Error */ |
| 137 | FIELD(ISR, PE, 0, 1) /* Parity Error */ |
| 138 | REG32(ICR, 0x20) |
| 139 | FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ |
| 140 | FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ |
| 141 | FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ |
| 142 | FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ |
| 143 | FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ |
| 144 | FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ |
| 145 | /* TCBGTCF only on STM32L496xx/4A6xx devices */ |
| 146 | FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ |
| 147 | FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ |
| 148 | FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ |
| 149 | FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ |
| 150 | FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ |
| 151 | FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ |
| 152 | REG32(RDR, 0x24) |
| 153 | FIELD(RDR, RDR, 0, 9) |
| 154 | REG32(TDR, 0x28) |
| 155 | FIELD(TDR, TDR, 0, 9) |
| 156 | |
| 157 | static void stm32l4x5_update_isr(Stm32l4x5UsartBaseState *s) |
| 158 | { |
| 159 | if (s->cr1 & R_CR1_TE_MASK) { |
| 160 | s->isr |= R_ISR_TEACK_MASK; |
| 161 | } else { |
| 162 | s->isr &= ~R_ISR_TEACK_MASK; |
| 163 | } |
| 164 | |
| 165 | if (s->cr1 & R_CR1_RE_MASK) { |
| 166 | s->isr |= R_ISR_REACK_MASK; |
| 167 | } else { |
| 168 | s->isr &= ~R_ISR_REACK_MASK; |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) |
| 173 | { |
| 174 | if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || |
| 175 | ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || |
| 176 | ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || |
| 177 | ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || |
| 178 | ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || |
| 179 | ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || |
| 180 | ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || |
| 181 | ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || |
| 182 | ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || |
| 183 | ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || |
| 184 | ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || |
| 185 | ((s->isr & R_ISR_ORE_MASK) && |
| 186 | ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || |
| 187 | /* TODO: Handle NF ? */ |
| 188 | ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || |
| 189 | ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { |
| 190 | qemu_irq_raise(s->irq); |
| 191 | trace_stm32l4x5_usart_irq_raised(s->isr); |
| 192 | } else { |
| 193 | qemu_irq_lower(s->irq); |
| 194 | trace_stm32l4x5_usart_irq_lowered(); |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | static int stm32l4x5_usart_base_can_receive(void *opaque) |
| 199 | { |
| 200 | Stm32l4x5UsartBaseState *s = opaque; |
| 201 | |
| 202 | if (!(s->isr & R_ISR_RXNE_MASK)) { |
| 203 | return 1; |
| 204 | } |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, |
| 210 | int size) |
| 211 | { |
| 212 | Stm32l4x5UsartBaseState *s = opaque; |
| 213 | |
| 214 | if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { |
| 215 | trace_stm32l4x5_usart_receiver_not_enabled( |
| 216 | FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); |
| 217 | return; |
| 218 | } |
| 219 | |
| 220 | /* Check if overrun detection is enabled and if there is an overrun */ |
| 221 | if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { |
| 222 | /* |
| 223 | * A character has been received while |
| 224 | * the previous has not been read = Overrun. |
| 225 | */ |
| 226 | s->isr |= R_ISR_ORE_MASK; |
| 227 | trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); |
| 228 | } else { |
| 229 | /* No overrun */ |
| 230 | s->rdr = *buf; |
| 231 | s->isr |= R_ISR_RXNE_MASK; |
| 232 | trace_stm32l4x5_usart_rx(s->rdr); |
| 233 | } |
| 234 | |
| 235 | stm32l4x5_update_irq(s); |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * Try to send tx data, and arrange to be called back later if |
| 240 | * we can't (ie the char backend is busy/blocking). |
| 241 | */ |
| 242 | static gboolean usart_transmit(void *do_not_use, GIOCondition cond, |
| 243 | void *opaque) |
| 244 | { |
| 245 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque); |
| 246 | int ret; |
| 247 | /* TODO: Handle 9 bits transmission */ |
| 248 | uint8_t ch = s->tdr; |
| 249 | |
| 250 | s->watch_tag = 0; |
| 251 | |
| 252 | if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { |
| 253 | return G_SOURCE_REMOVE; |
| 254 | } |
| 255 | |
| 256 | ret = qemu_chr_fe_write(&s->chr, &ch, 1); |
| 257 | if (ret <= 0) { |
| 258 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
| 259 | usart_transmit, s); |
| 260 | if (!s->watch_tag) { |
| 261 | /* |
| 262 | * Most common reason to be here is "no chardev backend": |
| 263 | * just insta-drain the buffer, so the serial output |
| 264 | * goes into a void, rather than blocking the guest. |
| 265 | */ |
| 266 | goto buffer_drained; |
| 267 | } |
| 268 | /* Transmit pending */ |
| 269 | trace_stm32l4x5_usart_tx_pending(); |
| 270 | return G_SOURCE_REMOVE; |
| 271 | } |
| 272 | |
| 273 | buffer_drained: |
| 274 | /* Character successfully sent */ |
| 275 | trace_stm32l4x5_usart_tx(ch); |
| 276 | s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; |
| 277 | stm32l4x5_update_irq(s); |
| 278 | return G_SOURCE_REMOVE; |
| 279 | } |
| 280 | |
| 281 | static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) |
| 282 | { |
| 283 | g_clear_handle_id(&s->watch_tag, g_source_remove); |
| 284 | } |
| 285 | |
| 286 | static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s) |
| 287 | { |
| 288 | int speed, parity, data_bits, stop_bits; |
| 289 | uint32_t value, usart_div; |
| 290 | QEMUSerialSetParams ssp; |
| 291 | |
| 292 | /* Select the parity type */ |
| 293 | if (s->cr1 & R_CR1_PCE_MASK) { |
| 294 | if (s->cr1 & R_CR1_PS_MASK) { |
| 295 | parity = 'O'; |
| 296 | } else { |
| 297 | parity = 'E'; |
| 298 | } |
| 299 | } else { |
| 300 | parity = 'N'; |
| 301 | } |
| 302 | |
| 303 | /* Select the number of stop bits */ |
| 304 | switch (FIELD_EX32(s->cr2, CR2, STOP)) { |
| 305 | case 0: |
| 306 | stop_bits = 1; |
| 307 | break; |
| 308 | case 2: |
| 309 | stop_bits = 2; |
| 310 | break; |
| 311 | default: |
| 312 | qemu_log_mask(LOG_UNIMP, |
| 313 | "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u", |
| 314 | FIELD_EX32(s->cr2, CR2, STOP)); |
| 315 | return; |
| 316 | } |
| 317 | |
| 318 | /* Select the length of the word */ |
| 319 | switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { |
| 320 | case 0: |
| 321 | data_bits = 8; |
| 322 | break; |
| 323 | case 1: |
| 324 | data_bits = 9; |
| 325 | break; |
| 326 | case 2: |
| 327 | data_bits = 7; |
| 328 | break; |
| 329 | default: |
| 330 | qemu_log_mask(LOG_GUEST_ERROR, |
| 331 | "UNDEFINED: invalid word length, CR1.M = 0b11"); |
| 332 | return; |
| 333 | } |
| 334 | |
| 335 | /* Select the baud rate */ |
| 336 | value = FIELD_EX32(s->brr, BRR, BRR); |
| 337 | if (value < 16) { |
| 338 | qemu_log_mask(LOG_GUEST_ERROR, |
| 339 | "UNDEFINED: BRR less than 16: %u", value); |
| 340 | return; |
| 341 | } |
| 342 | |
| 343 | if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { |
| 344 | /* |
| 345 | * Oversampling by 16 |
| 346 | * BRR = USARTDIV |
| 347 | */ |
| 348 | usart_div = value; |
| 349 | } else { |
| 350 | /* |
| 351 | * Oversampling by 8 |
| 352 | * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. |
| 353 | * - BRR[3] must be kept cleared. |
| 354 | * - BRR[15:4] = USARTDIV[15:4] |
| 355 | * - The frequency is multiplied by 2 |
| 356 | */ |
| 357 | usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; |
| 358 | } |
| 359 | |
| 360 | speed = clock_get_hz(s->clk) / usart_div; |
| 361 | |
| 362 | ssp.speed = speed; |
| 363 | ssp.parity = parity; |
| 364 | ssp.data_bits = data_bits; |
| 365 | ssp.stop_bits = stop_bits; |
| 366 | |
| 367 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 368 | |
| 369 | trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bits); |
| 370 | } |
| 371 | |
| 372 | static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) |
| 373 | { |
| 374 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); |
| 375 | |
| 376 | s->cr1 = 0x00000000; |
| 377 | s->cr2 = 0x00000000; |
| 378 | s->cr3 = 0x00000000; |
| 379 | s->brr = 0x00000000; |
| 380 | s->gtpr = 0x00000000; |
| 381 | s->rtor = 0x00000000; |
| 382 | s->isr = 0x020000C0; |
| 383 | s->rdr = 0x00000000; |
| 384 | s->tdr = 0x00000000; |
| 385 | |
| 386 | usart_cancel_transmit(s); |
| 387 | stm32l4x5_update_irq(s); |
| 388 | } |
| 389 | |
| 390 | static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) |
| 391 | { |
| 392 | /* TXFRQ */ |
| 393 | /* Reset RXNE flag */ |
| 394 | if (value & R_RQR_RXFRQ_MASK) { |
| 395 | s->isr &= ~R_ISR_RXNE_MASK; |
| 396 | } |
| 397 | /* MMRQ */ |
| 398 | /* SBKRQ */ |
| 399 | /* ABRRQ */ |
| 400 | stm32l4x5_update_irq(s); |
| 401 | } |
| 402 | |
| 403 | static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, |
| 404 | unsigned int size) |
| 405 | { |
| 406 | Stm32l4x5UsartBaseState *s = opaque; |
| 407 | uint64_t retvalue = 0; |
| 408 | |
| 409 | switch (addr) { |
| 410 | case A_CR1: |
| 411 | retvalue = s->cr1; |
| 412 | break; |
| 413 | case A_CR2: |
| 414 | retvalue = s->cr2; |
| 415 | break; |
| 416 | case A_CR3: |
| 417 | retvalue = s->cr3; |
| 418 | break; |
| 419 | case A_BRR: |
| 420 | retvalue = FIELD_EX32(s->brr, BRR, BRR); |
| 421 | break; |
| 422 | case A_GTPR: |
| 423 | retvalue = s->gtpr; |
| 424 | break; |
| 425 | case A_RTOR: |
| 426 | retvalue = s->rtor; |
| 427 | break; |
| 428 | case A_RQR: |
| 429 | /* RQR is a write only register */ |
| 430 | retvalue = 0x00000000; |
| 431 | break; |
| 432 | case A_ISR: |
| 433 | retvalue = s->isr; |
| 434 | break; |
| 435 | case A_ICR: |
| 436 | /* ICR is a clear register */ |
| 437 | retvalue = 0x00000000; |
| 438 | break; |
| 439 | case A_RDR: |
| 440 | retvalue = FIELD_EX32(s->rdr, RDR, RDR); |
| 441 | /* Reset RXNE flag */ |
| 442 | s->isr &= ~R_ISR_RXNE_MASK; |
| 443 | stm32l4x5_update_irq(s); |
| 444 | break; |
| 445 | case A_TDR: |
| 446 | retvalue = FIELD_EX32(s->tdr, TDR, TDR); |
| 447 | break; |
| 448 | default: |
| 449 | qemu_log_mask(LOG_GUEST_ERROR, |
| 450 | "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); |
| 451 | break; |
| 452 | } |
| 453 | |
| 454 | trace_stm32l4x5_usart_read(addr, retvalue); |
| 455 | |
| 456 | return retvalue; |
| 457 | } |
| 458 | |
| 459 | static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, |
| 460 | uint64_t val64, unsigned int size) |
| 461 | { |
| 462 | Stm32l4x5UsartBaseState *s = opaque; |
| 463 | const uint32_t value = val64; |
| 464 | |
| 465 | trace_stm32l4x5_usart_write(addr, value); |
| 466 | |
| 467 | switch (addr) { |
| 468 | case A_CR1: |
| 469 | s->cr1 = value; |
| 470 | stm32l4x5_update_params(s); |
| 471 | stm32l4x5_update_isr(s); |
| 472 | stm32l4x5_update_irq(s); |
| 473 | return; |
| 474 | case A_CR2: |
| 475 | s->cr2 = value; |
| 476 | stm32l4x5_update_params(s); |
| 477 | return; |
| 478 | case A_CR3: |
| 479 | s->cr3 = value; |
| 480 | return; |
| 481 | case A_BRR: |
| 482 | s->brr = value; |
| 483 | stm32l4x5_update_params(s); |
| 484 | return; |
| 485 | case A_GTPR: |
| 486 | s->gtpr = value; |
| 487 | return; |
| 488 | case A_RTOR: |
| 489 | s->rtor = value; |
| 490 | return; |
| 491 | case A_RQR: |
| 492 | usart_update_rqr(s, value); |
| 493 | return; |
| 494 | case A_ISR: |
| 495 | qemu_log_mask(LOG_GUEST_ERROR, |
| 496 | "%s: ISR is read only !\n", __func__); |
| 497 | return; |
| 498 | case A_ICR: |
| 499 | /* Clear the status flags */ |
| 500 | s->isr &= ~value; |
| 501 | stm32l4x5_update_irq(s); |
| 502 | return; |
| 503 | case A_RDR: |
| 504 | qemu_log_mask(LOG_GUEST_ERROR, |
| 505 | "%s: RDR is read only !\n", __func__); |
| 506 | return; |
| 507 | case A_TDR: |
| 508 | s->tdr = value; |
| 509 | s->isr &= ~R_ISR_TXE_MASK; |
| 510 | usart_transmit(NULL, G_IO_OUT, s); |
| 511 | return; |
| 512 | default: |
| 513 | qemu_log_mask(LOG_GUEST_ERROR, |
| 514 | "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | static const MemoryRegionOps stm32l4x5_usart_base_ops = { |
| 519 | .read = stm32l4x5_usart_base_read, |
| 520 | .write = stm32l4x5_usart_base_write, |
| 521 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 522 | .valid = { |
| 523 | .max_access_size = 4, |
| 524 | .min_access_size = 4, |
| 525 | .unaligned = false |
| 526 | }, |
| 527 | .impl = { |
| 528 | .max_access_size = 4, |
| 529 | .min_access_size = 4, |
| 530 | .unaligned = false |
| 531 | }, |
| 532 | }; |
| 533 | |
| 534 | static const Property stm32l4x5_usart_base_properties[] = { |
| 535 | DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), |
| 536 | }; |
| 537 | |
| 538 | static void stm32l4x5_usart_base_init(Object *obj) |
| 539 | { |
| 540 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); |
| 541 | |
| 542 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
| 543 | |
| 544 | memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, |
| 545 | TYPE_STM32L4X5_USART_BASE, 0x400); |
| 546 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); |
| 547 | |
| 548 | s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); |
| 549 | } |
| 550 | |
| 551 | static int stm32l4x5_usart_base_post_load(void *opaque, int version_id) |
| 552 | { |
| 553 | Stm32l4x5UsartBaseState *s = (Stm32l4x5UsartBaseState *)opaque; |
| 554 | |
| 555 | stm32l4x5_update_params(s); |
| 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | static const VMStateDescription vmstate_stm32l4x5_usart_base = { |
| 560 | .name = TYPE_STM32L4X5_USART_BASE, |
| 561 | .version_id = 1, |
| 562 | .minimum_version_id = 1, |
| 563 | .post_load = stm32l4x5_usart_base_post_load, |
| 564 | .fields = (VMStateField[]) { |
| 565 | VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), |
| 566 | VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), |
| 567 | VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), |
| 568 | VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), |
| 569 | VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), |
| 570 | VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), |
| 571 | VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), |
| 572 | VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), |
| 573 | VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), |
| 574 | VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), |
| 575 | VMSTATE_END_OF_LIST() |
| 576 | } |
| 577 | }; |
| 578 | |
| 579 | |
| 580 | static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) |
| 581 | { |
| 582 | ERRP_GUARD(); |
| 583 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); |
| 584 | if (!clock_has_source(s->clk)) { |
| 585 | error_setg(errp, "USART clock must be wired up by SoC code"); |
| 586 | return; |
| 587 | } |
| 588 | |
| 589 | qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, |
| 590 | stm32l4x5_usart_base_receive, NULL, NULL, |
| 591 | s, NULL, true); |
| 592 | } |
| 593 | |
| 594 | static void stm32l4x5_usart_base_class_init(ObjectClass *klass, |
| 595 | const void *data) |
| 596 | { |
| 597 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 598 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 599 | |
| 600 | rc->phases.hold = stm32l4x5_usart_base_reset_hold; |
| 601 | device_class_set_props(dc, stm32l4x5_usart_base_properties); |
| 602 | dc->realize = stm32l4x5_usart_base_realize; |
| 603 | dc->vmsd = &vmstate_stm32l4x5_usart_base; |
| 604 | } |
| 605 | |
| 606 | static void stm32l4x5_usart_class_init(ObjectClass *oc, const void *data) |
| 607 | { |
| 608 | Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); |
| 609 | |
| 610 | subc->type = STM32L4x5_USART; |
| 611 | } |
| 612 | |
| 613 | static void stm32l4x5_uart_class_init(ObjectClass *oc, const void *data) |
| 614 | { |
| 615 | Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); |
| 616 | |
| 617 | subc->type = STM32L4x5_UART; |
| 618 | } |
| 619 | |
| 620 | static void stm32l4x5_lpuart_class_init(ObjectClass *oc, const void *data) |
| 621 | { |
| 622 | Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); |
| 623 | |
| 624 | subc->type = STM32L4x5_LPUART; |
| 625 | } |
| 626 | |
| 627 | static const TypeInfo stm32l4x5_usart_types[] = { |
| 628 | { |
| 629 | .name = TYPE_STM32L4X5_USART_BASE, |
| 630 | .parent = TYPE_SYS_BUS_DEVICE, |
| 631 | .instance_size = sizeof(Stm32l4x5UsartBaseState), |
| 632 | .instance_init = stm32l4x5_usart_base_init, |
| 633 | .class_size = sizeof(Stm32l4x5UsartBaseClass), |
| 634 | .class_init = stm32l4x5_usart_base_class_init, |
| 635 | .abstract = true, |
| 636 | }, { |
| 637 | .name = TYPE_STM32L4X5_USART, |
| 638 | .parent = TYPE_STM32L4X5_USART_BASE, |
| 639 | .class_init = stm32l4x5_usart_class_init, |
| 640 | }, { |
| 641 | .name = TYPE_STM32L4X5_UART, |
| 642 | .parent = TYPE_STM32L4X5_USART_BASE, |
| 643 | .class_init = stm32l4x5_uart_class_init, |
| 644 | }, { |
| 645 | .name = TYPE_STM32L4X5_LPUART, |
| 646 | .parent = TYPE_STM32L4X5_USART_BASE, |
| 647 | .class_init = stm32l4x5_lpuart_class_init, |
| 648 | } |
| 649 | }; |
| 650 | |
| 651 | DEFINE_TYPES(stm32l4x5_usart_types) |