| 1 | /* |
| 2 | * Cortex-A15MPCore internal peripheral emulation. |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited. |
| 5 | * Written by Peter Maydell. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "hw/cpu/a15mpcore.h" |
| 25 | #include "hw/core/cpu.h" |
| 26 | #include "hw/core/irq.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "system/kvm.h" |
| 29 | #include "target/arm/gtimer.h" |
| 30 | |
| 31 | static void a15mp_priv_set_irq(void *opaque, int irq, int level) |
| 32 | { |
| 33 | A15MPPrivState *s = (A15MPPrivState *)opaque; |
| 34 | |
| 35 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); |
| 36 | } |
| 37 | |
| 38 | static void a15mp_priv_initfn(Object *obj) |
| 39 | { |
| 40 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 41 | A15MPPrivState *s = A15MPCORE_PRIV(obj); |
| 42 | |
| 43 | memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); |
| 44 | sysbus_init_mmio(sbd, &s->container); |
| 45 | |
| 46 | object_initialize_child(obj, "gic", &s->gic, gic_class_name()); |
| 47 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); |
| 48 | } |
| 49 | |
| 50 | static void a15mp_priv_realize(DeviceState *dev, Error **errp) |
| 51 | { |
| 52 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 53 | A15MPPrivState *s = A15MPCORE_PRIV(dev); |
| 54 | DeviceState *gicdev; |
| 55 | SysBusDevice *busdev; |
| 56 | int i; |
| 57 | bool has_el3; |
| 58 | bool has_el2 = false; |
| 59 | Object *cpuobj; |
| 60 | |
| 61 | if (s->num_irq < 32 || s->num_irq > 256) { |
| 62 | error_setg(errp, "Property 'num-irq' must be between 32 and 256"); |
| 63 | return; |
| 64 | } |
| 65 | |
| 66 | gicdev = DEVICE(&s->gic); |
| 67 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); |
| 68 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); |
| 69 | |
| 70 | if (!kvm_irqchip_in_kernel()) { |
| 71 | /* Make the GIC's TZ support match the CPUs. We assume that |
| 72 | * either all the CPUs have TZ, or none do. |
| 73 | */ |
| 74 | cpuobj = OBJECT(qemu_get_cpu(0)); |
| 75 | has_el3 = object_property_find(cpuobj, "has_el3") && |
| 76 | object_property_get_bool(cpuobj, "has_el3", &error_abort); |
| 77 | qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); |
| 78 | /* Similarly for virtualization support */ |
| 79 | has_el2 = object_property_find(cpuobj, "has_el2") && |
| 80 | object_property_get_bool(cpuobj, "has_el2", &error_abort); |
| 81 | qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2); |
| 82 | } |
| 83 | |
| 84 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
| 85 | return; |
| 86 | } |
| 87 | busdev = SYS_BUS_DEVICE(&s->gic); |
| 88 | |
| 89 | /* Pass through outbound IRQ lines from the GIC */ |
| 90 | sysbus_pass_irq(sbd, busdev); |
| 91 | |
| 92 | /* Pass through inbound GPIO lines to the GIC */ |
| 93 | qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); |
| 94 | |
| 95 | /* Wire the outputs from each CPU's generic timer to the |
| 96 | * appropriate GIC PPI inputs |
| 97 | */ |
| 98 | for (i = 0; i < s->num_cpu; i++) { |
| 99 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); |
| 100 | int ppibase = s->num_irq - 32 + i * 32; |
| 101 | int irq; |
| 102 | /* Mapping from the output timer irq lines from the CPU to the |
| 103 | * GIC PPI inputs used on the A15: |
| 104 | */ |
| 105 | const int timer_irq[] = { |
| 106 | [GTIMER_PHYS] = 30, |
| 107 | [GTIMER_VIRT] = 27, |
| 108 | [GTIMER_HYP] = 26, |
| 109 | [GTIMER_SEC] = 29, |
| 110 | }; |
| 111 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { |
| 112 | qdev_connect_gpio_out(cpudev, irq, |
| 113 | qdev_get_gpio_in(gicdev, |
| 114 | ppibase + timer_irq[irq])); |
| 115 | } |
| 116 | if (has_el2) { |
| 117 | /* Connect the GIC maintenance interrupt to PPI ID 25 */ |
| 118 | sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu, |
| 119 | qdev_get_gpio_in(gicdev, ppibase + 25)); |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | /* Memory map (addresses are offsets from PERIPHBASE): |
| 124 | * 0x0000-0x0fff -- reserved |
| 125 | * 0x1000-0x1fff -- GIC Distributor |
| 126 | * 0x2000-0x3fff -- GIC CPU interface |
| 127 | * 0x4000-0x4fff -- GIC virtual interface control for this CPU |
| 128 | * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 |
| 129 | * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 |
| 130 | * 0x5400-0x55ff -- GIC virtual interface control for CPU 2 |
| 131 | * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 |
| 132 | * 0x6000-0x7fff -- GIC virtual CPU interface |
| 133 | */ |
| 134 | memory_region_add_subregion(&s->container, 0x1000, |
| 135 | sysbus_mmio_get_region(busdev, 0)); |
| 136 | memory_region_add_subregion(&s->container, 0x2000, |
| 137 | sysbus_mmio_get_region(busdev, 1)); |
| 138 | if (has_el2) { |
| 139 | memory_region_add_subregion(&s->container, 0x4000, |
| 140 | sysbus_mmio_get_region(busdev, 2)); |
| 141 | memory_region_add_subregion(&s->container, 0x6000, |
| 142 | sysbus_mmio_get_region(busdev, 3)); |
| 143 | for (i = 0; i < s->num_cpu; i++) { |
| 144 | hwaddr base = 0x5000 + i * 0x200; |
| 145 | MemoryRegion *mr = sysbus_mmio_get_region(busdev, |
| 146 | 4 + s->num_cpu + i); |
| 147 | memory_region_add_subregion(&s->container, base, mr); |
| 148 | } |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | static const Property a15mp_priv_properties[] = { |
| 153 | DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), |
| 154 | /* |
| 155 | * The Cortex-A15MP may have anything from 0 to 224 external interrupt |
| 156 | * lines, plus always 32 internal IRQs. This property sets the total |
| 157 | * of internal + external, so the valid range is from 32 to 256. |
| 158 | * The board model must set this to whatever the configuration |
| 159 | * used for the CPU on that board or SoC is. |
| 160 | */ |
| 161 | DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0), |
| 162 | }; |
| 163 | |
| 164 | static void a15mp_priv_class_init(ObjectClass *klass, const void *data) |
| 165 | { |
| 166 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 167 | |
| 168 | dc->realize = a15mp_priv_realize; |
| 169 | device_class_set_props(dc, a15mp_priv_properties); |
| 170 | /* We currently have no saveable state */ |
| 171 | } |
| 172 | |
| 173 | static const TypeInfo a15mp_types[] = { |
| 174 | { |
| 175 | .name = TYPE_A15MPCORE_PRIV, |
| 176 | .parent = TYPE_SYS_BUS_DEVICE, |
| 177 | .instance_size = sizeof(A15MPPrivState), |
| 178 | .instance_init = a15mp_priv_initfn, |
| 179 | .class_init = a15mp_priv_class_init, |
| 180 | }, |
| 181 | }; |
| 182 | |
| 183 | DEFINE_TYPES(a15mp_types) |