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1 /*
2 * QEMU ATI SVGA emulation
3 *
4 * Copyright (c) 2019 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 */
8
9 #ifndef ATI_INT_H
10 #define ATI_INT_H
11
12 #include "qemu/timer.h"
13 #include "qemu/units.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/i2c/bitbang_i2c.h"
16 #include "hw/display/i2c-ddc.h"
17 #include "vga_int.h"
18 #include "qom/object.h"
19
20 /*#define DEBUG_ATI*/
21
22 #ifdef DEBUG_ATI
23 #define DPRINTF(fmt, ...) printf("%s: " fmt, __func__, ## __VA_ARGS__)
24 #else
25 #define DPRINTF(fmt, ...) do {} while (0)
26 #endif
27
28 #define PCI_VENDOR_ID_ATI 0x1002
29 /* Rage128 Pro GL */
30 #define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
31 /* Radeon RV100 (VE) */
32 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
33
34 #define ATI_RAGE128_LINEAR_APER_SIZE (64 * MiB)
35 #define ATI_R100_LINEAR_APER_SIZE (128 * MiB)
36 #define ATI_HOST_DATA_ACC_BITS 128
37
38 #define TYPE_ATI_VGA "ati-vga"
39 OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA)
40
41 typedef struct ATIVGARegs {
42 uint32_t mm_index;
43 uint32_t bios_scratch[8];
44 uint32_t gen_int_cntl;
45 uint32_t gen_int_status;
46 uint32_t crtc_gen_cntl;
47 uint32_t crtc_ext_cntl;
48 uint32_t dac_cntl;
49 uint32_t gpio_vga_ddc;
50 uint32_t gpio_dvi_ddc;
51 uint32_t gpio_monid;
52 uint32_t config_cntl;
53 uint32_t palette[256];
54 uint32_t crtc_h_total_disp;
55 uint32_t crtc_h_sync_strt_wid;
56 uint32_t crtc_v_total_disp;
57 uint32_t crtc_v_sync_strt_wid;
58 uint32_t crtc_offset;
59 uint32_t crtc_offset_cntl;
60 uint32_t crtc_pitch;
61 uint32_t cur_offset;
62 uint32_t cur_hv_pos;
63 uint32_t cur_hv_offs;
64 uint32_t cur_color0;
65 uint32_t cur_color1;
66 uint32_t dst_offset;
67 uint32_t dst_pitch;
68 uint32_t dst_tile;
69 uint32_t dst_width;
70 uint32_t dst_height;
71 uint32_t src_offset;
72 uint32_t src_pitch;
73 uint32_t src_tile;
74 uint32_t src_x;
75 uint32_t src_y;
76 uint32_t dst_x;
77 uint32_t dst_y;
78 uint32_t dp_gui_master_cntl;
79 uint32_t dp_brush_bkgd_clr;
80 uint32_t dp_brush_frgd_clr;
81 uint32_t dp_src_frgd_clr;
82 uint32_t dp_src_bkgd_clr;
83 uint16_t sc_top;
84 uint16_t sc_left;
85 uint16_t sc_bottom;
86 uint16_t sc_right;
87 uint16_t src_sc_bottom;
88 uint16_t src_sc_right;
89 uint32_t dp_cntl;
90 uint32_t dp_datatype;
91 uint32_t dp_mix;
92 uint32_t dp_write_mask;
93 uint32_t default_offset;
94 uint32_t default_pitch;
95 uint16_t default_sc_bottom;
96 uint16_t default_sc_right;
97 uint32_t default_tile;
98 } ATIVGARegs;
99
100 typedef struct ATIHostDataState {
101 bool active;
102 uint32_t row;
103 uint32_t col;
104 uint32_t next;
105 uint32_t acc[4];
106 } ATIHostDataState;
107
108 struct ATIVGAState {
109 PCIDevice dev;
110 VGACommonState vga;
111 char *model;
112 uint16_t dev_id;
113 uint8_t mode;
114 uint8_t use_pixman;
115 bool cursor_guest_mode;
116 uint16_t cursor_size;
117 uint32_t cursor_offset;
118 QEMUCursor *cursor;
119 QEMUTimer vblank_timer;
120 bitbang_i2c_interface bbi2c;
121 I2CDDCState i2cddc;
122 uint64_t linear_aper_sz;
123 MemoryRegion linear_aper;
124 MemoryRegion io;
125 MemoryRegion mm;
126 ATIVGARegs regs;
127 ATIHostDataState host_data;
128 };
129
130 const char *ati_reg_name(int num);
131
132 void ati_2d_blt(ATIVGAState *s);
133 bool ati_host_data_flush(ATIVGAState *s);
134 void ati_host_data_finish(ATIVGAState *s);
135
136 #endif /* ATI_INT_H */