| 1 | /* |
| 2 | * QEMU CG3 Frame buffer |
| 3 | * |
| 4 | * Copyright (c) 2012 Bob Breuer |
| 5 | * Copyright (c) 2013 Mark Cave-Ayland |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "qemu/datadir.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "qemu/error-report.h" |
| 30 | #include "ui/console.h" |
| 31 | #include "hw/core/sysbus.h" |
| 32 | #include "migration/vmstate.h" |
| 33 | #include "hw/core/irq.h" |
| 34 | #include "hw/core/loader.h" |
| 35 | #include "hw/core/qdev-properties.h" |
| 36 | #include "qemu/log.h" |
| 37 | #include "qemu/module.h" |
| 38 | #include "trace.h" |
| 39 | #include "qom/object.h" |
| 40 | |
| 41 | /* Change to 1 to enable debugging */ |
| 42 | #define DEBUG_CG3 0 |
| 43 | |
| 44 | #define CG3_ROM_FILE "QEMU,cgthree.bin" |
| 45 | #define FCODE_MAX_ROM_SIZE 0x10000 |
| 46 | |
| 47 | #define CG3_REG_SIZE 0x20 |
| 48 | |
| 49 | #define CG3_REG_BT458_ADDR 0x0 |
| 50 | #define CG3_REG_BT458_COLMAP 0x4 |
| 51 | #define CG3_REG_FBC_CTRL 0x10 |
| 52 | #define CG3_REG_FBC_STATUS 0x11 |
| 53 | #define CG3_REG_FBC_CURSTART 0x12 |
| 54 | #define CG3_REG_FBC_CUREND 0x13 |
| 55 | #define CG3_REG_FBC_VCTRL 0x14 |
| 56 | |
| 57 | /* Control register flags */ |
| 58 | #define CG3_CR_ENABLE_INTS 0x80 |
| 59 | |
| 60 | /* Status register flags */ |
| 61 | #define CG3_SR_PENDING_INT 0x80 |
| 62 | #define CG3_SR_1152_900_76_B 0x60 |
| 63 | #define CG3_SR_ID_COLOR 0x01 |
| 64 | |
| 65 | #define CG3_VRAM_SIZE 0x100000 |
| 66 | #define CG3_VRAM_OFFSET 0x800000 |
| 67 | |
| 68 | #define TYPE_CG3 "cgthree" |
| 69 | OBJECT_DECLARE_SIMPLE_TYPE(CG3State, CG3) |
| 70 | |
| 71 | struct CG3State { |
| 72 | SysBusDevice parent_obj; |
| 73 | |
| 74 | QemuConsole *con; |
| 75 | qemu_irq irq; |
| 76 | hwaddr prom_addr; |
| 77 | MemoryRegion vram_mem; |
| 78 | MemoryRegion rom; |
| 79 | MemoryRegion reg; |
| 80 | uint32_t vram_size; |
| 81 | int full_update; |
| 82 | uint8_t regs[16]; |
| 83 | uint8_t r[256], g[256], b[256]; |
| 84 | uint16_t width, height, depth; |
| 85 | uint8_t dac_index, dac_state; |
| 86 | }; |
| 87 | |
| 88 | static bool cg3_update_display(void *opaque) |
| 89 | { |
| 90 | CG3State *s = opaque; |
| 91 | DisplaySurface *surface = qemu_console_surface(s->con); |
| 92 | const uint8_t *pix; |
| 93 | uint32_t *data; |
| 94 | uint32_t dval; |
| 95 | int x, y, y_start; |
| 96 | unsigned int width, height; |
| 97 | ram_addr_t page; |
| 98 | DirtyBitmapSnapshot *snap = NULL; |
| 99 | |
| 100 | if (surface_bits_per_pixel(surface) != 32) { |
| 101 | return true; |
| 102 | } |
| 103 | width = s->width; |
| 104 | height = s->height; |
| 105 | |
| 106 | y_start = -1; |
| 107 | pix = memory_region_get_ram_ptr(&s->vram_mem); |
| 108 | data = (uint32_t *)surface_data(surface); |
| 109 | |
| 110 | if (!s->full_update) { |
| 111 | snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0, |
| 112 | memory_region_size(&s->vram_mem), |
| 113 | DIRTY_MEMORY_VGA); |
| 114 | } |
| 115 | |
| 116 | for (y = 0; y < height; y++) { |
| 117 | int update; |
| 118 | |
| 119 | page = (ram_addr_t)y * width; |
| 120 | |
| 121 | if (s->full_update) { |
| 122 | update = 1; |
| 123 | } else { |
| 124 | update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page, |
| 125 | width); |
| 126 | } |
| 127 | |
| 128 | if (update) { |
| 129 | if (y_start < 0) { |
| 130 | y_start = y; |
| 131 | } |
| 132 | |
| 133 | for (x = 0; x < width; x++) { |
| 134 | dval = *pix++; |
| 135 | dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; |
| 136 | *data++ = dval; |
| 137 | } |
| 138 | } else { |
| 139 | if (y_start >= 0) { |
| 140 | qemu_console_update(s->con, 0, y_start, width, y - y_start); |
| 141 | y_start = -1; |
| 142 | } |
| 143 | pix += width; |
| 144 | data += width; |
| 145 | } |
| 146 | } |
| 147 | s->full_update = 0; |
| 148 | if (y_start >= 0) { |
| 149 | qemu_console_update(s->con, 0, y_start, width, y - y_start); |
| 150 | } |
| 151 | /* vsync interrupt? */ |
| 152 | if (s->regs[0] & CG3_CR_ENABLE_INTS) { |
| 153 | s->regs[1] |= CG3_SR_PENDING_INT; |
| 154 | qemu_irq_raise(s->irq); |
| 155 | } |
| 156 | g_free(snap); |
| 157 | return true; |
| 158 | } |
| 159 | |
| 160 | static void cg3_invalidate_display(void *opaque) |
| 161 | { |
| 162 | CG3State *s = opaque; |
| 163 | |
| 164 | memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); |
| 165 | } |
| 166 | |
| 167 | static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) |
| 168 | { |
| 169 | CG3State *s = opaque; |
| 170 | int val; |
| 171 | |
| 172 | switch (addr) { |
| 173 | case CG3_REG_BT458_ADDR: |
| 174 | case CG3_REG_BT458_COLMAP: |
| 175 | val = 0; |
| 176 | break; |
| 177 | case CG3_REG_FBC_CTRL: |
| 178 | val = s->regs[0]; |
| 179 | break; |
| 180 | case CG3_REG_FBC_STATUS: |
| 181 | /* monitor ID 6, board type = 1 (color) */ |
| 182 | val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; |
| 183 | break; |
| 184 | case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: |
| 185 | val = s->regs[addr - 0x10]; |
| 186 | break; |
| 187 | default: |
| 188 | qemu_log_mask(LOG_UNIMP, |
| 189 | "cg3: Unimplemented register read " |
| 190 | "reg 0x%" HWADDR_PRIx " size 0x%x\n", |
| 191 | addr, size); |
| 192 | val = 0; |
| 193 | break; |
| 194 | } |
| 195 | trace_cg3_read(addr, val, size); |
| 196 | |
| 197 | return val; |
| 198 | } |
| 199 | |
| 200 | static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, |
| 201 | unsigned size) |
| 202 | { |
| 203 | CG3State *s = opaque; |
| 204 | uint8_t regval; |
| 205 | int i; |
| 206 | |
| 207 | trace_cg3_write(addr, val, size); |
| 208 | switch (addr) { |
| 209 | case CG3_REG_BT458_ADDR: |
| 210 | s->dac_index = val; |
| 211 | s->dac_state = 0; |
| 212 | break; |
| 213 | case CG3_REG_BT458_COLMAP: |
| 214 | /* This register can be written to as either a long word or a byte */ |
| 215 | if (size == 1) { |
| 216 | val <<= 24; |
| 217 | } |
| 218 | |
| 219 | for (i = 0; i < size; i++) { |
| 220 | regval = val >> 24; |
| 221 | |
| 222 | switch (s->dac_state) { |
| 223 | case 0: |
| 224 | s->r[s->dac_index] = regval; |
| 225 | s->dac_state++; |
| 226 | break; |
| 227 | case 1: |
| 228 | s->g[s->dac_index] = regval; |
| 229 | s->dac_state++; |
| 230 | break; |
| 231 | case 2: |
| 232 | s->b[s->dac_index] = regval; |
| 233 | /* Index autoincrement */ |
| 234 | s->dac_index = (s->dac_index + 1) & 0xff; |
| 235 | /* fall through */ |
| 236 | default: |
| 237 | s->dac_state = 0; |
| 238 | break; |
| 239 | } |
| 240 | val <<= 8; |
| 241 | } |
| 242 | s->full_update = 1; |
| 243 | break; |
| 244 | case CG3_REG_FBC_CTRL: |
| 245 | s->regs[0] = val; |
| 246 | break; |
| 247 | case CG3_REG_FBC_STATUS: |
| 248 | if (s->regs[1] & CG3_SR_PENDING_INT) { |
| 249 | /* clear interrupt */ |
| 250 | s->regs[1] &= ~CG3_SR_PENDING_INT; |
| 251 | qemu_irq_lower(s->irq); |
| 252 | } |
| 253 | break; |
| 254 | case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: |
| 255 | s->regs[addr - 0x10] = val; |
| 256 | break; |
| 257 | default: |
| 258 | qemu_log_mask(LOG_UNIMP, |
| 259 | "cg3: Unimplemented register write " |
| 260 | "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", |
| 261 | addr, size, val); |
| 262 | break; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | static const MemoryRegionOps cg3_reg_ops = { |
| 267 | .read = cg3_reg_read, |
| 268 | .write = cg3_reg_write, |
| 269 | .endianness = DEVICE_BIG_ENDIAN, |
| 270 | .valid = { |
| 271 | .min_access_size = 1, |
| 272 | .max_access_size = 4, |
| 273 | }, |
| 274 | }; |
| 275 | |
| 276 | static const GraphicHwOps cg3_ops = { |
| 277 | .invalidate = cg3_invalidate_display, |
| 278 | .gfx_update = cg3_update_display, |
| 279 | }; |
| 280 | |
| 281 | static void cg3_realizefn(DeviceState *dev, Error **errp) |
| 282 | { |
| 283 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 284 | Object *obj = OBJECT(dev); |
| 285 | CG3State *s = CG3(dev); |
| 286 | int ret; |
| 287 | char *fcode_filename; |
| 288 | |
| 289 | memory_region_init_rom(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE, |
| 290 | &error_fatal); |
| 291 | sysbus_init_mmio(sbd, &s->rom); |
| 292 | |
| 293 | memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", |
| 294 | CG3_REG_SIZE); |
| 295 | sysbus_init_mmio(sbd, &s->reg); |
| 296 | |
| 297 | /* FCode ROM */ |
| 298 | fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); |
| 299 | if (fcode_filename) { |
| 300 | ret = load_image_mr(fcode_filename, &s->rom); |
| 301 | g_free(fcode_filename); |
| 302 | if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { |
| 303 | warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, |
| 308 | &error_fatal); |
| 309 | memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); |
| 310 | sysbus_init_mmio(sbd, &s->vram_mem); |
| 311 | |
| 312 | sysbus_init_irq(sbd, &s->irq); |
| 313 | |
| 314 | s->con = qemu_graphic_console_create(dev, 0, &cg3_ops, s); |
| 315 | qemu_console_resize(s->con, s->width, s->height); |
| 316 | } |
| 317 | |
| 318 | static int vmstate_cg3_post_load(void *opaque, int version_id) |
| 319 | { |
| 320 | CG3State *s = opaque; |
| 321 | |
| 322 | cg3_invalidate_display(s); |
| 323 | |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | static const VMStateDescription vmstate_cg3 = { |
| 328 | .name = "cg3", |
| 329 | .version_id = 1, |
| 330 | .minimum_version_id = 1, |
| 331 | .post_load = vmstate_cg3_post_load, |
| 332 | .fields = (const VMStateField[]) { |
| 333 | VMSTATE_UINT16(height, CG3State), |
| 334 | VMSTATE_UINT16(width, CG3State), |
| 335 | VMSTATE_UINT16(depth, CG3State), |
| 336 | VMSTATE_BUFFER(r, CG3State), |
| 337 | VMSTATE_BUFFER(g, CG3State), |
| 338 | VMSTATE_BUFFER(b, CG3State), |
| 339 | VMSTATE_UINT8(dac_index, CG3State), |
| 340 | VMSTATE_UINT8(dac_state, CG3State), |
| 341 | VMSTATE_END_OF_LIST() |
| 342 | } |
| 343 | }; |
| 344 | |
| 345 | static void cg3_reset(DeviceState *d) |
| 346 | { |
| 347 | CG3State *s = CG3(d); |
| 348 | |
| 349 | /* Initialize palette */ |
| 350 | memset(s->r, 0, 256); |
| 351 | memset(s->g, 0, 256); |
| 352 | memset(s->b, 0, 256); |
| 353 | |
| 354 | s->dac_state = 0; |
| 355 | s->full_update = 1; |
| 356 | qemu_irq_lower(s->irq); |
| 357 | } |
| 358 | |
| 359 | static const Property cg3_properties[] = { |
| 360 | DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), |
| 361 | DEFINE_PROP_UINT16("width", CG3State, width, -1), |
| 362 | DEFINE_PROP_UINT16("height", CG3State, height, -1), |
| 363 | DEFINE_PROP_UINT16("depth", CG3State, depth, -1), |
| 364 | }; |
| 365 | |
| 366 | static void cg3_class_init(ObjectClass *klass, const void *data) |
| 367 | { |
| 368 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 369 | |
| 370 | dc->realize = cg3_realizefn; |
| 371 | device_class_set_legacy_reset(dc, cg3_reset); |
| 372 | dc->vmsd = &vmstate_cg3; |
| 373 | device_class_set_props(dc, cg3_properties); |
| 374 | } |
| 375 | |
| 376 | static const TypeInfo cg3_info = { |
| 377 | .name = TYPE_CG3, |
| 378 | .parent = TYPE_SYS_BUS_DEVICE, |
| 379 | .instance_size = sizeof(CG3State), |
| 380 | .class_init = cg3_class_init, |
| 381 | }; |
| 382 | |
| 383 | static void cg3_register_types(void) |
| 384 | { |
| 385 | type_register_static(&cg3_info); |
| 386 | } |
| 387 | |
| 388 | type_init(cg3_register_types) |