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1 /*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
8 *
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/core/qdev-properties.h"
27 #include "hw/core/irq.h"
28 #include "hw/core/sysbus.h"
29 #include "exec/cpu-common.h"
30 #include "migration/vmstate.h"
31 #include "system/physmem.h"
32 #include "ui/console.h"
33 #include "ui/pixel_ops.h"
34 #include "qemu/bswap.h"
35 #include "qemu/module.h"
36 #include "qemu/log.h"
37 #include "qapi/error.h"
38 #include "qom/object.h"
39
40 /* Debug messages configuration */
41 #define EXYNOS4210_FIMD_DEBUG 0
42 #define EXYNOS4210_FIMD_MODE_TRACE 0
43
44 #if EXYNOS4210_FIMD_DEBUG == 0
45 #define DPRINT_L1(fmt, args...) do { } while (0)
46 #define DPRINT_L2(fmt, args...) do { } while (0)
47 #elif EXYNOS4210_FIMD_DEBUG == 1
48 #define DPRINT_L1(fmt, args...) \
49 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
50 #define DPRINT_L2(fmt, args...) do { } while (0)
51 #else
52 #define DPRINT_L1(fmt, args...) \
53 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
54 #define DPRINT_L2(fmt, args...) \
55 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
56 #endif
57
58 #if EXYNOS4210_FIMD_MODE_TRACE == 0
59 #define DPRINT_TRACE(fmt, args...) do { } while (0)
60 #else
61 #define DPRINT_TRACE(fmt, args...) \
62 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
63 #endif
64
65 #define NUM_OF_WINDOWS 5
66 #define FIMD_REGS_SIZE 0x4114
67
68 /* Video main control registers */
69 #define FIMD_VIDCON0 0x0000
70 #define FIMD_VIDCON1 0x0004
71 #define FIMD_VIDCON2 0x0008
72 #define FIMD_VIDCON3 0x000C
73 #define FIMD_VIDCON0_ENVID_F (1 << 0)
74 #define FIMD_VIDCON0_ENVID (1 << 1)
75 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
76 #define FIMD_VIDCON1_ROMASK 0x07FFE000
77
78 /* Video time control registers */
79 #define FIMD_VIDTCON_START 0x10
80 #define FIMD_VIDTCON_END 0x1C
81 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF
82 #define FIMD_VIDTCON2_HOR_SHIFT 0
83 #define FIMD_VIDTCON2_VER_SHIFT 11
84
85 /* Window control registers */
86 #define FIMD_WINCON_START 0x0020
87 #define FIMD_WINCON_END 0x0030
88 #define FIMD_WINCON_ROMASK 0x82200000
89 #define FIMD_WINCON_ENWIN (1 << 0)
90 #define FIMD_WINCON_BLD_PIX (1 << 6)
91 #define FIMD_WINCON_ALPHA_MUL (1 << 7)
92 #define FIMD_WINCON_ALPHA_SEL (1 << 1)
93 #define FIMD_WINCON_SWAP 0x078000
94 #define FIMD_WINCON_SWAP_SHIFT 15
95 #define FIMD_WINCON_SWAP_WORD 0x1
96 #define FIMD_WINCON_SWAP_HWORD 0x2
97 #define FIMD_WINCON_SWAP_BYTE 0x4
98 #define FIMD_WINCON_SWAP_BITS 0x8
99 #define FIMD_WINCON_BUFSTAT_L (1 << 21)
100 #define FIMD_WINCON_BUFSTAT_H (1 << 31)
101 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31))
102 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
103 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
104 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31))
105 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30))
106 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
107 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
108 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
109 #define FIMD_WINCON_BUFMODE (1 << 14)
110 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
111 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7)
112 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
113 #define WIN_BPP_MODE_WITH_ALPHA(w) \
114 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
115
116 /* Shadow control register */
117 #define FIMD_SHADOWCON 0x0034
118 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
119 /* Channel mapping control register */
120 #define FIMD_WINCHMAP 0x003C
121
122 /* Window position control registers */
123 #define FIMD_VIDOSD_START 0x0040
124 #define FIMD_VIDOSD_END 0x0088
125 #define FIMD_VIDOSD_COORD_MASK 0x07FF
126 #define FIMD_VIDOSD_HOR_SHIFT 11
127 #define FIMD_VIDOSD_VER_SHIFT 0
128 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
129 #define FIMD_VIDOSD_AEN0_SHIFT 12
130 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
131
132 /* Frame buffer address registers */
133 #define FIMD_VIDWADD0_START 0x00A0
134 #define FIMD_VIDWADD0_END 0x00C4
135 #define FIMD_VIDWADD1_START 0x00D0
136 #define FIMD_VIDWADD1_END 0x00F4
137 #define FIMD_VIDWADD2_START 0x0100
138 #define FIMD_VIDWADD2_END 0x0110
139 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
140 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF
141 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
142 #define FIMD_VIDW0ADD0_B2 0x20A0
143 #define FIMD_VIDW4ADD0_B2 0x20C0
144
145 /* Video interrupt control registers */
146 #define FIMD_VIDINTCON0 0x130
147 #define FIMD_VIDINTCON1 0x134
148
149 /* Window color key registers */
150 #define FIMD_WKEYCON_START 0x140
151 #define FIMD_WKEYCON_END 0x15C
152 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
153 #define FIMD_WKEYCON0_CTL_SHIFT 24
154 #define FIMD_WKEYCON0_DIRCON (1 << 24)
155 #define FIMD_WKEYCON0_KEYEN (1 << 25)
156 #define FIMD_WKEYCON0_KEYBLEN (1 << 26)
157 /* Window color key alpha control register */
158 #define FIMD_WKEYALPHA_START 0x160
159 #define FIMD_WKEYALPHA_END 0x16C
160
161 /* Dithering control register */
162 #define FIMD_DITHMODE 0x170
163
164 /* Window alpha control registers */
165 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
166 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
167 #define FIMD_VIDWALPHA_START 0x21C
168 #define FIMD_VIDWALPHA_END 0x240
169
170 /* Window color map registers */
171 #define FIMD_WINMAP_START 0x180
172 #define FIMD_WINMAP_END 0x190
173 #define FIMD_WINMAP_EN (1 << 24)
174 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
175
176 /* Window palette control registers */
177 #define FIMD_WPALCON_HIGH 0x019C
178 #define FIMD_WPALCON_LOW 0x01A0
179 #define FIMD_WPALCON_UPDATEEN (1 << 9)
180 #define FIMD_WPAL_W0PAL_L 0x07
181 #define FIMD_WPAL_W0PAL_L_SHT 0
182 #define FIMD_WPAL_W1PAL_L 0x07
183 #define FIMD_WPAL_W1PAL_L_SHT 3
184 #define FIMD_WPAL_W2PAL_L 0x01
185 #define FIMD_WPAL_W2PAL_L_SHT 6
186 #define FIMD_WPAL_W2PAL_H 0x06
187 #define FIMD_WPAL_W2PAL_H_SHT 8
188 #define FIMD_WPAL_W3PAL_L 0x01
189 #define FIMD_WPAL_W3PAL_L_SHT 7
190 #define FIMD_WPAL_W3PAL_H 0x06
191 #define FIMD_WPAL_W3PAL_H_SHT 12
192 #define FIMD_WPAL_W4PAL_L 0x01
193 #define FIMD_WPAL_W4PAL_L_SHT 8
194 #define FIMD_WPAL_W4PAL_H 0x06
195 #define FIMD_WPAL_W4PAL_H_SHT 16
196
197 /* Trigger control registers */
198 #define FIMD_TRIGCON 0x01A4
199 #define FIMD_TRIGCON_ROMASK 0x00000004
200
201 /* LCD I80 Interface Control */
202 #define FIMD_I80IFCON_START 0x01B0
203 #define FIMD_I80IFCON_END 0x01BC
204 /* Color gain control register */
205 #define FIMD_COLORGAINCON 0x01C0
206 /* LCD i80 Interface Command Control */
207 #define FIMD_LDI_CMDCON0 0x01D0
208 #define FIMD_LDI_CMDCON1 0x01D4
209 /* I80 System Interface Manual Command Control */
210 #define FIMD_SIFCCON0 0x01E0
211 #define FIMD_SIFCCON2 0x01E8
212
213 /* Hue Control Registers */
214 #define FIMD_HUECOEFCR_START 0x01EC
215 #define FIMD_HUECOEFCR_END 0x01F4
216 #define FIMD_HUECOEFCB_START 0x01FC
217 #define FIMD_HUECOEFCB_END 0x0208
218 #define FIMD_HUEOFFSET 0x020C
219
220 /* Video interrupt control registers */
221 #define FIMD_VIDINT_INTFIFOPEND (1 << 0)
222 #define FIMD_VIDINT_INTFRMPEND (1 << 1)
223 #define FIMD_VIDINT_INTI80PEND (1 << 2)
224 #define FIMD_VIDINT_INTEN (1 << 0)
225 #define FIMD_VIDINT_INTFIFOEN (1 << 1)
226 #define FIMD_VIDINT_INTFRMEN (1 << 12)
227 #define FIMD_VIDINT_I80IFDONE (1 << 17)
228
229 /* Window blend equation control registers */
230 #define FIMD_BLENDEQ_START 0x0244
231 #define FIMD_BLENDEQ_END 0x0250
232 #define FIMD_BLENDCON 0x0260
233 #define FIMD_ALPHA_8BIT (1 << 0)
234 #define FIMD_BLENDEQ_COEF_MASK 0xF
235
236 /* Window RTQOS Control Registers */
237 #define FIMD_WRTQOSCON_START 0x0264
238 #define FIMD_WRTQOSCON_END 0x0274
239
240 /* LCD I80 Interface Command */
241 #define FIMD_I80IFCMD_START 0x0280
242 #define FIMD_I80IFCMD_END 0x02AC
243
244 /* Shadow windows control registers */
245 #define FIMD_SHD_ADD0_START 0x40A0
246 #define FIMD_SHD_ADD0_END 0x40C0
247 #define FIMD_SHD_ADD1_START 0x40D0
248 #define FIMD_SHD_ADD1_END 0x40F0
249 #define FIMD_SHD_ADD2_START 0x4100
250 #define FIMD_SHD_ADD2_END 0x4110
251
252 /* Palette memory */
253 #define FIMD_PAL_MEM_START 0x2400
254 #define FIMD_PAL_MEM_END 0x37FC
255 /* Palette memory aliases for windows 0 and 1 */
256 #define FIMD_PALMEM_AL_START 0x0400
257 #define FIMD_PALMEM_AL_END 0x0BFC
258
259 typedef struct {
260 uint8_t r, g, b;
261 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
262 uint32_t a;
263 } rgba;
264 #define RGBA_SIZE 7
265
266 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
267 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
268
269 struct Exynos4210fimdWindow {
270 uint32_t wincon; /* Window control register */
271 uint32_t buf_start[3]; /* Start address for video frame buffer */
272 uint32_t buf_end[3]; /* End address for video frame buffer */
273 uint32_t keycon[2]; /* Window color key registers */
274 uint32_t keyalpha; /* Color key alpha control register */
275 uint32_t winmap; /* Window color map register */
276 uint32_t blendeq; /* Window blending equation control register */
277 uint32_t rtqoscon; /* Window RTQOS Control Registers */
278 uint32_t palette[256]; /* Palette RAM */
279 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
280 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
281 uint32_t shadow_buf_size; /* Virtual shadow screen width */
282
283 pixel_to_rgb_func *pixel_to_rgb;
284 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
285 uint32_t width, bool blend);
286 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
287 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
288 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
289 uint32_t osdsize; /* VIDOSD2&3 register */
290 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
291 uint16_t virtpage_width; /* VIDWADD2 register */
292 uint16_t virtpage_offsize; /* VIDWADD2 register */
293 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
294 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
295 hwaddr fb_len; /* Framebuffer length */
296 };
297
298 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
299 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210fimdState, EXYNOS4210_FIMD)
300
301 struct Exynos4210fimdState {
302 SysBusDevice parent_obj;
303
304 MemoryRegion iomem;
305 QemuConsole *console;
306 qemu_irq irq[3];
307 MemoryRegion *fbmem;
308
309 uint32_t vidcon[4]; /* Video main control registers 0-3 */
310 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
311 uint32_t shadowcon; /* Window shadow control register */
312 uint32_t winchmap; /* Channel mapping control register */
313 uint32_t vidintcon[2]; /* Video interrupt control registers */
314 uint32_t dithmode; /* Dithering control register */
315 uint32_t wpalcon[2]; /* Window palette control registers */
316 uint32_t trigcon; /* Trigger control register */
317 uint32_t i80ifcon[4]; /* I80 interface control registers */
318 uint32_t colorgaincon; /* Color gain control register */
319 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
320 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
321 uint32_t huecoef_cr[4]; /* Hue control registers */
322 uint32_t huecoef_cb[4]; /* Hue control registers */
323 uint32_t hueoffset; /* Hue offset control register */
324 uint32_t blendcon; /* Blending control register */
325 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
326
327 Exynos4210fimdWindow window[5]; /* Window-specific registers */
328 uint8_t *ifb; /* Internal frame buffer */
329 bool invalidate; /* Image needs to be redrawn */
330 bool enabled; /* Display controller is enabled */
331 };
332
333 /* Perform byte/halfword/word swap of data according to WINCON */
334 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
335 {
336 int i;
337 uint64_t res;
338 uint64_t x = *data;
339
340 if (swap_ctl & FIMD_WINCON_SWAP_BITS) {
341 res = 0;
342 for (i = 0; i < 64; i++) {
343 if (x & (1ULL << (63 - i))) {
344 res |= (1ULL << i);
345 }
346 }
347 x = res;
348 }
349
350 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) {
351 x = bswap64(x);
352 }
353
354 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) {
355 x = ((x & 0x000000000000FFFFULL) << 48) |
356 ((x & 0x00000000FFFF0000ULL) << 16) |
357 ((x & 0x0000FFFF00000000ULL) >> 16) |
358 ((x & 0xFFFF000000000000ULL) >> 48);
359 }
360
361 if (swap_ctl & FIMD_WINCON_SWAP_WORD) {
362 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
363 ((x & 0xFFFFFFFF00000000ULL) >> 32);
364 }
365
366 *data = x;
367 }
368
369 /* Conversion routines of Pixel data from frame buffer area to internal RGBA
370 * pixel representation.
371 * Every color component internally represented as 8-bit value. If original
372 * data has less than 8 bit for component, data is extended to 8 bit. For
373 * example, if blue component has only two possible values 0 and 1 it will be
374 * extended to 0 and 0xFF */
375
376 /* One bit for alpha representation */
377 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
378 static void N(uint32_t pixel, rgba *p) \
379 { \
380 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
381 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
382 pixel >>= (B); \
383 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
384 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
385 pixel >>= (G); \
386 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
387 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
388 pixel >>= (R); \
389 p->a = (pixel & 0x1); \
390 }
391
392 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)
393 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
394 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)
395 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)
396 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)
397 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)
398
399 /* Alpha component is always zero */
400 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
401 static void N(uint32_t pixel, rgba *p) \
402 { \
403 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
404 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
405 pixel >>= (B); \
406 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
407 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
408 pixel >>= (G); \
409 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
410 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
411 p->a = 0x0; \
412 }
413
414 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)
415 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)
416 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)
417 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)
418
419 /* Alpha component has some meaningful value */
420 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
421 static void N(uint32_t pixel, rgba *p) \
422 { \
423 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
424 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
425 pixel >>= (B); \
426 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
427 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
428 pixel >>= (G); \
429 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
430 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
431 pixel >>= (R); \
432 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
433 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
434 p->a = p->a | (p->a << 8) | (p->a << 16); \
435 }
436
437 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)
438 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)
439
440 /* Lookup table to extent 2-bit color component to 8 bit */
441 static const uint8_t pixel_lutable_2b[4] = {
442 0x0, 0x55, 0xAA, 0xFF
443 };
444 /* Lookup table to extent 3-bit color component to 8 bit */
445 static const uint8_t pixel_lutable_3b[8] = {
446 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
447 };
448 /* Special case for a232 bpp mode */
449 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
450 {
451 p->b = pixel_lutable_2b[(pixel & 0x3)];
452 pixel >>= 2;
453 p->g = pixel_lutable_3b[(pixel & 0x7)];
454 pixel >>= 3;
455 p->r = pixel_lutable_2b[(pixel & 0x3)];
456 pixel >>= 2;
457 p->a = (pixel & 0x1);
458 }
459
460 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
461 * for all three color components */
462 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
463 {
464 uint8_t comm = (pixel >> 15) & 1;
465 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
466 pixel >>= 5;
467 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
468 pixel >>= 5;
469 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
470 p->a = 0x0;
471 }
472
473 /* Put/get pixel to/from internal LCD Controller framebuffer */
474
475 static int put_pixel_ifb(const rgba p, uint8_t *d)
476 {
477 *(uint8_t *)d++ = p.r;
478 *(uint8_t *)d++ = p.g;
479 *(uint8_t *)d++ = p.b;
480 *(uint32_t *)d = p.a;
481 return RGBA_SIZE;
482 }
483
484 static int get_pixel_ifb(const uint8_t *s, rgba *p)
485 {
486 p->r = *(uint8_t *)s++;
487 p->g = *(uint8_t *)s++;
488 p->b = *(uint8_t *)s++;
489 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
490 return RGBA_SIZE;
491 }
492
493 static pixel_to_rgb_func *palette_data_format[8] = {
494 [0] = pixel_565_to_rgb,
495 [1] = pixel_a555_to_rgb,
496 [2] = pixel_666_to_rgb,
497 [3] = pixel_a665_to_rgb,
498 [4] = pixel_a666_to_rgb,
499 [5] = pixel_888_to_rgb,
500 [6] = pixel_a888_to_rgb,
501 [7] = pixel_8888_to_rgb
502 };
503
504 /* Returns Index in palette data formats table for given window number WINDOW */
505 static uint32_t
506 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
507 {
508 uint32_t ret;
509
510 switch (window) {
511 case 0:
512 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L;
513 if (ret != 7) {
514 ret = 6 - ret;
515 }
516 break;
517 case 1:
518 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L;
519 if (ret != 7) {
520 ret = 6 - ret;
521 }
522 break;
523 case 2:
524 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) |
525 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L);
526 break;
527 case 3:
528 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) |
529 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L);
530 break;
531 case 4:
532 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) |
533 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L);
534 break;
535 default:
536 qemu_log_mask(LOG_GUEST_ERROR,
537 "exynos4210.fimd: incorrect window number %d\n", window);
538 ret = 0;
539 break;
540 }
541 return ret;
542 }
543
544 #define FIMD_1_MINUS_COLOR(x) \
545 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
546 (0xFF0000 - ((x) & 0xFF0000)))
547 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
548 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
549
550 /* Multiply three lower bytes of two 32-bit words with each other.
551 * Each byte with values 0-255 is considered as a number with possible values
552 * in a range [0 - 1] */
553 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
554 {
555 uint32_t tmp;
556 uint32_t ret;
557
558 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
559 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
560 0xFF00 : tmp << 8;
561 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
562 0xFF0000 : tmp << 16;
563 return ret;
564 }
565
566 /* For each corresponding bytes of two 32-bit words: (a*b + c*d)
567 * Byte values 0-255 are mapped to a range [0 .. 1] */
568 static inline uint32_t
569 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
570 {
571 uint32_t tmp;
572 uint32_t ret;
573
574 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
575 > 0xFF) ? 0xFF : tmp;
576 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
577 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
578 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
579 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
580 0xFF0000 : tmp << 16;
581 return ret;
582 }
583
584 /* These routines cover all possible sources of window's transparent factor
585 * used in blending equation. Choice of routine is affected by WPALCON
586 * registers, BLENDCON register and window's WINCON register */
587
588 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
589 {
590 return pix_a;
591 }
592
593 static uint32_t
594 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
595 {
596 return EXTEND_LOWER_HALFBYTE(pix_a);
597 }
598
599 static uint32_t
600 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
601 {
602 return EXTEND_UPPER_HALFBYTE(pix_a);
603 }
604
605 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
606 {
607 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
608 }
609
610 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
611 {
612 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a),
613 EXTEND_UPPER_HALFBYTE(w->alpha_val[0]));
614 }
615
616 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
617 {
618 return w->alpha_val[pix_a];
619 }
620
621 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
622 {
623 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]);
624 }
625
626 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
627 {
628 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0];
629 }
630
631 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
632 {
633 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &
634 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]);
635 }
636
637 /* Updates currently active alpha value get function for specified window */
638 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
639 {
640 Exynos4210fimdWindow *w = &s->window[win];
641 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT;
642
643 if (w->wincon & FIMD_WINCON_BLD_PIX) {
644 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) {
645 /* In this case, alpha component contains meaningful value */
646 if (w->wincon & FIMD_WINCON_ALPHA_MUL) {
647 w->get_alpha = alpha_is_8bit ?
648 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
649 } else {
650 w->get_alpha = alpha_is_8bit ?
651 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
652 }
653 } else {
654 if (IS_PALETTIZED_MODE(w) &&
655 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) {
656 /* Alpha component has 8-bit numeric value */
657 w->get_alpha = alpha_is_8bit ?
658 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
659 } else {
660 /* Alpha has only two possible values (AEN) */
661 w->get_alpha = alpha_is_8bit ?
662 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
663 }
664 }
665 } else {
666 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
667 fimd_get_alpha_sel_ext;
668 }
669 }
670
671 /* Blends current window's (w) pixel (foreground pixel *ret) with background
672 * window (w_blend) pixel p_bg according to formula:
673 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
674 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
675 */
676 static void
677 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
678 {
679 rgba p_fg = *ret;
680 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
681 (p_bg.b & 0xFF);
682 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
683 (p_fg.b & 0xFF);
684 uint32_t alpha_fg = p_fg.a;
685 int i;
686 /* It is possible that blending equation parameters a and b do not
687 * depend on window BLENEQ register. Account for this with first_coef */
688 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
689 uint32_t first_coef = A_COEF;
690 uint32_t blend_param[COEF_NUM];
691
692 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) {
693 uint32_t colorkey = (w->keycon[1] &
694 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY;
695
696 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) &&
697 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
698 /* Foreground pixel is displayed */
699 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
700 alpha_fg = w->keyalpha;
701 blend_param[A_COEF] = alpha_fg;
702 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
703 } else {
704 alpha_fg = 0;
705 blend_param[A_COEF] = 0xFFFFFF;
706 blend_param[B_COEF] = 0x0;
707 }
708 first_coef = P_COEF;
709 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 &&
710 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
711 /* Background pixel is displayed */
712 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
713 alpha_fg = w->keyalpha;
714 blend_param[A_COEF] = alpha_fg;
715 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
716 } else {
717 alpha_fg = 0;
718 blend_param[A_COEF] = 0x0;
719 blend_param[B_COEF] = 0xFFFFFF;
720 }
721 first_coef = P_COEF;
722 }
723 }
724
725 for (i = first_coef; i < COEF_NUM; i++) {
726 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) {
727 case 0:
728 blend_param[i] = 0;
729 break;
730 case 1:
731 blend_param[i] = 0xFFFFFF;
732 break;
733 case 2:
734 blend_param[i] = alpha_fg;
735 break;
736 case 3:
737 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg);
738 break;
739 case 4:
740 blend_param[i] = p_bg.a;
741 break;
742 case 5:
743 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a);
744 break;
745 case 6:
746 blend_param[i] = w->alpha_val[0];
747 break;
748 case 10:
749 blend_param[i] = fg_color;
750 break;
751 case 11:
752 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color);
753 break;
754 case 12:
755 blend_param[i] = bg_color;
756 break;
757 case 13:
758 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color);
759 break;
760 default:
761 qemu_log_mask(LOG_GUEST_ERROR,
762 "exynos4210.fimd: blend equation coef illegal value\n");
763 blend_param[i] = 0;
764 break;
765 }
766 }
767
768 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
769 fg_color, blend_param[A_COEF]);
770 ret->b = fg_color & 0xFF;
771 fg_color >>= 8;
772 ret->g = fg_color & 0xFF;
773 fg_color >>= 8;
774 ret->r = fg_color & 0xFF;
775 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
776 p_bg.a, blend_param[Q_COEF]);
777 }
778
779 /* These routines read data from video frame buffer in system RAM, convert
780 * this data to display controller internal representation, if necessary,
781 * perform pixel blending with data, currently presented in internal buffer.
782 * Result is stored in display controller internal frame buffer. */
783
784 /* Draw line with index in palette table in RAM frame buffer data */
785 #define DEF_DRAW_LINE_PALETTE(N) \
786 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
787 uint8_t *dst, uint32_t width, \
788 bool blend) \
789 { \
790 uint8_t *ifb = dst; \
791 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
792 uint64_t data; \
793 rgba p, p_old; \
794 int i; \
795 do { \
796 memcpy(&data, src, sizeof(data)); \
797 src += 8; \
798 fimd_swap_data(swap, &data); \
799 for (i = (64 / (N) - 1); i >= 0; i--) { \
800 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
801 ((1ULL << (N)) - 1)], &p); \
802 p.a = w->get_alpha(w, p.a); \
803 if (blend) { \
804 ifb += get_pixel_ifb(ifb, &p_old); \
805 exynos4210_fimd_blend_pixel(w, p_old, &p); \
806 } \
807 dst += put_pixel_ifb(p, dst); \
808 } \
809 width -= (64 / (N)); \
810 } while (width > 0); \
811 }
812
813 /* Draw line with direct color value in RAM frame buffer data */
814 #define DEF_DRAW_LINE_NOPALETTE(N) \
815 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
816 uint8_t *dst, uint32_t width, bool blend) \
817 { \
818 uint8_t *ifb = dst; \
819 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
820 uint64_t data; \
821 rgba p, p_old; \
822 int i; \
823 do { \
824 memcpy(&data, src, sizeof(data)); \
825 src += 8; \
826 fimd_swap_data(swap, &data); \
827 for (i = (64 / (N) - 1); i >= 0; i--) { \
828 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
829 p.a = w->get_alpha(w, p.a); \
830 if (blend) { \
831 ifb += get_pixel_ifb(ifb, &p_old); \
832 exynos4210_fimd_blend_pixel(w, p_old, &p); \
833 } \
834 dst += put_pixel_ifb(p, dst); \
835 } \
836 width -= (64 / (N)); \
837 } while (width > 0); \
838 }
839
840 DEF_DRAW_LINE_PALETTE(1)
841 DEF_DRAW_LINE_PALETTE(2)
842 DEF_DRAW_LINE_PALETTE(4)
843 DEF_DRAW_LINE_PALETTE(8)
844 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */
845 DEF_DRAW_LINE_NOPALETTE(16)
846 DEF_DRAW_LINE_NOPALETTE(32)
847
848 /* Special draw line routine for window color map case */
849 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
850 uint8_t *dst, uint32_t width, bool blend)
851 {
852 rgba p, p_old;
853 uint8_t *ifb = dst;
854 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK;
855
856 do {
857 pixel_888_to_rgb(map_color, &p);
858 p.a = w->get_alpha(w, p.a);
859 if (blend) {
860 ifb += get_pixel_ifb(ifb, &p_old);
861 exynos4210_fimd_blend_pixel(w, p_old, &p);
862 }
863 dst += put_pixel_ifb(p, dst);
864 } while (--width);
865 }
866
867 /* Write RGB to QEMU's GraphicConsole framebuffer */
868 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
869 {
870 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
871 *(uint32_t *)d = pixel;
872 return 4;
873 }
874
875 /* Routine to copy a line from internal frame buffer to QEMU display */
876 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
877 {
878 rgba p;
879
880 do {
881 src += get_pixel_ifb(src, &p);
882 dst += put_to_qemufb_pixel32(p, dst);
883 } while (--width);
884 }
885
886 /* Parse BPPMODE_F = WINCON1[5:2] bits */
887 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
888 {
889 Exynos4210fimdWindow *w = &s->window[win];
890
891 if (w->winmap & FIMD_WINMAP_EN) {
892 w->draw_line = draw_line_mapcolor;
893 return;
894 }
895
896 switch (WIN_BPP_MODE(w)) {
897 case 0:
898 w->draw_line = draw_line_palette_1;
899 w->pixel_to_rgb =
900 palette_data_format[exynos4210_fimd_palette_format(s, win)];
901 break;
902 case 1:
903 w->draw_line = draw_line_palette_2;
904 w->pixel_to_rgb =
905 palette_data_format[exynos4210_fimd_palette_format(s, win)];
906 break;
907 case 2:
908 w->draw_line = draw_line_palette_4;
909 w->pixel_to_rgb =
910 palette_data_format[exynos4210_fimd_palette_format(s, win)];
911 break;
912 case 3:
913 w->draw_line = draw_line_palette_8;
914 w->pixel_to_rgb =
915 palette_data_format[exynos4210_fimd_palette_format(s, win)];
916 break;
917 case 4:
918 w->draw_line = draw_line_8;
919 w->pixel_to_rgb = pixel_a232_to_rgb;
920 break;
921 case 5:
922 w->draw_line = draw_line_16;
923 w->pixel_to_rgb = pixel_565_to_rgb;
924 break;
925 case 6:
926 w->draw_line = draw_line_16;
927 w->pixel_to_rgb = pixel_a555_to_rgb;
928 break;
929 case 7:
930 w->draw_line = draw_line_16;
931 w->pixel_to_rgb = pixel_1555_to_rgb;
932 break;
933 case 8:
934 w->draw_line = draw_line_32;
935 w->pixel_to_rgb = pixel_666_to_rgb;
936 break;
937 case 9:
938 w->draw_line = draw_line_32;
939 w->pixel_to_rgb = pixel_a665_to_rgb;
940 break;
941 case 10:
942 w->draw_line = draw_line_32;
943 w->pixel_to_rgb = pixel_a666_to_rgb;
944 break;
945 case 11:
946 w->draw_line = draw_line_32;
947 w->pixel_to_rgb = pixel_888_to_rgb;
948 break;
949 case 12:
950 w->draw_line = draw_line_32;
951 w->pixel_to_rgb = pixel_a887_to_rgb;
952 break;
953 case 13:
954 w->draw_line = draw_line_32;
955 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
956 FIMD_WINCON_ALPHA_SEL)) {
957 w->pixel_to_rgb = pixel_8888_to_rgb;
958 } else {
959 w->pixel_to_rgb = pixel_a888_to_rgb;
960 }
961 break;
962 case 14:
963 w->draw_line = draw_line_16;
964 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
965 FIMD_WINCON_ALPHA_SEL)) {
966 w->pixel_to_rgb = pixel_4444_to_rgb;
967 } else {
968 w->pixel_to_rgb = pixel_a444_to_rgb;
969 }
970 break;
971 case 15:
972 w->draw_line = draw_line_16;
973 w->pixel_to_rgb = pixel_555_to_rgb;
974 break;
975 }
976 }
977
978 #if EXYNOS4210_FIMD_MODE_TRACE > 0
979 static const char *exynos4210_fimd_get_bppmode(int mode_code)
980 {
981 switch (mode_code) {
982 case 0:
983 return "1 bpp";
984 case 1:
985 return "2 bpp";
986 case 2:
987 return "4 bpp";
988 case 3:
989 return "8 bpp (palettized)";
990 case 4:
991 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
992 case 5:
993 return "16 bpp (non-palettized, R:5-G:6-B:5)";
994 case 6:
995 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
996 case 7:
997 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
998 case 8:
999 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1000 case 9:
1001 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1002 case 10:
1003 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1004 case 11:
1005 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1006 case 12:
1007 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1008 case 13:
1009 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1010 case 14:
1011 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1012 case 15:
1013 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1014 default:
1015 return "Non-existing bpp mode";
1016 }
1017 }
1018
1019 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1020 int win_num, uint32_t val)
1021 {
1022 Exynos4210fimdWindow *w = &s->window[win_num];
1023
1024 if (w->winmap & FIMD_WINMAP_EN) {
1025 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1026 win_num, w->winmap & 0xFFFFFF);
1027 return;
1028 }
1029
1030 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1031 return;
1032 }
1033 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1034 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1035 }
1036 #else
1037 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1038 int win_num, uint32_t val)
1039 {
1040
1041 }
1042 #endif
1043
1044 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1045 {
1046 switch (w->wincon & FIMD_WINCON_BUFSTATUS) {
1047 case FIMD_WINCON_BUF0_STAT:
1048 return 0;
1049 case FIMD_WINCON_BUF1_STAT:
1050 return 1;
1051 case FIMD_WINCON_BUF2_STAT:
1052 return 2;
1053 default:
1054 qemu_log_mask(LOG_GUEST_ERROR, "FIMD: Non-existent buffer index\n");
1055 return 0;
1056 }
1057 }
1058
1059 static void exynos4210_fimd_invalidate(void *opaque)
1060 {
1061 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1062 s->invalidate = true;
1063 }
1064
1065 /* Updates specified window's MemorySection based on values of WINCON,
1066 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1067 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1068 {
1069 Exynos4210fimdWindow *w = &s->window[win];
1070 hwaddr fb_start_addr, fb_mapped_len;
1071
1072 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
1073 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
1074 return;
1075 }
1076
1077 if (w->host_fb_addr) {
1078 physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1079 w->host_fb_addr = NULL;
1080 w->fb_len = 0;
1081 }
1082
1083 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1084 /* Total number of bytes of virtual screen used by current window */
1085 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1086 (w->rightbot_y - w->lefttop_y + 1);
1087
1088 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1089 * does not support hot-unplug.
1090 */
1091 if (w->mem_section.mr) {
1092 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA);
1093 memory_region_unref(w->mem_section.mr);
1094 w->mem_section.mr = NULL;
1095 }
1096
1097 if (w->fb_len == 0) {
1098 qemu_log_mask(LOG_GUEST_ERROR,
1099 "FIMD: Guest config means framebuffer is zero length\n");
1100 goto error_return;
1101 }
1102
1103 w->mem_section = memory_region_find(s->fbmem, fb_start_addr, w->fb_len);
1104 assert(w->mem_section.mr);
1105 assert(w->mem_section.offset_within_address_space == fb_start_addr);
1106 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
1107 win, fb_start_addr, w->fb_len);
1108
1109 if (int128_get64(w->mem_section.size) != w->fb_len ||
1110 !memory_region_is_ram(w->mem_section.mr)) {
1111 qemu_log_mask(LOG_GUEST_ERROR,
1112 "FIMD: Failed to find window %u framebuffer region\n",
1113 win);
1114 goto error_return;
1115 }
1116
1117 w->host_fb_addr = physical_memory_map(fb_start_addr, &fb_mapped_len,
1118 false);
1119 if (!w->host_fb_addr) {
1120 qemu_log_mask(LOG_GUEST_ERROR,
1121 "FIMD: Failed to map window %u framebuffer\n", win);
1122 goto error_return;
1123 }
1124
1125 if (fb_mapped_len != w->fb_len) {
1126 qemu_log_mask(LOG_GUEST_ERROR,
1127 "FIMD: Window %u mapped framebuffer length is less than "
1128 "expected\n", win);
1129 physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1130 goto error_return;
1131 }
1132 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA);
1133 exynos4210_fimd_invalidate(s);
1134 return;
1135
1136 error_return:
1137 memory_region_unref(w->mem_section.mr);
1138 w->mem_section.mr = NULL;
1139 w->mem_section.size = int128_zero();
1140 w->host_fb_addr = NULL;
1141 w->fb_len = 0;
1142 }
1143
1144 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled)
1145 {
1146 if (enabled && !s->enabled) {
1147 unsigned w;
1148 s->enabled = true;
1149 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1150 fimd_update_memory_section(s, w);
1151 }
1152 }
1153 s->enabled = enabled;
1154 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled");
1155 }
1156
1157 static inline uint32_t unpack_upper_4(uint32_t x)
1158 {
1159 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1160 }
1161
1162 static inline uint32_t pack_upper_4(uint32_t x)
1163 {
1164 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1165 ((x & 0xF0) >> 4)) & 0xFFF;
1166 }
1167
1168 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1169 {
1170 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) {
1171 qemu_irq_lower(s->irq[0]);
1172 qemu_irq_lower(s->irq[1]);
1173 qemu_irq_lower(s->irq[2]);
1174 return;
1175 }
1176 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) &&
1177 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) {
1178 qemu_irq_raise(s->irq[0]);
1179 } else {
1180 qemu_irq_lower(s->irq[0]);
1181 }
1182 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) &&
1183 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) {
1184 qemu_irq_raise(s->irq[1]);
1185 } else {
1186 qemu_irq_lower(s->irq[1]);
1187 }
1188 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) &&
1189 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) {
1190 qemu_irq_raise(s->irq[2]);
1191 } else {
1192 qemu_irq_lower(s->irq[2]);
1193 }
1194 }
1195
1196 static uint32_t exynos4210_fimd_global_width(Exynos4210fimdState *s)
1197 {
1198 return ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
1199 FIMD_VIDTCON2_SIZE_MASK) + 1;
1200 }
1201
1202 static uint32_t exynos4210_fimd_global_height(Exynos4210fimdState *s)
1203 {
1204 return ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
1205 FIMD_VIDTCON2_SIZE_MASK) + 1;
1206 }
1207
1208 static void exynos4210_update_resolution(Exynos4210fimdState *s)
1209 {
1210 DisplaySurface *surface = qemu_console_surface(s->console);
1211
1212 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1213 uint32_t width = exynos4210_fimd_global_width(s);
1214 uint32_t height = exynos4210_fimd_global_height(s);
1215
1216 if (s->ifb == NULL || surface_width(surface) != width ||
1217 surface_height(surface) != height) {
1218 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
1219 surface_width(surface), surface_height(surface), width, height);
1220 qemu_console_resize(s->console, width, height);
1221 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
1222 memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
1223 exynos4210_fimd_invalidate(s);
1224 }
1225 }
1226
1227 static bool exynos4210_fimd_update(void *opaque)
1228 {
1229 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1230 DisplaySurface *surface;
1231 Exynos4210fimdWindow *w;
1232 DirtyBitmapSnapshot *snap;
1233 int i, line;
1234 hwaddr fb_line_addr, inc_size;
1235 int scrn_height;
1236 int first_line = -1, last_line = -1, scrn_width;
1237 bool blend = false;
1238 uint8_t *host_fb_addr;
1239 bool is_dirty = false;
1240 uint32_t global_width, global_height;
1241 uint32_t window_width;
1242
1243 if (!s || !s->console || !s->enabled ||
1244 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
1245 return true;
1246 }
1247
1248 global_width = exynos4210_fimd_global_width(s);
1249 global_height = exynos4210_fimd_global_height(s);
1250 exynos4210_update_resolution(s);
1251 surface = qemu_console_surface(s->console);
1252
1253 for (i = 0; i < NUM_OF_WINDOWS; i++) {
1254 w = &s->window[i];
1255 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) {
1256 uint32_t rightbot_x, rightbot_y;
1257
1258 if (w->lefttop_x >= global_width ||
1259 w->lefttop_y >= global_height) {
1260 /* Guest has put the window entirely offscreen: ignore */
1261 continue;
1262 }
1263
1264 /* Clamp right corner coords to be within the screen */
1265 rightbot_x = MIN(w->rightbot_x, global_width - 1);
1266 rightbot_y = MIN(w->rightbot_y, global_height - 1);
1267 scrn_height = rightbot_y - w->lefttop_y + 1;
1268 scrn_width = w->virtpage_width;
1269 /* Number of bytes to actually draw */
1270 window_width = rightbot_x - w->lefttop_x + 1;
1271 /* Total width of virtual screen page in bytes */
1272 inc_size = scrn_width + w->virtpage_offsize;
1273 host_fb_addr = w->host_fb_addr;
1274 fb_line_addr = w->mem_section.offset_within_region;
1275 snap = memory_region_snapshot_and_clear_dirty(w->mem_section.mr,
1276 fb_line_addr, inc_size * scrn_height, DIRTY_MEMORY_VGA);
1277
1278 for (line = 0; line < scrn_height; line++) {
1279 is_dirty = memory_region_snapshot_get_dirty(w->mem_section.mr,
1280 snap, fb_line_addr, scrn_width);
1281
1282 if (s->invalidate || is_dirty) {
1283 if (first_line == -1) {
1284 first_line = line;
1285 }
1286 last_line = line;
1287 w->draw_line(w, host_fb_addr, s->ifb +
1288 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) *
1289 global_width * RGBA_SIZE,
1290 window_width, blend);
1291 }
1292 host_fb_addr += inc_size;
1293 fb_line_addr += inc_size;
1294 }
1295 g_free(snap);
1296 blend = true;
1297 }
1298 }
1299
1300 /* Copy resulting image to QEMU_CONSOLE. */
1301 if (first_line >= 0) {
1302 uint8_t *d;
1303 int bpp;
1304
1305 bpp = surface_bits_per_pixel(surface);
1306 assert(bpp == 32);
1307 bpp = (bpp + 1) >> 3;
1308 d = surface_data(surface);
1309 for (line = first_line; line <= last_line; line++) {
1310 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1311 RGBA_SIZE, d + global_width * line * bpp);
1312 }
1313 qemu_console_update_full(s->console);
1314 }
1315 s->invalidate = false;
1316 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND;
1317 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) {
1318 exynos4210_fimd_enable(s, false);
1319 }
1320 exynos4210_fimd_update_irq(s);
1321
1322 return true;
1323 }
1324
1325 static void exynos4210_fimd_reset(DeviceState *d)
1326 {
1327 Exynos4210fimdState *s = EXYNOS4210_FIMD(d);
1328 unsigned w;
1329
1330 DPRINT_TRACE("Display controller reset\n");
1331 /* Set all display controller registers to 0 */
1332 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1333 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1334 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1335 s->window[w].blendeq = 0xC2;
1336 exynos4210_fimd_update_win_bppmode(s, w);
1337 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1338 fimd_update_get_alpha(s, w);
1339 }
1340
1341 g_free(s->ifb);
1342 s->ifb = NULL;
1343
1344 exynos4210_fimd_invalidate(s);
1345 exynos4210_fimd_enable(s, false);
1346 /* Some registers have non-zero initial values */
1347 s->winchmap = 0x7D517D51;
1348 s->colorgaincon = 0x10040100;
1349 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1350 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1351 s->hueoffset = 0x01800080;
1352 }
1353
1354 static void exynos4210_fimd_write(void *opaque, hwaddr offset,
1355 uint64_t val, unsigned size)
1356 {
1357 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1358 unsigned w, i;
1359 uint32_t old_value;
1360
1361 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,
1362 (long long unsigned int)val, (long long unsigned int)val);
1363
1364 switch (offset) {
1365 case FIMD_VIDCON0:
1366 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) {
1367 exynos4210_fimd_enable(s, true);
1368 } else {
1369 if ((val & FIMD_VIDCON0_ENVID) == 0) {
1370 exynos4210_fimd_enable(s, false);
1371 }
1372 }
1373 s->vidcon[0] = val;
1374 break;
1375 case FIMD_VIDCON1:
1376 /* Leave read-only bits as is */
1377 val = (val & (~FIMD_VIDCON1_ROMASK)) |
1378 (s->vidcon[1] & FIMD_VIDCON1_ROMASK);
1379 s->vidcon[1] = val;
1380 break;
1381 case FIMD_VIDCON2 ... FIMD_VIDCON3:
1382 s->vidcon[(offset) >> 2] = val;
1383 break;
1384 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1385 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val;
1386 break;
1387 case FIMD_WINCON_START ... FIMD_WINCON_END:
1388 w = (offset - FIMD_WINCON_START) >> 2;
1389 /* Window's current buffer ID */
1390 i = fimd_get_buffer_id(&s->window[w]);
1391 old_value = s->window[w].wincon;
1392 val = (val & ~FIMD_WINCON_ROMASK) |
1393 (s->window[w].wincon & FIMD_WINCON_ROMASK);
1394 if (w == 0) {
1395 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1396 val &= ~FIMD_WINCON_ALPHA_MUL;
1397 }
1398 exynos4210_fimd_trace_bppmode(s, w, val);
1399 switch (val & FIMD_WINCON_BUFSELECT) {
1400 case FIMD_WINCON_BUF0_SEL:
1401 val &= ~FIMD_WINCON_BUFSTATUS;
1402 break;
1403 case FIMD_WINCON_BUF1_SEL:
1404 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L;
1405 break;
1406 case FIMD_WINCON_BUF2_SEL:
1407 if (val & FIMD_WINCON_BUFMODE) {
1408 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H;
1409 }
1410 break;
1411 default:
1412 break;
1413 }
1414 s->window[w].wincon = val;
1415 exynos4210_fimd_update_win_bppmode(s, w);
1416 fimd_update_get_alpha(s, w);
1417 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1418 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon &
1419 FIMD_WINCON_ENWIN))) {
1420 fimd_update_memory_section(s, w);
1421 }
1422 break;
1423 case FIMD_SHADOWCON:
1424 old_value = s->shadowcon;
1425 s->shadowcon = val;
1426 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1427 if (FIMD_WINDOW_PROTECTED(old_value, w) &&
1428 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) {
1429 fimd_update_memory_section(s, w);
1430 }
1431 }
1432 break;
1433 case FIMD_WINCHMAP:
1434 s->winchmap = val;
1435 break;
1436 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1437 w = (offset - FIMD_VIDOSD_START) >> 4;
1438 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1439 switch (i) {
1440 case 0:
1441 old_value = s->window[w].lefttop_y;
1442 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1443 FIMD_VIDOSD_COORD_MASK;
1444 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1445 FIMD_VIDOSD_COORD_MASK;
1446 if (s->window[w].lefttop_y != old_value) {
1447 fimd_update_memory_section(s, w);
1448 }
1449 break;
1450 case 1:
1451 old_value = s->window[w].rightbot_y;
1452 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1453 FIMD_VIDOSD_COORD_MASK;
1454 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1455 FIMD_VIDOSD_COORD_MASK;
1456 if (s->window[w].rightbot_y != old_value) {
1457 fimd_update_memory_section(s, w);
1458 }
1459 break;
1460 case 2:
1461 if (w == 0) {
1462 s->window[w].osdsize = val;
1463 } else {
1464 s->window[w].alpha_val[0] =
1465 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
1466 FIMD_VIDOSD_AEN0_SHIFT) |
1467 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
1468 s->window[w].alpha_val[1] =
1469 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
1470 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
1471 }
1472 break;
1473 case 3:
1474 if (w != 1 && w != 2) {
1475 qemu_log_mask(LOG_GUEST_ERROR,
1476 "FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n",
1477 offset);
1478 return;
1479 }
1480 s->window[w].osdsize = val;
1481 break;
1482 }
1483 break;
1484 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1485 w = (offset - FIMD_VIDWADD0_START) >> 3;
1486 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1487 if (i == fimd_get_buffer_id(&s->window[w]) &&
1488 s->window[w].buf_start[i] != val) {
1489 s->window[w].buf_start[i] = val;
1490 fimd_update_memory_section(s, w);
1491 break;
1492 }
1493 s->window[w].buf_start[i] = val;
1494 break;
1495 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1496 w = (offset - FIMD_VIDWADD1_START) >> 3;
1497 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1498 s->window[w].buf_end[i] = val;
1499 break;
1500 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1501 w = (offset - FIMD_VIDWADD2_START) >> 2;
1502 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) ||
1503 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) !=
1504 s->window[w].virtpage_offsize)) {
1505 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
1506 s->window[w].virtpage_offsize =
1507 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
1508 fimd_update_memory_section(s, w);
1509 }
1510 break;
1511 case FIMD_VIDINTCON0:
1512 s->vidintcon[0] = val;
1513 break;
1514 case FIMD_VIDINTCON1:
1515 s->vidintcon[1] &= ~(val & 7);
1516 exynos4210_fimd_update_irq(s);
1517 break;
1518 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1519 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1520 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1521 s->window[w].keycon[i] = val;
1522 break;
1523 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1524 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1525 s->window[w].keyalpha = val;
1526 break;
1527 case FIMD_DITHMODE:
1528 s->dithmode = val;
1529 break;
1530 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1531 w = (offset - FIMD_WINMAP_START) >> 2;
1532 old_value = s->window[w].winmap;
1533 s->window[w].winmap = val;
1534 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) {
1535 exynos4210_fimd_invalidate(s);
1536 exynos4210_fimd_update_win_bppmode(s, w);
1537 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1538 exynos4210_fimd_update(s);
1539 }
1540 break;
1541 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1542 i = (offset - FIMD_WPALCON_HIGH) >> 2;
1543 s->wpalcon[i] = val;
1544 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) {
1545 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1546 exynos4210_fimd_update_win_bppmode(s, w);
1547 fimd_update_get_alpha(s, w);
1548 }
1549 }
1550 break;
1551 case FIMD_TRIGCON:
1552 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK);
1553 s->trigcon = val;
1554 break;
1555 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1556 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val;
1557 break;
1558 case FIMD_COLORGAINCON:
1559 s->colorgaincon = val;
1560 break;
1561 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1562 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val;
1563 break;
1564 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1565 i = (offset - FIMD_SIFCCON0) >> 2;
1566 if (i != 2) {
1567 s->sifccon[i] = val;
1568 }
1569 break;
1570 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1571 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1572 s->huecoef_cr[i] = val;
1573 break;
1574 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1575 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1576 s->huecoef_cb[i] = val;
1577 break;
1578 case FIMD_HUEOFFSET:
1579 s->hueoffset = val;
1580 break;
1581 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1582 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1583 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1584 if (w == 0) {
1585 s->window[w].alpha_val[i] = val;
1586 } else {
1587 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) |
1588 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER);
1589 }
1590 break;
1591 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1592 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val;
1593 break;
1594 case FIMD_BLENDCON:
1595 old_value = s->blendcon;
1596 s->blendcon = val;
1597 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) {
1598 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1599 fimd_update_get_alpha(s, w);
1600 }
1601 }
1602 break;
1603 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1604 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val;
1605 break;
1606 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1607 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val;
1608 break;
1609 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1610 if (offset & 0x0004) {
1611 qemu_log_mask(LOG_GUEST_ERROR,
1612 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1613 offset);
1614 break;
1615 }
1616 w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
1617 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1618 s->window[w].buf_start[2] != val) {
1619 s->window[w].buf_start[2] = val;
1620 fimd_update_memory_section(s, w);
1621 break;
1622 }
1623 s->window[w].buf_start[2] = val;
1624 break;
1625 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1626 if (offset & 0x0004) {
1627 qemu_log_mask(LOG_GUEST_ERROR,
1628 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1629 offset);
1630 break;
1631 }
1632 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
1633 break;
1634 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1635 if (offset & 0x0004) {
1636 qemu_log_mask(LOG_GUEST_ERROR,
1637 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1638 offset);
1639 break;
1640 }
1641 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
1642 break;
1643 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1644 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val;
1645 break;
1646 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1647 w = (offset - FIMD_PAL_MEM_START) >> 10;
1648 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1649 s->window[w].palette[i] = val;
1650 break;
1651 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1652 /* Palette memory aliases for windows 0 and 1 */
1653 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1654 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1655 s->window[w].palette[i] = val;
1656 break;
1657 default:
1658 qemu_log_mask(LOG_GUEST_ERROR,
1659 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset);
1660 break;
1661 }
1662 }
1663
1664 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
1665 unsigned size)
1666 {
1667 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1668 int w, i;
1669 uint32_t ret = 0;
1670
1671 DPRINT_L2("read offset 0x%08x\n", offset);
1672
1673 switch (offset) {
1674 case FIMD_VIDCON0 ... FIMD_VIDCON3:
1675 return s->vidcon[(offset - FIMD_VIDCON0) >> 2];
1676 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1677 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2];
1678 case FIMD_WINCON_START ... FIMD_WINCON_END:
1679 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon;
1680 case FIMD_SHADOWCON:
1681 return s->shadowcon;
1682 case FIMD_WINCHMAP:
1683 return s->winchmap;
1684 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1685 w = (offset - FIMD_VIDOSD_START) >> 4;
1686 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1687 switch (i) {
1688 case 0:
1689 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) <<
1690 FIMD_VIDOSD_HOR_SHIFT) |
1691 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK);
1692 break;
1693 case 1:
1694 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) <<
1695 FIMD_VIDOSD_HOR_SHIFT) |
1696 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK);
1697 break;
1698 case 2:
1699 if (w == 0) {
1700 ret = s->window[w].osdsize;
1701 } else {
1702 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1703 FIMD_VIDOSD_AEN0_SHIFT) |
1704 pack_upper_4(s->window[w].alpha_val[1]);
1705 }
1706 break;
1707 case 3:
1708 if (w != 1 && w != 2) {
1709 qemu_log_mask(LOG_GUEST_ERROR,
1710 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n",
1711 offset);
1712 return 0xBAADBAAD;
1713 }
1714 ret = s->window[w].osdsize;
1715 break;
1716 }
1717 return ret;
1718 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1719 w = (offset - FIMD_VIDWADD0_START) >> 3;
1720 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1721 return s->window[w].buf_start[i];
1722 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1723 w = (offset - FIMD_VIDWADD1_START) >> 3;
1724 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1725 return s->window[w].buf_end[i];
1726 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1727 w = (offset - FIMD_VIDWADD2_START) >> 2;
1728 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1729 FIMD_VIDWADD2_OFFSIZE_SHIFT);
1730 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1:
1731 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2];
1732 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1733 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1734 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1735 return s->window[w].keycon[i];
1736 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1737 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1738 return s->window[w].keyalpha;
1739 case FIMD_DITHMODE:
1740 return s->dithmode;
1741 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1742 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap;
1743 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1744 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2];
1745 case FIMD_TRIGCON:
1746 return s->trigcon;
1747 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1748 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2];
1749 case FIMD_COLORGAINCON:
1750 return s->colorgaincon;
1751 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1752 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2];
1753 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1754 i = (offset - FIMD_SIFCCON0) >> 2;
1755 return s->sifccon[i];
1756 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1757 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1758 return s->huecoef_cr[i];
1759 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1760 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1761 return s->huecoef_cb[i];
1762 case FIMD_HUEOFFSET:
1763 return s->hueoffset;
1764 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1765 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1766 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1767 return s->window[w].alpha_val[i] &
1768 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER);
1769 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1770 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq;
1771 case FIMD_BLENDCON:
1772 return s->blendcon;
1773 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1774 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon;
1775 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1776 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2];
1777 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1778 if (offset & 0x0004) {
1779 break;
1780 }
1781 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2];
1782 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1783 if (offset & 0x0004) {
1784 break;
1785 }
1786 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start;
1787 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1788 if (offset & 0x0004) {
1789 break;
1790 }
1791 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end;
1792 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1793 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size;
1794 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1795 w = (offset - FIMD_PAL_MEM_START) >> 10;
1796 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1797 return s->window[w].palette[i];
1798 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1799 /* Palette aliases for win 0,1 */
1800 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1801 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1802 return s->window[w].palette[i];
1803 }
1804
1805 qemu_log_mask(LOG_GUEST_ERROR,
1806 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset);
1807 return 0xBAADBAAD;
1808 }
1809
1810 static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1811 .read = exynos4210_fimd_read,
1812 .write = exynos4210_fimd_write,
1813 .valid = {
1814 .min_access_size = 4,
1815 .max_access_size = 4,
1816 .unaligned = false
1817 },
1818 .endianness = DEVICE_NATIVE_ENDIAN,
1819 };
1820
1821 static int exynos4210_fimd_load(void *opaque, int version_id)
1822 {
1823 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1824 int w;
1825
1826 if (version_id != 1) {
1827 return -EINVAL;
1828 }
1829
1830 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1831 exynos4210_fimd_update_win_bppmode(s, w);
1832 fimd_update_get_alpha(s, w);
1833 fimd_update_memory_section(s, w);
1834 }
1835
1836 /* Redraw the whole screen */
1837 exynos4210_update_resolution(s);
1838 exynos4210_fimd_invalidate(s);
1839 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) ==
1840 FIMD_VIDCON0_ENVID_MASK);
1841 return 0;
1842 }
1843
1844 static const VMStateDescription exynos4210_fimd_window_vmstate = {
1845 .name = "exynos4210.fimd_window",
1846 .version_id = 1,
1847 .minimum_version_id = 1,
1848 .fields = (const VMStateField[]) {
1849 VMSTATE_UINT32(wincon, Exynos4210fimdWindow),
1850 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3),
1851 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3),
1852 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2),
1853 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow),
1854 VMSTATE_UINT32(winmap, Exynos4210fimdWindow),
1855 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow),
1856 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow),
1857 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256),
1858 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow),
1859 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow),
1860 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow),
1861 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow),
1862 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow),
1863 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow),
1864 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow),
1865 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow),
1866 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2),
1867 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow),
1868 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow),
1869 VMSTATE_END_OF_LIST()
1870 }
1871 };
1872
1873 static const VMStateDescription exynos4210_fimd_vmstate = {
1874 .name = "exynos4210.fimd",
1875 .version_id = 1,
1876 .minimum_version_id = 1,
1877 .post_load = exynos4210_fimd_load,
1878 .fields = (const VMStateField[]) {
1879 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),
1880 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4),
1881 VMSTATE_UINT32(shadowcon, Exynos4210fimdState),
1882 VMSTATE_UINT32(winchmap, Exynos4210fimdState),
1883 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2),
1884 VMSTATE_UINT32(dithmode, Exynos4210fimdState),
1885 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2),
1886 VMSTATE_UINT32(trigcon, Exynos4210fimdState),
1887 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4),
1888 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState),
1889 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2),
1890 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3),
1891 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4),
1892 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4),
1893 VMSTATE_UINT32(hueoffset, Exynos4210fimdState),
1894 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12),
1895 VMSTATE_UINT32(blendcon, Exynos4210fimdState),
1896 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,
1897 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow),
1898 VMSTATE_END_OF_LIST()
1899 }
1900 };
1901
1902 static const GraphicHwOps exynos4210_fimd_ops = {
1903 .invalidate = exynos4210_fimd_invalidate,
1904 .gfx_update = exynos4210_fimd_update,
1905 };
1906
1907 static const Property exynos4210_fimd_properties[] = {
1908 DEFINE_PROP_LINK("framebuffer-memory", Exynos4210fimdState, fbmem,
1909 TYPE_MEMORY_REGION, MemoryRegion *),
1910 };
1911
1912 static void exynos4210_fimd_init(Object *obj)
1913 {
1914 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
1915 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1916
1917 s->ifb = NULL;
1918
1919 sysbus_init_irq(dev, &s->irq[0]);
1920 sysbus_init_irq(dev, &s->irq[1]);
1921 sysbus_init_irq(dev, &s->irq[2]);
1922
1923 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s,
1924 "exynos4210.fimd", FIMD_REGS_SIZE);
1925 sysbus_init_mmio(dev, &s->iomem);
1926 }
1927
1928 static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
1929 {
1930 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
1931
1932 if (!s->fbmem) {
1933 error_setg(errp, "'framebuffer-memory' property was not set");
1934 return;
1935 }
1936
1937 s->console = qemu_graphic_console_create(dev, 0, &exynos4210_fimd_ops, s);
1938 }
1939
1940 static void exynos4210_fimd_class_init(ObjectClass *klass, const void *data)
1941 {
1942 DeviceClass *dc = DEVICE_CLASS(klass);
1943
1944 dc->vmsd = &exynos4210_fimd_vmstate;
1945 device_class_set_legacy_reset(dc, exynos4210_fimd_reset);
1946 dc->realize = exynos4210_fimd_realize;
1947 device_class_set_props(dc, exynos4210_fimd_properties);
1948 }
1949
1950 static const TypeInfo exynos4210_fimd_info = {
1951 .name = TYPE_EXYNOS4210_FIMD,
1952 .parent = TYPE_SYS_BUS_DEVICE,
1953 .instance_size = sizeof(Exynos4210fimdState),
1954 .instance_init = exynos4210_fimd_init,
1955 .class_init = exynos4210_fimd_class_init,
1956 };
1957
1958 static void exynos4210_fimd_register_types(void)
1959 {
1960 type_register_static(&exynos4210_fimd_info);
1961 }
1962
1963 type_init(exynos4210_fimd_register_types)