| 1 | /* |
| 2 | * OMAP LCD controller. |
| 3 | * |
| 4 | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "hw/core/irq.h" |
| 22 | #include "ui/console.h" |
| 23 | #include "hw/arm/omap.h" |
| 24 | #include "framebuffer.h" |
| 25 | #include "ui/pixel_ops.h" |
| 26 | #include "exec/cpu-common.h" |
| 27 | #include "system/physmem.h" |
| 28 | |
| 29 | struct omap_lcd_panel_s { |
| 30 | MemoryRegion *sysmem; |
| 31 | MemoryRegion iomem; |
| 32 | MemoryRegionSection fbsection; |
| 33 | qemu_irq irq; |
| 34 | QemuConsole *con; |
| 35 | |
| 36 | int plm; |
| 37 | int tft; |
| 38 | int mono; |
| 39 | int enable; |
| 40 | int width; |
| 41 | int height; |
| 42 | int interrupts; |
| 43 | uint32_t timing[3]; |
| 44 | uint32_t subpanel; |
| 45 | uint32_t ctrl; |
| 46 | |
| 47 | struct omap_dma_lcd_channel_s *dma; |
| 48 | uint16_t palette[256]; |
| 49 | int palette_done; |
| 50 | int frame_done; |
| 51 | int invalidate; |
| 52 | int sync_error; |
| 53 | }; |
| 54 | |
| 55 | static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
| 56 | { |
| 57 | if (s->frame_done && (s->interrupts & 1)) { |
| 58 | qemu_irq_raise(s->irq); |
| 59 | return; |
| 60 | } |
| 61 | |
| 62 | if (s->palette_done && (s->interrupts & 2)) { |
| 63 | qemu_irq_raise(s->irq); |
| 64 | return; |
| 65 | } |
| 66 | |
| 67 | if (s->sync_error) { |
| 68 | qemu_irq_raise(s->irq); |
| 69 | return; |
| 70 | } |
| 71 | |
| 72 | qemu_irq_lower(s->irq); |
| 73 | } |
| 74 | |
| 75 | /* |
| 76 | * 2-bit colour |
| 77 | */ |
| 78 | static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, |
| 79 | int width, int deststep) |
| 80 | { |
| 81 | uint16_t *pal = opaque; |
| 82 | uint8_t v, r, g, b; |
| 83 | |
| 84 | do { |
| 85 | v = ldub_p((void *) s); |
| 86 | r = (pal[v & 3] >> 4) & 0xf0; |
| 87 | g = pal[v & 3] & 0xf0; |
| 88 | b = (pal[v & 3] << 4) & 0xf0; |
| 89 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 90 | d += 4; |
| 91 | v >>= 2; |
| 92 | r = (pal[v & 3] >> 4) & 0xf0; |
| 93 | g = pal[v & 3] & 0xf0; |
| 94 | b = (pal[v & 3] << 4) & 0xf0; |
| 95 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 96 | d += 4; |
| 97 | v >>= 2; |
| 98 | r = (pal[v & 3] >> 4) & 0xf0; |
| 99 | g = pal[v & 3] & 0xf0; |
| 100 | b = (pal[v & 3] << 4) & 0xf0; |
| 101 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 102 | d += 4; |
| 103 | v >>= 2; |
| 104 | r = (pal[v & 3] >> 4) & 0xf0; |
| 105 | g = pal[v & 3] & 0xf0; |
| 106 | b = (pal[v & 3] << 4) & 0xf0; |
| 107 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 108 | d += 4; |
| 109 | s++; |
| 110 | width -= 4; |
| 111 | } while (width > 0); |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * 4-bit colour |
| 116 | */ |
| 117 | static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, |
| 118 | int width, int deststep) |
| 119 | { |
| 120 | uint16_t *pal = opaque; |
| 121 | uint8_t v, r, g, b; |
| 122 | |
| 123 | do { |
| 124 | v = ldub_p((void *) s); |
| 125 | r = (pal[v & 0xf] >> 4) & 0xf0; |
| 126 | g = pal[v & 0xf] & 0xf0; |
| 127 | b = (pal[v & 0xf] << 4) & 0xf0; |
| 128 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 129 | d += 4; |
| 130 | v >>= 4; |
| 131 | r = (pal[v & 0xf] >> 4) & 0xf0; |
| 132 | g = pal[v & 0xf] & 0xf0; |
| 133 | b = (pal[v & 0xf] << 4) & 0xf0; |
| 134 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 135 | d += 4; |
| 136 | s++; |
| 137 | width -= 2; |
| 138 | } while (width > 0); |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * 8-bit colour |
| 143 | */ |
| 144 | static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, |
| 145 | int width, int deststep) |
| 146 | { |
| 147 | uint16_t *pal = opaque; |
| 148 | uint8_t v, r, g, b; |
| 149 | |
| 150 | do { |
| 151 | v = ldub_p((void *) s); |
| 152 | r = (pal[v] >> 4) & 0xf0; |
| 153 | g = pal[v] & 0xf0; |
| 154 | b = (pal[v] << 4) & 0xf0; |
| 155 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 156 | s++; |
| 157 | d += 4; |
| 158 | } while (-- width != 0); |
| 159 | } |
| 160 | |
| 161 | /* |
| 162 | * 12-bit colour |
| 163 | */ |
| 164 | static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, |
| 165 | int width, int deststep) |
| 166 | { |
| 167 | uint16_t v; |
| 168 | uint8_t r, g, b; |
| 169 | |
| 170 | do { |
| 171 | v = lduw_le_p((void *) s); |
| 172 | r = (v >> 4) & 0xf0; |
| 173 | g = v & 0xf0; |
| 174 | b = (v << 4) & 0xf0; |
| 175 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 176 | s += 2; |
| 177 | d += 4; |
| 178 | } while (-- width != 0); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * 16-bit colour |
| 183 | */ |
| 184 | static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, |
| 185 | int width, int deststep) |
| 186 | { |
| 187 | uint16_t v; |
| 188 | uint8_t r, g, b; |
| 189 | |
| 190 | do { |
| 191 | v = lduw_le_p((void *) s); |
| 192 | r = (v >> 8) & 0xf8; |
| 193 | g = (v >> 3) & 0xfc; |
| 194 | b = (v << 3) & 0xf8; |
| 195 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
| 196 | s += 2; |
| 197 | d += 4; |
| 198 | } while (-- width != 0); |
| 199 | } |
| 200 | |
| 201 | static bool omap_update_display(void *opaque) |
| 202 | { |
| 203 | struct omap_lcd_panel_s *omap_lcd = opaque; |
| 204 | DisplaySurface *surface; |
| 205 | drawfn draw_line; |
| 206 | int size, height, first, last; |
| 207 | int width, linesize, step, bpp, frame_offset; |
| 208 | hwaddr frame_base; |
| 209 | |
| 210 | if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { |
| 211 | return true; |
| 212 | } |
| 213 | |
| 214 | surface = qemu_console_surface(omap_lcd->con); |
| 215 | if (!surface_bits_per_pixel(surface)) { |
| 216 | return true; |
| 217 | } |
| 218 | |
| 219 | frame_offset = 0; |
| 220 | if (omap_lcd->plm != 2) { |
| 221 | physical_memory_read( |
| 222 | omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], |
| 223 | omap_lcd->palette, 0x200); |
| 224 | switch (omap_lcd->palette[0] >> 12 & 7) { |
| 225 | case 3 ... 7: |
| 226 | frame_offset += 0x200; |
| 227 | break; |
| 228 | default: |
| 229 | frame_offset += 0x20; |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | /* Colour depth */ |
| 234 | switch ((omap_lcd->palette[0] >> 12) & 7) { |
| 235 | case 1: |
| 236 | draw_line = draw_line2_32; |
| 237 | bpp = 2; |
| 238 | break; |
| 239 | |
| 240 | case 2: |
| 241 | draw_line = draw_line4_32; |
| 242 | bpp = 4; |
| 243 | break; |
| 244 | |
| 245 | case 3: |
| 246 | draw_line = draw_line8_32; |
| 247 | bpp = 8; |
| 248 | break; |
| 249 | |
| 250 | case 4 ... 7: |
| 251 | if (!omap_lcd->tft) |
| 252 | draw_line = draw_line12_32; |
| 253 | else |
| 254 | draw_line = draw_line16_32; |
| 255 | bpp = 16; |
| 256 | break; |
| 257 | |
| 258 | default: |
| 259 | /* Unsupported at the moment. */ |
| 260 | return true; |
| 261 | } |
| 262 | |
| 263 | /* Resolution */ |
| 264 | width = omap_lcd->width; |
| 265 | if (width != surface_width(surface) || |
| 266 | omap_lcd->height != surface_height(surface)) { |
| 267 | qemu_console_resize(omap_lcd->con, |
| 268 | omap_lcd->width, omap_lcd->height); |
| 269 | surface = qemu_console_surface(omap_lcd->con); |
| 270 | omap_lcd->invalidate = 1; |
| 271 | } |
| 272 | |
| 273 | if (omap_lcd->dma->current_frame == 0) |
| 274 | size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; |
| 275 | else |
| 276 | size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; |
| 277 | |
| 278 | if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) { |
| 279 | omap_lcd->sync_error = 1; |
| 280 | omap_lcd_interrupts(omap_lcd); |
| 281 | omap_lcd->enable = 0; |
| 282 | return true; |
| 283 | } |
| 284 | |
| 285 | /* Content */ |
| 286 | frame_base = omap_lcd->dma->phys_framebuffer[ |
| 287 | omap_lcd->dma->current_frame] + frame_offset; |
| 288 | omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; |
| 289 | if (omap_lcd->dma->interrupts & 1) |
| 290 | qemu_irq_raise(omap_lcd->dma->irq); |
| 291 | if (omap_lcd->dma->dual) |
| 292 | omap_lcd->dma->current_frame ^= 1; |
| 293 | |
| 294 | if (!surface_bits_per_pixel(surface)) { |
| 295 | return true; |
| 296 | } |
| 297 | |
| 298 | first = 0; |
| 299 | height = omap_lcd->height; |
| 300 | if (omap_lcd->subpanel & (1 << 31)) { |
| 301 | if (omap_lcd->subpanel & (1 << 29)) |
| 302 | first = (omap_lcd->subpanel >> 16) & 0x3ff; |
| 303 | else |
| 304 | height = (omap_lcd->subpanel >> 16) & 0x3ff; |
| 305 | /* TODO: fill the rest of the panel with DPD */ |
| 306 | } |
| 307 | |
| 308 | step = width * bpp >> 3; |
| 309 | linesize = surface_stride(surface); |
| 310 | if (omap_lcd->invalidate) { |
| 311 | framebuffer_update_memory_section(&omap_lcd->fbsection, |
| 312 | omap_lcd->sysmem, frame_base, |
| 313 | height, step); |
| 314 | } |
| 315 | |
| 316 | framebuffer_update_display(surface, &omap_lcd->fbsection, |
| 317 | width, height, |
| 318 | step, linesize, 0, |
| 319 | omap_lcd->invalidate, |
| 320 | draw_line, omap_lcd->palette, |
| 321 | &first, &last); |
| 322 | |
| 323 | if (first >= 0) { |
| 324 | qemu_console_update(omap_lcd->con, 0, first, width, last - first + 1); |
| 325 | } |
| 326 | omap_lcd->invalidate = 0; |
| 327 | |
| 328 | return true; |
| 329 | } |
| 330 | |
| 331 | static void omap_invalidate_display(void *opaque) { |
| 332 | struct omap_lcd_panel_s *omap_lcd = opaque; |
| 333 | omap_lcd->invalidate = 1; |
| 334 | } |
| 335 | |
| 336 | static void omap_lcd_update(struct omap_lcd_panel_s *s) { |
| 337 | if (!s->enable) { |
| 338 | s->dma->current_frame = -1; |
| 339 | s->sync_error = 0; |
| 340 | if (s->plm != 1) |
| 341 | s->frame_done = 1; |
| 342 | omap_lcd_interrupts(s); |
| 343 | return; |
| 344 | } |
| 345 | |
| 346 | if (s->dma->current_frame == -1) { |
| 347 | s->frame_done = 0; |
| 348 | s->palette_done = 0; |
| 349 | s->dma->current_frame = 0; |
| 350 | } |
| 351 | |
| 352 | if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu, |
| 353 | s->dma->src_f1_top) || |
| 354 | !s->dma->mpu->port[ |
| 355 | s->dma->src].addr_valid(s->dma->mpu, |
| 356 | s->dma->src_f1_bottom) || |
| 357 | (s->dma->dual && |
| 358 | (!s->dma->mpu->port[ |
| 359 | s->dma->src].addr_valid(s->dma->mpu, |
| 360 | s->dma->src_f2_top) || |
| 361 | !s->dma->mpu->port[ |
| 362 | s->dma->src].addr_valid(s->dma->mpu, |
| 363 | s->dma->src_f2_bottom)))) { |
| 364 | s->dma->condition |= 1 << 2; |
| 365 | if (s->dma->interrupts & (1 << 1)) |
| 366 | qemu_irq_raise(s->dma->irq); |
| 367 | s->enable = 0; |
| 368 | return; |
| 369 | } |
| 370 | |
| 371 | s->dma->phys_framebuffer[0] = s->dma->src_f1_top; |
| 372 | s->dma->phys_framebuffer[1] = s->dma->src_f2_top; |
| 373 | |
| 374 | if (s->plm != 2 && !s->palette_done) { |
| 375 | physical_memory_read( |
| 376 | s->dma->phys_framebuffer[s->dma->current_frame], |
| 377 | s->palette, 0x200); |
| 378 | s->palette_done = 1; |
| 379 | omap_lcd_interrupts(s); |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size) |
| 384 | { |
| 385 | struct omap_lcd_panel_s *s = opaque; |
| 386 | |
| 387 | switch (addr) { |
| 388 | case 0x00: /* LCD_CONTROL */ |
| 389 | return (s->tft << 23) | (s->plm << 20) | |
| 390 | (s->tft << 7) | (s->interrupts << 3) | |
| 391 | (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34; |
| 392 | |
| 393 | case 0x04: /* LCD_TIMING0 */ |
| 394 | return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f; |
| 395 | |
| 396 | case 0x08: /* LCD_TIMING1 */ |
| 397 | return (s->timing[1] << 10) | (s->height - 1); |
| 398 | |
| 399 | case 0x0c: /* LCD_TIMING2 */ |
| 400 | return s->timing[2] | 0xfc000000; |
| 401 | |
| 402 | case 0x10: /* LCD_STATUS */ |
| 403 | return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done; |
| 404 | |
| 405 | case 0x14: /* LCD_SUBPANEL */ |
| 406 | return s->subpanel; |
| 407 | |
| 408 | default: |
| 409 | break; |
| 410 | } |
| 411 | OMAP_BAD_REG(addr); |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | static void omap_lcdc_write(void *opaque, hwaddr addr, |
| 416 | uint64_t value, unsigned size) |
| 417 | { |
| 418 | struct omap_lcd_panel_s *s = opaque; |
| 419 | |
| 420 | switch (addr) { |
| 421 | case 0x00: /* LCD_CONTROL */ |
| 422 | s->plm = (value >> 20) & 3; |
| 423 | s->tft = (value >> 7) & 1; |
| 424 | s->interrupts = (value >> 3) & 3; |
| 425 | s->mono = (value >> 1) & 1; |
| 426 | s->ctrl = value & 0x01cff300; |
| 427 | if (s->enable != (value & 1)) { |
| 428 | s->enable = value & 1; |
| 429 | omap_lcd_update(s); |
| 430 | } |
| 431 | break; |
| 432 | |
| 433 | case 0x04: /* LCD_TIMING0 */ |
| 434 | s->timing[0] = value >> 10; |
| 435 | s->width = (value & 0x3ff) + 1; |
| 436 | break; |
| 437 | |
| 438 | case 0x08: /* LCD_TIMING1 */ |
| 439 | s->timing[1] = value >> 10; |
| 440 | s->height = (value & 0x3ff) + 1; |
| 441 | break; |
| 442 | |
| 443 | case 0x0c: /* LCD_TIMING2 */ |
| 444 | s->timing[2] = value; |
| 445 | break; |
| 446 | |
| 447 | case 0x10: /* LCD_STATUS */ |
| 448 | break; |
| 449 | |
| 450 | case 0x14: /* LCD_SUBPANEL */ |
| 451 | s->subpanel = value & 0xa1ffffff; |
| 452 | break; |
| 453 | |
| 454 | default: |
| 455 | OMAP_BAD_REG(addr); |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | static const MemoryRegionOps omap_lcdc_ops = { |
| 460 | .read = omap_lcdc_read, |
| 461 | .write = omap_lcdc_write, |
| 462 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 463 | }; |
| 464 | |
| 465 | void omap_lcdc_reset(struct omap_lcd_panel_s *s) |
| 466 | { |
| 467 | s->dma->current_frame = -1; |
| 468 | s->plm = 0; |
| 469 | s->tft = 0; |
| 470 | s->mono = 0; |
| 471 | s->enable = 0; |
| 472 | s->width = 0; |
| 473 | s->height = 0; |
| 474 | s->interrupts = 0; |
| 475 | s->timing[0] = 0; |
| 476 | s->timing[1] = 0; |
| 477 | s->timing[2] = 0; |
| 478 | s->subpanel = 0; |
| 479 | s->palette_done = 0; |
| 480 | s->frame_done = 0; |
| 481 | s->sync_error = 0; |
| 482 | s->invalidate = 1; |
| 483 | s->subpanel = 0; |
| 484 | s->ctrl = 0; |
| 485 | } |
| 486 | |
| 487 | static const GraphicHwOps omap_ops = { |
| 488 | .invalidate = omap_invalidate_display, |
| 489 | .gfx_update = omap_update_display, |
| 490 | }; |
| 491 | |
| 492 | struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, |
| 493 | hwaddr base, |
| 494 | qemu_irq irq, |
| 495 | struct omap_dma_lcd_channel_s *dma, |
| 496 | omap_clk clk) |
| 497 | { |
| 498 | struct omap_lcd_panel_s *s = g_new0(struct omap_lcd_panel_s, 1); |
| 499 | |
| 500 | s->irq = irq; |
| 501 | s->dma = dma; |
| 502 | s->sysmem = sysmem; |
| 503 | omap_lcdc_reset(s); |
| 504 | |
| 505 | memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100); |
| 506 | memory_region_add_subregion(sysmem, base, &s->iomem); |
| 507 | |
| 508 | s->con = qemu_graphic_console_create(NULL, 0, &omap_ops, s); |
| 509 | |
| 510 | return s; |
| 511 | } |