| 1 | /* |
| 2 | * QEMU SM501 Device |
| 3 | * |
| 4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI |
| 5 | * Copyright (c) 2016-2020 BALATON Zoltan |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "qemu/units.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "qemu/error-report.h" |
| 30 | #include "qemu/log.h" |
| 31 | #include "qemu/module.h" |
| 32 | #include "hw/usb/hcd-ohci.h" |
| 33 | #include "hw/char/serial-mm.h" |
| 34 | #include "ui/console.h" |
| 35 | #include "hw/core/sysbus.h" |
| 36 | #include "migration/vmstate.h" |
| 37 | #include "hw/pci/pci_device.h" |
| 38 | #include "hw/core/qdev-properties.h" |
| 39 | #include "hw/i2c/i2c.h" |
| 40 | #include "hw/display/i2c-ddc.h" |
| 41 | #include "qemu/range.h" |
| 42 | #include "ui/pixel_ops.h" |
| 43 | #include "qemu/bswap.h" |
| 44 | #include "trace.h" |
| 45 | #include "qom/object.h" |
| 46 | |
| 47 | #define MMIO_BASE_OFFSET 0x3e00000 |
| 48 | #define MMIO_SIZE 0x200000 |
| 49 | #define DC_PALETTE_ENTRIES (0x400 * 3) |
| 50 | |
| 51 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ |
| 52 | |
| 53 | /* System Configuration area */ |
| 54 | /* System config base */ |
| 55 | #define SM501_SYS_CONFIG 0x000000 |
| 56 | |
| 57 | /* config 1 */ |
| 58 | #define SM501_SYSTEM_CONTROL 0x000000 |
| 59 | |
| 60 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
| 61 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) |
| 62 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) |
| 63 | |
| 64 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
| 65 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) |
| 66 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) |
| 67 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) |
| 68 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) |
| 69 | |
| 70 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
| 71 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) |
| 72 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) |
| 73 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) |
| 74 | |
| 75 | /* miscellaneous control */ |
| 76 | |
| 77 | #define SM501_MISC_CONTROL 0x000004 |
| 78 | |
| 79 | #define SM501_MISC_BUS_SH 0x0 |
| 80 | #define SM501_MISC_BUS_PCI 0x1 |
| 81 | #define SM501_MISC_BUS_XSCALE 0x2 |
| 82 | #define SM501_MISC_BUS_NEC 0x6 |
| 83 | #define SM501_MISC_BUS_MASK 0x7 |
| 84 | |
| 85 | #define SM501_MISC_VR_62MB (1 << 3) |
| 86 | #define SM501_MISC_CDR_RESET (1 << 7) |
| 87 | #define SM501_MISC_USB_LB (1 << 8) |
| 88 | #define SM501_MISC_USB_SLAVE (1 << 9) |
| 89 | #define SM501_MISC_BL_1 (1 << 10) |
| 90 | #define SM501_MISC_MC (1 << 11) |
| 91 | #define SM501_MISC_DAC_POWER (1 << 12) |
| 92 | #define SM501_MISC_IRQ_INVERT (1 << 16) |
| 93 | #define SM501_MISC_SH (1 << 17) |
| 94 | |
| 95 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
| 96 | #define SM501_MISC_HOLD_8 (1 << 18) |
| 97 | #define SM501_MISC_HOLD_16 (2 << 18) |
| 98 | #define SM501_MISC_HOLD_24 (3 << 18) |
| 99 | #define SM501_MISC_HOLD_32 (4 << 18) |
| 100 | #define SM501_MISC_HOLD_MASK (7 << 18) |
| 101 | |
| 102 | #define SM501_MISC_FREQ_12 (1 << 24) |
| 103 | #define SM501_MISC_PNL_24BIT (1 << 25) |
| 104 | #define SM501_MISC_8051_LE (1 << 26) |
| 105 | |
| 106 | |
| 107 | |
| 108 | #define SM501_GPIO31_0_CONTROL 0x000008 |
| 109 | #define SM501_GPIO63_32_CONTROL 0x00000C |
| 110 | #define SM501_DRAM_CONTROL 0x000010 |
| 111 | |
| 112 | /* command list */ |
| 113 | #define SM501_ARBTRTN_CONTROL 0x000014 |
| 114 | |
| 115 | /* command list */ |
| 116 | #define SM501_COMMAND_LIST_STATUS 0x000024 |
| 117 | |
| 118 | /* interrupt debug */ |
| 119 | #define SM501_RAW_IRQ_STATUS 0x000028 |
| 120 | #define SM501_RAW_IRQ_CLEAR 0x000028 |
| 121 | #define SM501_IRQ_STATUS 0x00002C |
| 122 | #define SM501_IRQ_MASK 0x000030 |
| 123 | #define SM501_DEBUG_CONTROL 0x000034 |
| 124 | |
| 125 | /* power management */ |
| 126 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
| 127 | #define SM501_POWERMODE_V2X_SRC (1 << 20) |
| 128 | #define SM501_POWERMODE_M_SRC (1 << 12) |
| 129 | #define SM501_POWERMODE_M1_SRC (1 << 4) |
| 130 | |
| 131 | #define SM501_CURRENT_GATE 0x000038 |
| 132 | #define SM501_CURRENT_CLOCK 0x00003C |
| 133 | #define SM501_POWER_MODE_0_GATE 0x000040 |
| 134 | #define SM501_POWER_MODE_0_CLOCK 0x000044 |
| 135 | #define SM501_POWER_MODE_1_GATE 0x000048 |
| 136 | #define SM501_POWER_MODE_1_CLOCK 0x00004C |
| 137 | #define SM501_SLEEP_MODE_GATE 0x000050 |
| 138 | #define SM501_POWER_MODE_CONTROL 0x000054 |
| 139 | |
| 140 | /* power gates for units within the 501 */ |
| 141 | #define SM501_GATE_HOST 0 |
| 142 | #define SM501_GATE_MEMORY 1 |
| 143 | #define SM501_GATE_DISPLAY 2 |
| 144 | #define SM501_GATE_2D_ENGINE 3 |
| 145 | #define SM501_GATE_CSC 4 |
| 146 | #define SM501_GATE_ZVPORT 5 |
| 147 | #define SM501_GATE_GPIO 6 |
| 148 | #define SM501_GATE_UART0 7 |
| 149 | #define SM501_GATE_UART1 8 |
| 150 | #define SM501_GATE_SSP 10 |
| 151 | #define SM501_GATE_USB_HOST 11 |
| 152 | #define SM501_GATE_USB_GADGET 12 |
| 153 | #define SM501_GATE_UCONTROLLER 17 |
| 154 | #define SM501_GATE_AC97 18 |
| 155 | |
| 156 | /* panel clock */ |
| 157 | #define SM501_CLOCK_P2XCLK 24 |
| 158 | /* crt clock */ |
| 159 | #define SM501_CLOCK_V2XCLK 16 |
| 160 | /* main clock */ |
| 161 | #define SM501_CLOCK_MCLK 8 |
| 162 | /* SDRAM controller clock */ |
| 163 | #define SM501_CLOCK_M1XCLK 0 |
| 164 | |
| 165 | /* config 2 */ |
| 166 | #define SM501_PCI_MASTER_BASE 0x000058 |
| 167 | #define SM501_ENDIAN_CONTROL 0x00005C |
| 168 | #define SM501_DEVICEID 0x000060 |
| 169 | /* 0x050100A0 */ |
| 170 | |
| 171 | #define SM501_DEVICEID_SM501 0x05010000 |
| 172 | #define SM501_DEVICEID_IDMASK 0xffff0000 |
| 173 | #define SM501_DEVICEID_REVMASK 0x000000ff |
| 174 | |
| 175 | #define SM501_PLLCLOCK_COUNT 0x000064 |
| 176 | #define SM501_MISC_TIMING 0x000068 |
| 177 | #define SM501_CURRENT_SDRAM_CLOCK 0x00006C |
| 178 | |
| 179 | #define SM501_PROGRAMMABLE_PLL_CONTROL 0x000074 |
| 180 | |
| 181 | /* GPIO base */ |
| 182 | #define SM501_GPIO 0x010000 |
| 183 | #define SM501_GPIO_DATA_LOW 0x00 |
| 184 | #define SM501_GPIO_DATA_HIGH 0x04 |
| 185 | #define SM501_GPIO_DDR_LOW 0x08 |
| 186 | #define SM501_GPIO_DDR_HIGH 0x0C |
| 187 | #define SM501_GPIO_IRQ_SETUP 0x10 |
| 188 | #define SM501_GPIO_IRQ_STATUS 0x14 |
| 189 | #define SM501_GPIO_IRQ_RESET 0x14 |
| 190 | |
| 191 | /* I2C controller base */ |
| 192 | #define SM501_I2C 0x010040 |
| 193 | #define SM501_I2C_BYTE_COUNT 0x00 |
| 194 | #define SM501_I2C_CONTROL 0x01 |
| 195 | #define SM501_I2C_STATUS 0x02 |
| 196 | #define SM501_I2C_RESET 0x02 |
| 197 | #define SM501_I2C_SLAVE_ADDRESS 0x03 |
| 198 | #define SM501_I2C_DATA 0x04 |
| 199 | |
| 200 | #define SM501_I2C_CONTROL_START (1 << 2) |
| 201 | #define SM501_I2C_CONTROL_ENABLE (1 << 0) |
| 202 | |
| 203 | #define SM501_I2C_STATUS_COMPLETE (1 << 3) |
| 204 | #define SM501_I2C_STATUS_ERROR (1 << 2) |
| 205 | |
| 206 | #define SM501_I2C_RESET_ERROR (1 << 2) |
| 207 | |
| 208 | /* SSP base */ |
| 209 | #define SM501_SSP 0x020000 |
| 210 | |
| 211 | /* Uart 0 base */ |
| 212 | #define SM501_UART0 0x030000 |
| 213 | |
| 214 | /* Uart 1 base */ |
| 215 | #define SM501_UART1 0x030020 |
| 216 | |
| 217 | /* USB host port base */ |
| 218 | #define SM501_USB_HOST 0x040000 |
| 219 | |
| 220 | /* USB slave/gadget base */ |
| 221 | #define SM501_USB_GADGET 0x060000 |
| 222 | |
| 223 | /* USB slave/gadget data port base */ |
| 224 | #define SM501_USB_GADGET_DATA 0x070000 |
| 225 | |
| 226 | /* Display controller/video engine base */ |
| 227 | #define SM501_DC 0x080000 |
| 228 | |
| 229 | /* common defines for the SM501 address registers */ |
| 230 | #define SM501_ADDR_FLIP (1 << 31) |
| 231 | #define SM501_ADDR_EXT (1 << 27) |
| 232 | #define SM501_ADDR_CS1 (1 << 26) |
| 233 | #define SM501_ADDR_MASK (0x3f << 26) |
| 234 | |
| 235 | #define SM501_FIFO_MASK (0x3 << 16) |
| 236 | #define SM501_FIFO_1 (0x0 << 16) |
| 237 | #define SM501_FIFO_3 (0x1 << 16) |
| 238 | #define SM501_FIFO_7 (0x2 << 16) |
| 239 | #define SM501_FIFO_11 (0x3 << 16) |
| 240 | |
| 241 | /* common registers for panel and the crt */ |
| 242 | #define SM501_OFF_DC_H_TOT 0x000 |
| 243 | #define SM501_OFF_DC_V_TOT 0x008 |
| 244 | #define SM501_OFF_DC_H_SYNC 0x004 |
| 245 | #define SM501_OFF_DC_V_SYNC 0x00C |
| 246 | |
| 247 | #define SM501_DC_PANEL_CONTROL 0x000 |
| 248 | |
| 249 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) |
| 250 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) |
| 251 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) |
| 252 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) |
| 253 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) |
| 254 | |
| 255 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) |
| 256 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) |
| 257 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) |
| 258 | |
| 259 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) |
| 260 | |
| 261 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) |
| 262 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) |
| 263 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) |
| 264 | |
| 265 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) |
| 266 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) |
| 267 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) |
| 268 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) |
| 269 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) |
| 270 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) |
| 271 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) |
| 272 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) |
| 273 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) |
| 274 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) |
| 275 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) |
| 276 | |
| 277 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) |
| 278 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) |
| 279 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) |
| 280 | |
| 281 | |
| 282 | #define SM501_DC_PANEL_PANNING_CONTROL 0x004 |
| 283 | #define SM501_DC_PANEL_COLOR_KEY 0x008 |
| 284 | #define SM501_DC_PANEL_FB_ADDR 0x00C |
| 285 | #define SM501_DC_PANEL_FB_OFFSET 0x010 |
| 286 | #define SM501_DC_PANEL_FB_WIDTH 0x014 |
| 287 | #define SM501_DC_PANEL_FB_HEIGHT 0x018 |
| 288 | #define SM501_DC_PANEL_TL_LOC 0x01C |
| 289 | #define SM501_DC_PANEL_BR_LOC 0x020 |
| 290 | #define SM501_DC_PANEL_H_TOT 0x024 |
| 291 | #define SM501_DC_PANEL_H_SYNC 0x028 |
| 292 | #define SM501_DC_PANEL_V_TOT 0x02C |
| 293 | #define SM501_DC_PANEL_V_SYNC 0x030 |
| 294 | #define SM501_DC_PANEL_CUR_LINE 0x034 |
| 295 | |
| 296 | #define SM501_DC_VIDEO_CONTROL 0x040 |
| 297 | #define SM501_DC_VIDEO_FB0_ADDR 0x044 |
| 298 | #define SM501_DC_VIDEO_FB_WIDTH 0x048 |
| 299 | #define SM501_DC_VIDEO_FB0_LAST_ADDR 0x04C |
| 300 | #define SM501_DC_VIDEO_TL_LOC 0x050 |
| 301 | #define SM501_DC_VIDEO_BR_LOC 0x054 |
| 302 | #define SM501_DC_VIDEO_SCALE 0x058 |
| 303 | #define SM501_DC_VIDEO_INIT_SCALE 0x05C |
| 304 | #define SM501_DC_VIDEO_YUV_CONSTANTS 0x060 |
| 305 | #define SM501_DC_VIDEO_FB1_ADDR 0x064 |
| 306 | #define SM501_DC_VIDEO_FB1_LAST_ADDR 0x068 |
| 307 | |
| 308 | #define SM501_DC_VIDEO_ALPHA_CONTROL 0x080 |
| 309 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR 0x084 |
| 310 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET 0x088 |
| 311 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR 0x08C |
| 312 | #define SM501_DC_VIDEO_ALPHA_TL_LOC 0x090 |
| 313 | #define SM501_DC_VIDEO_ALPHA_BR_LOC 0x094 |
| 314 | #define SM501_DC_VIDEO_ALPHA_SCALE 0x098 |
| 315 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE 0x09C |
| 316 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY 0x0A0 |
| 317 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP 0x0A4 |
| 318 | |
| 319 | #define SM501_DC_PANEL_HWC_BASE 0x0F0 |
| 320 | #define SM501_DC_PANEL_HWC_ADDR 0x0F0 |
| 321 | #define SM501_DC_PANEL_HWC_LOC 0x0F4 |
| 322 | #define SM501_DC_PANEL_HWC_COLOR_1_2 0x0F8 |
| 323 | #define SM501_DC_PANEL_HWC_COLOR_3 0x0FC |
| 324 | |
| 325 | #define SM501_HWC_EN (1 << 31) |
| 326 | |
| 327 | #define SM501_OFF_HWC_ADDR 0x00 |
| 328 | #define SM501_OFF_HWC_LOC 0x04 |
| 329 | #define SM501_OFF_HWC_COLOR_1_2 0x08 |
| 330 | #define SM501_OFF_HWC_COLOR_3 0x0C |
| 331 | |
| 332 | #define SM501_DC_ALPHA_CONTROL 0x100 |
| 333 | #define SM501_DC_ALPHA_FB_ADDR 0x104 |
| 334 | #define SM501_DC_ALPHA_FB_OFFSET 0x108 |
| 335 | #define SM501_DC_ALPHA_TL_LOC 0x10C |
| 336 | #define SM501_DC_ALPHA_BR_LOC 0x110 |
| 337 | #define SM501_DC_ALPHA_CHROMA_KEY 0x114 |
| 338 | #define SM501_DC_ALPHA_COLOR_LOOKUP 0x118 |
| 339 | |
| 340 | #define SM501_DC_CRT_CONTROL 0x200 |
| 341 | |
| 342 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) |
| 343 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) |
| 344 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) |
| 345 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) |
| 346 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) |
| 347 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) |
| 348 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) |
| 349 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) |
| 350 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
| 351 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
| 352 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) |
| 353 | |
| 354 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
| 355 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) |
| 356 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) |
| 357 | |
| 358 | #define SM501_DC_CRT_FB_ADDR 0x204 |
| 359 | #define SM501_DC_CRT_FB_OFFSET 0x208 |
| 360 | #define SM501_DC_CRT_H_TOT 0x20C |
| 361 | #define SM501_DC_CRT_H_SYNC 0x210 |
| 362 | #define SM501_DC_CRT_V_TOT 0x214 |
| 363 | #define SM501_DC_CRT_V_SYNC 0x218 |
| 364 | #define SM501_DC_CRT_SIGNATURE_ANALYZER 0x21C |
| 365 | #define SM501_DC_CRT_CUR_LINE 0x220 |
| 366 | #define SM501_DC_CRT_MONITOR_DETECT 0x224 |
| 367 | |
| 368 | #define SM501_DC_CRT_HWC_BASE 0x230 |
| 369 | #define SM501_DC_CRT_HWC_ADDR 0x230 |
| 370 | #define SM501_DC_CRT_HWC_LOC 0x234 |
| 371 | #define SM501_DC_CRT_HWC_COLOR_1_2 0x238 |
| 372 | #define SM501_DC_CRT_HWC_COLOR_3 0x23C |
| 373 | |
| 374 | #define SM501_DC_PANEL_PALETTE 0x400 |
| 375 | |
| 376 | #define SM501_DC_VIDEO_PALETTE 0x800 |
| 377 | |
| 378 | #define SM501_DC_CRT_PALETTE 0xC00 |
| 379 | |
| 380 | /* Zoom Video port base */ |
| 381 | #define SM501_ZVPORT 0x090000 |
| 382 | |
| 383 | /* AC97/I2S base */ |
| 384 | #define SM501_AC97 0x0A0000 |
| 385 | |
| 386 | /* 8051 micro controller base */ |
| 387 | #define SM501_UCONTROLLER 0x0B0000 |
| 388 | |
| 389 | /* 8051 micro controller SRAM base */ |
| 390 | #define SM501_UCONTROLLER_SRAM 0x0C0000 |
| 391 | |
| 392 | /* DMA base */ |
| 393 | #define SM501_DMA 0x0D0000 |
| 394 | |
| 395 | /* 2d engine base */ |
| 396 | #define SM501_2D_ENGINE 0x100000 |
| 397 | #define SM501_2D_SOURCE 0x00 |
| 398 | #define SM501_2D_DESTINATION 0x04 |
| 399 | #define SM501_2D_DIMENSION 0x08 |
| 400 | #define SM501_2D_CONTROL 0x0C |
| 401 | #define SM501_2D_PITCH 0x10 |
| 402 | #define SM501_2D_FOREGROUND 0x14 |
| 403 | #define SM501_2D_BACKGROUND 0x18 |
| 404 | #define SM501_2D_STRETCH 0x1C |
| 405 | #define SM501_2D_COLOR_COMPARE 0x20 |
| 406 | #define SM501_2D_COLOR_COMPARE_MASK 0x24 |
| 407 | #define SM501_2D_MASK 0x28 |
| 408 | #define SM501_2D_CLIP_TL 0x2C |
| 409 | #define SM501_2D_CLIP_BR 0x30 |
| 410 | #define SM501_2D_MONO_PATTERN_LOW 0x34 |
| 411 | #define SM501_2D_MONO_PATTERN_HIGH 0x38 |
| 412 | #define SM501_2D_WINDOW_WIDTH 0x3C |
| 413 | #define SM501_2D_SOURCE_BASE 0x40 |
| 414 | #define SM501_2D_DESTINATION_BASE 0x44 |
| 415 | #define SM501_2D_ALPHA 0x48 |
| 416 | #define SM501_2D_WRAP 0x4C |
| 417 | #define SM501_2D_STATUS 0x50 |
| 418 | |
| 419 | #define SM501_CSC_Y_SOURCE_BASE 0xC8 |
| 420 | #define SM501_CSC_CONSTANTS 0xCC |
| 421 | #define SM501_CSC_Y_SOURCE_X 0xD0 |
| 422 | #define SM501_CSC_Y_SOURCE_Y 0xD4 |
| 423 | #define SM501_CSC_U_SOURCE_BASE 0xD8 |
| 424 | #define SM501_CSC_V_SOURCE_BASE 0xDC |
| 425 | #define SM501_CSC_SOURCE_DIMENSION 0xE0 |
| 426 | #define SM501_CSC_SOURCE_PITCH 0xE4 |
| 427 | #define SM501_CSC_DESTINATION 0xE8 |
| 428 | #define SM501_CSC_DESTINATION_DIMENSION 0xEC |
| 429 | #define SM501_CSC_DESTINATION_PITCH 0xF0 |
| 430 | #define SM501_CSC_SCALE_FACTOR 0xF4 |
| 431 | #define SM501_CSC_DESTINATION_BASE 0xF8 |
| 432 | #define SM501_CSC_CONTROL 0xFC |
| 433 | |
| 434 | /* 2d engine data port base */ |
| 435 | #define SM501_2D_ENGINE_DATA 0x110000 |
| 436 | |
| 437 | /* end of register definitions */ |
| 438 | |
| 439 | #define SM501_HWC_WIDTH 64 |
| 440 | #define SM501_HWC_HEIGHT 64 |
| 441 | |
| 442 | #ifdef CONFIG_PIXMAN |
| 443 | #define DEFAULT_X_PIXMAN 7 |
| 444 | #else |
| 445 | #define DEFAULT_X_PIXMAN 0 |
| 446 | #endif |
| 447 | |
| 448 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ |
| 449 | static const uint32_t sm501_mem_local_size[] = { |
| 450 | [0] = 4 * MiB, |
| 451 | [1] = 8 * MiB, |
| 452 | [2] = 16 * MiB, |
| 453 | [3] = 32 * MiB, |
| 454 | [4] = 64 * MiB, |
| 455 | [5] = 2 * MiB, |
| 456 | }; |
| 457 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] |
| 458 | |
| 459 | typedef struct SM501State { |
| 460 | /* graphic console status */ |
| 461 | QemuConsole *con; |
| 462 | |
| 463 | /* status & internal resources */ |
| 464 | uint32_t local_mem_size_index; |
| 465 | uint8_t *local_mem; |
| 466 | MemoryRegion local_mem_region; |
| 467 | MemoryRegion mmio_region; |
| 468 | MemoryRegion system_config_region; |
| 469 | MemoryRegion i2c_region; |
| 470 | MemoryRegion disp_ctrl_region; |
| 471 | MemoryRegion twoD_engine_region; |
| 472 | uint32_t last_width; |
| 473 | uint32_t last_height; |
| 474 | bool do_full_update; /* perform a full update next time */ |
| 475 | uint8_t use_pixman; |
| 476 | I2CBus *i2c_bus; |
| 477 | |
| 478 | /* mmio registers */ |
| 479 | uint32_t system_control; |
| 480 | uint32_t misc_control; |
| 481 | uint32_t gpio_31_0_control; |
| 482 | uint32_t gpio_63_32_control; |
| 483 | uint32_t dram_control; |
| 484 | uint32_t arbitration_control; |
| 485 | uint32_t irq_mask; |
| 486 | uint32_t misc_timing; |
| 487 | uint32_t power_mode_control; |
| 488 | |
| 489 | uint8_t i2c_byte_count; |
| 490 | uint8_t i2c_status; |
| 491 | uint8_t i2c_addr; |
| 492 | uint8_t i2c_data[16]; |
| 493 | |
| 494 | uint32_t uart0_ier; |
| 495 | uint32_t uart0_lcr; |
| 496 | uint32_t uart0_mcr; |
| 497 | uint32_t uart0_scr; |
| 498 | |
| 499 | uint8_t dc_palette[DC_PALETTE_ENTRIES]; |
| 500 | |
| 501 | uint32_t dc_panel_control; |
| 502 | uint32_t dc_panel_panning_control; |
| 503 | uint32_t dc_panel_fb_addr; |
| 504 | uint32_t dc_panel_fb_offset; |
| 505 | uint32_t dc_panel_fb_width; |
| 506 | uint32_t dc_panel_fb_height; |
| 507 | uint32_t dc_panel_tl_location; |
| 508 | uint32_t dc_panel_br_location; |
| 509 | uint32_t dc_panel_h_total; |
| 510 | uint32_t dc_panel_h_sync; |
| 511 | uint32_t dc_panel_v_total; |
| 512 | uint32_t dc_panel_v_sync; |
| 513 | |
| 514 | uint32_t dc_panel_hwc_addr; |
| 515 | uint32_t dc_panel_hwc_location; |
| 516 | uint32_t dc_panel_hwc_color_1_2; |
| 517 | uint32_t dc_panel_hwc_color_3; |
| 518 | |
| 519 | uint32_t dc_video_control; |
| 520 | |
| 521 | uint32_t dc_crt_control; |
| 522 | uint32_t dc_crt_fb_addr; |
| 523 | uint32_t dc_crt_fb_offset; |
| 524 | uint32_t dc_crt_h_total; |
| 525 | uint32_t dc_crt_h_sync; |
| 526 | uint32_t dc_crt_v_total; |
| 527 | uint32_t dc_crt_v_sync; |
| 528 | |
| 529 | uint32_t dc_crt_hwc_addr; |
| 530 | uint32_t dc_crt_hwc_location; |
| 531 | uint32_t dc_crt_hwc_color_1_2; |
| 532 | uint32_t dc_crt_hwc_color_3; |
| 533 | |
| 534 | uint32_t twoD_source; |
| 535 | uint32_t twoD_destination; |
| 536 | uint32_t twoD_dimension; |
| 537 | uint32_t twoD_control; |
| 538 | uint32_t twoD_pitch; |
| 539 | uint32_t twoD_foreground; |
| 540 | uint32_t twoD_background; |
| 541 | uint32_t twoD_stretch; |
| 542 | uint32_t twoD_color_compare; |
| 543 | uint32_t twoD_color_compare_mask; |
| 544 | uint32_t twoD_mask; |
| 545 | uint32_t twoD_clip_tl; |
| 546 | uint32_t twoD_clip_br; |
| 547 | uint32_t twoD_mono_pattern_low; |
| 548 | uint32_t twoD_mono_pattern_high; |
| 549 | uint32_t twoD_window_width; |
| 550 | uint32_t twoD_source_base; |
| 551 | uint32_t twoD_destination_base; |
| 552 | uint32_t twoD_alpha; |
| 553 | uint32_t twoD_wrap; |
| 554 | } SM501State; |
| 555 | |
| 556 | static uint32_t get_local_mem_size_index(uint32_t size) |
| 557 | { |
| 558 | uint32_t norm_size = 0; |
| 559 | int i, index = 0; |
| 560 | |
| 561 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
| 562 | uint32_t new_size = sm501_mem_local_size[i]; |
| 563 | if (new_size >= size) { |
| 564 | if (norm_size == 0 || norm_size > new_size) { |
| 565 | norm_size = new_size; |
| 566 | index = i; |
| 567 | } |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | return index; |
| 572 | } |
| 573 | |
| 574 | static void set_new_local_mem_size_index(SM501State *s, uint32_t idx) |
| 575 | { |
| 576 | /* |
| 577 | * Update local_mem_size_index on guest write. We don't allow this |
| 578 | * to be set to larger than the actual RAM size. (The guest will |
| 579 | * still read back the SYSTEM_CONTROL.Size bits that it wrote.) |
| 580 | */ |
| 581 | if (idx < ARRAY_SIZE(sm501_mem_local_size) && |
| 582 | sm501_mem_local_size[idx] <= memory_region_size(&s->local_mem_region)) { |
| 583 | s->local_mem_size_index = idx; |
| 584 | return; |
| 585 | } |
| 586 | qemu_log_mask(LOG_GUEST_ERROR, |
| 587 | "sm501: Guest set DRAM_CONTROL.Size to 0x%x but " |
| 588 | "local memory is not that large\n", |
| 589 | idx); |
| 590 | /* Don't change the effective size, leave it as whatever it was */ |
| 591 | } |
| 592 | |
| 593 | static ram_addr_t get_fb_addr(SM501State *s, int crt) |
| 594 | { |
| 595 | return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; |
| 596 | } |
| 597 | |
| 598 | static inline int get_width(SM501State *s, int crt) |
| 599 | { |
| 600 | int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; |
| 601 | return (width & 0x00000FFF) + 1; |
| 602 | } |
| 603 | |
| 604 | static inline int get_height(SM501State *s, int crt) |
| 605 | { |
| 606 | int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; |
| 607 | return (height & 0x00000FFF) + 1; |
| 608 | } |
| 609 | |
| 610 | static inline int get_bpp(SM501State *s, int crt) |
| 611 | { |
| 612 | int bpp = crt ? s->dc_crt_control : s->dc_panel_control; |
| 613 | return 1 << (bpp & 3); |
| 614 | } |
| 615 | |
| 616 | /** |
| 617 | * Check the availability of hardware cursor. |
| 618 | * @param crt 0 for PANEL, 1 for CRT. |
| 619 | */ |
| 620 | static inline int is_hwc_enabled(SM501State *state, int crt) |
| 621 | { |
| 622 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; |
| 623 | return addr & SM501_HWC_EN; |
| 624 | } |
| 625 | |
| 626 | /** |
| 627 | * Get the address which holds cursor pattern data. |
| 628 | * @param crt 0 for PANEL, 1 for CRT. |
| 629 | */ |
| 630 | static inline uint8_t *get_hwc_address(SM501State *state, int crt) |
| 631 | { |
| 632 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; |
| 633 | return state->local_mem + (addr & 0x03FFFFF0); |
| 634 | } |
| 635 | |
| 636 | /** |
| 637 | * Get the cursor position in y coordinate. |
| 638 | * @param crt 0 for PANEL, 1 for CRT. |
| 639 | */ |
| 640 | static inline uint32_t get_hwc_y(SM501State *state, int crt) |
| 641 | { |
| 642 | uint32_t location = crt ? state->dc_crt_hwc_location |
| 643 | : state->dc_panel_hwc_location; |
| 644 | return (location & 0x07FF0000) >> 16; |
| 645 | } |
| 646 | |
| 647 | /** |
| 648 | * Get the cursor position in x coordinate. |
| 649 | * @param crt 0 for PANEL, 1 for CRT. |
| 650 | */ |
| 651 | static inline uint32_t get_hwc_x(SM501State *state, int crt) |
| 652 | { |
| 653 | uint32_t location = crt ? state->dc_crt_hwc_location |
| 654 | : state->dc_panel_hwc_location; |
| 655 | return location & 0x000007FF; |
| 656 | } |
| 657 | |
| 658 | /** |
| 659 | * Get the hardware cursor palette. |
| 660 | * @param crt 0 for PANEL, 1 for CRT. |
| 661 | * @param palette pointer to a [3 * 3] array to store color values in |
| 662 | */ |
| 663 | static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) |
| 664 | { |
| 665 | int i; |
| 666 | uint32_t color_reg; |
| 667 | uint16_t rgb565; |
| 668 | |
| 669 | for (i = 0; i < 3; i++) { |
| 670 | if (i + 1 == 3) { |
| 671 | color_reg = crt ? state->dc_crt_hwc_color_3 |
| 672 | : state->dc_panel_hwc_color_3; |
| 673 | } else { |
| 674 | color_reg = crt ? state->dc_crt_hwc_color_1_2 |
| 675 | : state->dc_panel_hwc_color_1_2; |
| 676 | } |
| 677 | |
| 678 | if (i + 1 == 2) { |
| 679 | rgb565 = (color_reg >> 16) & 0xFFFF; |
| 680 | } else { |
| 681 | rgb565 = color_reg & 0xFFFF; |
| 682 | } |
| 683 | palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ |
| 684 | palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ |
| 685 | palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | static inline void hwc_invalidate(SM501State *s, int crt) |
| 690 | { |
| 691 | int w = get_width(s, crt); |
| 692 | int h = get_height(s, crt); |
| 693 | int bpp = get_bpp(s, crt); |
| 694 | int start = get_hwc_y(s, crt); |
| 695 | int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; |
| 696 | |
| 697 | start *= w * bpp; |
| 698 | end *= w * bpp; |
| 699 | |
| 700 | memory_region_set_dirty(&s->local_mem_region, |
| 701 | get_fb_addr(s, crt) + start, end - start); |
| 702 | } |
| 703 | |
| 704 | static bool sm501_rect_outside_vram(SM501State *s, uint32_t base, |
| 705 | uint32_t x, uint32_t y, |
| 706 | uint32_t width, uint32_t height, |
| 707 | uint32_t pitch, uint32_t bypp) |
| 708 | { |
| 709 | /* |
| 710 | * Return true if the 2D area specified by the arguments is |
| 711 | * partially or completely outside the VRAM (a guest error) |
| 712 | * |
| 713 | * Limits on the input sizes mean we can't overflow as long as |
| 714 | * we do all the arithmetic at 64 bits. |
| 715 | */ |
| 716 | uint64_t rect_size, last_addr; |
| 717 | |
| 718 | assert(x <= UINT16_MAX && y <= UINT16_MAX && height <= UINT16_MAX && |
| 719 | pitch <= UINT16_MAX && bypp <= 8); |
| 720 | rect_size = (((uint64_t)y + height) * pitch + x + width) * bypp; |
| 721 | last_addr = base + rect_size; |
| 722 | |
| 723 | return last_addr >= get_local_mem_size(s); |
| 724 | } |
| 725 | |
| 726 | static void sm501_2d_operation(SM501State *s) |
| 727 | { |
| 728 | int cmd = (s->twoD_control >> 16) & 0x1F; |
| 729 | int rtl = s->twoD_control & BIT(27); |
| 730 | int format = (s->twoD_stretch >> 20) & 3; |
| 731 | int bypp = 1 << format; /* bytes per pixel */ |
| 732 | int rop_mode = (s->twoD_control >> 15) & 1; /* 1 for rop2, else rop3 */ |
| 733 | /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ |
| 734 | int rop2_source_is_pattern = (s->twoD_control >> 14) & 1; |
| 735 | int rop = s->twoD_control & 0xFF; |
| 736 | unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
| 737 | unsigned int dst_y = s->twoD_destination & 0xFFFF; |
| 738 | unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF; |
| 739 | unsigned int height = s->twoD_dimension & 0xFFFF; |
| 740 | uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; |
| 741 | unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; |
| 742 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
| 743 | int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); |
| 744 | bool overlap = false, fallback = false; |
| 745 | |
| 746 | if ((s->twoD_stretch >> 16) & 0xF) { |
| 747 | qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); |
| 748 | return; |
| 749 | } |
| 750 | |
| 751 | if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { |
| 752 | qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); |
| 753 | return; |
| 754 | } |
| 755 | |
| 756 | if (!dst_pitch) { |
| 757 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n"); |
| 758 | return; |
| 759 | } |
| 760 | |
| 761 | if (!width || !height) { |
| 762 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n"); |
| 763 | return; |
| 764 | } |
| 765 | |
| 766 | if (rtl) { |
| 767 | if (dst_x < (width - 1) || dst_y < (height - 1)) { |
| 768 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: RTL op out of bounds\n"); |
| 769 | return; |
| 770 | } |
| 771 | dst_x -= width - 1; |
| 772 | dst_y -= height - 1; |
| 773 | } |
| 774 | |
| 775 | if (sm501_rect_outside_vram(s, dst_base, dst_x, dst_y, width, height, |
| 776 | dst_pitch, bypp)) { |
| 777 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n"); |
| 778 | return; |
| 779 | } |
| 780 | |
| 781 | switch (cmd) { |
| 782 | case 0: /* BitBlt */ |
| 783 | { |
| 784 | unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF; |
| 785 | unsigned int src_y = s->twoD_source & 0xFFFF; |
| 786 | uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; |
| 787 | unsigned int src_pitch = s->twoD_pitch & 0x1FFF; |
| 788 | |
| 789 | if (!src_pitch) { |
| 790 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n"); |
| 791 | return; |
| 792 | } |
| 793 | |
| 794 | if (rtl) { |
| 795 | if (src_x < (width - 1) || src_y < (height - 1)) { |
| 796 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: RTL op out of bounds\n"); |
| 797 | return; |
| 798 | } |
| 799 | src_x -= width - 1; |
| 800 | src_y -= height - 1; |
| 801 | } |
| 802 | |
| 803 | if (sm501_rect_outside_vram(s, src_base, src_x, src_y, width, height, |
| 804 | src_pitch, bypp)) { |
| 805 | qemu_log_mask(LOG_GUEST_ERROR, |
| 806 | "sm501: 2D op src is outside vram.\n"); |
| 807 | return; |
| 808 | } |
| 809 | |
| 810 | if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) { |
| 811 | /* DSTINVERT, is there a way to do this with pixman? */ |
| 812 | unsigned int x, y, i; |
| 813 | uint8_t *d = s->local_mem + dst_base; |
| 814 | |
| 815 | for (y = 0; y < height; y++) { |
| 816 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
| 817 | for (x = 0; x < width; x++, i += bypp) { |
| 818 | stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp)); |
| 819 | } |
| 820 | } |
| 821 | } else if (!rop_mode && rop == 0x99) { |
| 822 | /* DSxn, is there a way to do this with pixman? */ |
| 823 | unsigned int x, y, i, j; |
| 824 | uint8_t *sp = s->local_mem + src_base; |
| 825 | uint8_t *d = s->local_mem + dst_base; |
| 826 | |
| 827 | for (y = 0; y < height; y++) { |
| 828 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
| 829 | j = (src_x + (src_y + y) * src_pitch) * bypp; |
| 830 | for (x = 0; x < width; x++, i += bypp, j += bypp) { |
| 831 | stn_he_p(&d[i], bypp, |
| 832 | ~(ldn_he_p(&sp[j], bypp) ^ ldn_he_p(&d[i], bypp))); |
| 833 | } |
| 834 | } |
| 835 | } else if (!rop_mode && rop == 0xee) { |
| 836 | /* SRCPAINT, is there a way to do this with pixman? */ |
| 837 | unsigned int x, y, i, j; |
| 838 | uint8_t *sp = s->local_mem + src_base; |
| 839 | uint8_t *d = s->local_mem + dst_base; |
| 840 | |
| 841 | for (y = 0; y < height; y++) { |
| 842 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
| 843 | j = (src_x + (src_y + y) * src_pitch) * bypp; |
| 844 | for (x = 0; x < width; x++, i += bypp, j += bypp) { |
| 845 | stn_he_p(&d[i], bypp, |
| 846 | ldn_he_p(&sp[j], bypp) | ldn_he_p(&d[i], bypp)); |
| 847 | } |
| 848 | } |
| 849 | } else { |
| 850 | /* Do copy src for unimplemented ops, better than unpainted area */ |
| 851 | if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) || |
| 852 | (!rop_mode && rop != 0xcc)) { |
| 853 | qemu_log_mask(LOG_UNIMP, |
| 854 | "sm501: rop%d op %x%s not implemented\n", |
| 855 | (rop_mode ? 2 : 3), rop, |
| 856 | (rop2_source_is_pattern ? |
| 857 | " with pattern source" : "")); |
| 858 | } |
| 859 | /* Ignore no-op blits, some guests seem to do this */ |
| 860 | if (src_base == dst_base && src_pitch == dst_pitch && |
| 861 | src_x == dst_x && src_y == dst_y) { |
| 862 | break; |
| 863 | } |
| 864 | /* Some clients also do 1 pixel blits, avoid overhead for these */ |
| 865 | if (width == 1 && height == 1) { |
| 866 | unsigned int si = (src_x + src_y * src_pitch) * bypp; |
| 867 | unsigned int di = (dst_x + dst_y * dst_pitch) * bypp; |
| 868 | stn_he_p(&s->local_mem[dst_base + di], bypp, |
| 869 | ldn_he_p(&s->local_mem[src_base + si], bypp)); |
| 870 | break; |
| 871 | } |
| 872 | /* If reverse blit do simple check for overlaps */ |
| 873 | if (rtl && src_base == dst_base && src_pitch == dst_pitch) { |
| 874 | overlap = (src_x < dst_x + width && src_x + width > dst_x && |
| 875 | src_y < dst_y + height && src_y + height > dst_y); |
| 876 | } else if (rtl) { |
| 877 | unsigned int sb, se, db, de; |
| 878 | sb = src_base + (src_x + src_y * src_pitch) * bypp; |
| 879 | se = sb + (width + (height - 1) * src_pitch) * bypp; |
| 880 | db = dst_base + (dst_x + dst_y * dst_pitch) * bypp; |
| 881 | de = db + (width + (height - 1) * dst_pitch) * bypp; |
| 882 | overlap = (db < se && sb < de); |
| 883 | } |
| 884 | #ifdef CONFIG_PIXMAN |
| 885 | if (overlap && (s->use_pixman & BIT(2))) { |
| 886 | /* pixman can't do reverse blit: copy via temporary */ |
| 887 | int tmp_stride = DIV_ROUND_UP(width * bypp, sizeof(uint32_t)); |
| 888 | static uint32_t tmp_buf[16384]; |
| 889 | uint32_t *tmp = tmp_buf; |
| 890 | |
| 891 | if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) { |
| 892 | tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height); |
| 893 | } |
| 894 | fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], |
| 895 | tmp, |
| 896 | src_pitch * bypp / sizeof(uint32_t), |
| 897 | tmp_stride, |
| 898 | 8 * bypp, 8 * bypp, |
| 899 | src_x, src_y, 0, 0, width, height); |
| 900 | if (!fallback) { |
| 901 | fallback = !pixman_blt(tmp, |
| 902 | (uint32_t *)&s->local_mem[dst_base], |
| 903 | tmp_stride, |
| 904 | dst_pitch * bypp / sizeof(uint32_t), |
| 905 | 8 * bypp, 8 * bypp, |
| 906 | 0, 0, dst_x, dst_y, width, height); |
| 907 | } |
| 908 | if (tmp != tmp_buf) { |
| 909 | g_free(tmp); |
| 910 | } |
| 911 | } else if (!overlap && (s->use_pixman & BIT(1))) { |
| 912 | fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], |
| 913 | (uint32_t *)&s->local_mem[dst_base], |
| 914 | src_pitch * bypp / sizeof(uint32_t), |
| 915 | dst_pitch * bypp / sizeof(uint32_t), |
| 916 | 8 * bypp, 8 * bypp, src_x, src_y, |
| 917 | dst_x, dst_y, width, height); |
| 918 | } else |
| 919 | #endif |
| 920 | { |
| 921 | fallback = true; |
| 922 | } |
| 923 | if (fallback) { |
| 924 | uint8_t *sp = s->local_mem + src_base; |
| 925 | uint8_t *d = s->local_mem + dst_base; |
| 926 | unsigned int y, i, j; |
| 927 | for (y = 0; y < height; y++) { |
| 928 | if (overlap) { /* overlap also means rtl */ |
| 929 | i = (dst_y + height - 1 - y) * dst_pitch; |
| 930 | i = (dst_x + i) * bypp; |
| 931 | j = (src_y + height - 1 - y) * src_pitch; |
| 932 | j = (src_x + j) * bypp; |
| 933 | memmove(&d[i], &sp[j], width * bypp); |
| 934 | } else { |
| 935 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
| 936 | j = (src_x + (src_y + y) * src_pitch) * bypp; |
| 937 | memcpy(&d[i], &sp[j], width * bypp); |
| 938 | } |
| 939 | } |
| 940 | } |
| 941 | } |
| 942 | break; |
| 943 | } |
| 944 | case 1: /* Rectangle Fill */ |
| 945 | { |
| 946 | uint32_t color = s->twoD_foreground; |
| 947 | |
| 948 | if (format == 2) { |
| 949 | color = cpu_to_le32(color); |
| 950 | } else if (format == 1) { |
| 951 | color = cpu_to_le16(color); |
| 952 | } |
| 953 | |
| 954 | #ifdef CONFIG_PIXMAN |
| 955 | if (!(s->use_pixman & BIT(0)) || (width == 1 && height == 1) || |
| 956 | !pixman_fill((uint32_t *)&s->local_mem[dst_base], |
| 957 | dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, |
| 958 | dst_x, dst_y, width, height, color)) |
| 959 | #endif |
| 960 | { |
| 961 | /* fallback when pixman failed or we don't want to call it */ |
| 962 | uint8_t *d = s->local_mem + dst_base; |
| 963 | unsigned int x, y, i; |
| 964 | for (y = 0; y < height; y++) { |
| 965 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
| 966 | for (x = 0; x < width; x++, i += bypp) { |
| 967 | stn_he_p(&d[i], bypp, color); |
| 968 | } |
| 969 | } |
| 970 | } |
| 971 | break; |
| 972 | } |
| 973 | default: |
| 974 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", |
| 975 | cmd); |
| 976 | return; |
| 977 | } |
| 978 | |
| 979 | if (dst_base >= get_fb_addr(s, crt) && |
| 980 | dst_base <= get_fb_addr(s, crt) + fb_len) { |
| 981 | int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + |
| 982 | dst_x + width) * bypp); |
| 983 | if (dst_len) { |
| 984 | memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); |
| 985 | } |
| 986 | } |
| 987 | } |
| 988 | |
| 989 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
| 990 | unsigned size) |
| 991 | { |
| 992 | SM501State *s = opaque; |
| 993 | uint32_t ret = 0; |
| 994 | |
| 995 | switch (addr) { |
| 996 | case SM501_SYSTEM_CONTROL: |
| 997 | ret = s->system_control; |
| 998 | break; |
| 999 | case SM501_MISC_CONTROL: |
| 1000 | ret = s->misc_control; |
| 1001 | break; |
| 1002 | case SM501_GPIO31_0_CONTROL: |
| 1003 | ret = s->gpio_31_0_control; |
| 1004 | break; |
| 1005 | case SM501_GPIO63_32_CONTROL: |
| 1006 | ret = s->gpio_63_32_control; |
| 1007 | break; |
| 1008 | case SM501_DEVICEID: |
| 1009 | ret = 0x050100A0; |
| 1010 | break; |
| 1011 | case SM501_DRAM_CONTROL: |
| 1012 | ret = (s->dram_control & 0x07F1E7C0); |
| 1013 | break; |
| 1014 | case SM501_ARBTRTN_CONTROL: |
| 1015 | ret = s->arbitration_control; |
| 1016 | break; |
| 1017 | case SM501_COMMAND_LIST_STATUS: |
| 1018 | ret = 0x00180002; /* FIFOs are empty, everything idle */ |
| 1019 | break; |
| 1020 | case SM501_IRQ_MASK: |
| 1021 | ret = s->irq_mask; |
| 1022 | break; |
| 1023 | case SM501_MISC_TIMING: |
| 1024 | /* TODO : simulate gate control */ |
| 1025 | ret = s->misc_timing; |
| 1026 | break; |
| 1027 | case SM501_CURRENT_GATE: |
| 1028 | /* TODO : simulate gate control */ |
| 1029 | ret = 0x00021807; |
| 1030 | break; |
| 1031 | case SM501_CURRENT_CLOCK: |
| 1032 | ret = 0x2A1A0A09; |
| 1033 | break; |
| 1034 | case SM501_POWER_MODE_CONTROL: |
| 1035 | ret = s->power_mode_control; |
| 1036 | break; |
| 1037 | case SM501_ENDIAN_CONTROL: |
| 1038 | ret = 0; /* Only default little endian mode is supported */ |
| 1039 | break; |
| 1040 | |
| 1041 | default: |
| 1042 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
| 1043 | "register read. addr=%" HWADDR_PRIx "\n", addr); |
| 1044 | } |
| 1045 | trace_sm501_system_config_read(addr, ret); |
| 1046 | return ret; |
| 1047 | } |
| 1048 | |
| 1049 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
| 1050 | uint64_t value, unsigned size) |
| 1051 | { |
| 1052 | SM501State *s = opaque; |
| 1053 | |
| 1054 | trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); |
| 1055 | switch (addr) { |
| 1056 | case SM501_SYSTEM_CONTROL: |
| 1057 | s->system_control &= 0x10DB0000; |
| 1058 | s->system_control |= value & 0xEF00B8F7; |
| 1059 | break; |
| 1060 | case SM501_MISC_CONTROL: |
| 1061 | s->misc_control &= 0xEF; |
| 1062 | s->misc_control |= value & 0xFF7FFF10; |
| 1063 | break; |
| 1064 | case SM501_GPIO31_0_CONTROL: |
| 1065 | s->gpio_31_0_control = value; |
| 1066 | break; |
| 1067 | case SM501_GPIO63_32_CONTROL: |
| 1068 | s->gpio_63_32_control = value & 0xFF80FFFF; |
| 1069 | break; |
| 1070 | case SM501_DRAM_CONTROL: |
| 1071 | set_new_local_mem_size_index(s, (value >> 13) & 0x7); |
| 1072 | s->dram_control &= 0x80000000; |
| 1073 | s->dram_control |= value & 0x7FFFFFC3; |
| 1074 | break; |
| 1075 | case SM501_ARBTRTN_CONTROL: |
| 1076 | s->arbitration_control = value & 0x37777777; |
| 1077 | break; |
| 1078 | case SM501_IRQ_MASK: |
| 1079 | s->irq_mask = value & 0xFFDF3F5F; |
| 1080 | break; |
| 1081 | case SM501_MISC_TIMING: |
| 1082 | s->misc_timing = value & 0xF31F1FFF; |
| 1083 | break; |
| 1084 | case SM501_POWER_MODE_0_GATE: |
| 1085 | case SM501_POWER_MODE_1_GATE: |
| 1086 | case SM501_POWER_MODE_0_CLOCK: |
| 1087 | case SM501_POWER_MODE_1_CLOCK: |
| 1088 | /* TODO : simulate gate & clock control */ |
| 1089 | break; |
| 1090 | case SM501_POWER_MODE_CONTROL: |
| 1091 | s->power_mode_control = value & 0x00000003; |
| 1092 | break; |
| 1093 | case SM501_ENDIAN_CONTROL: |
| 1094 | if (value & 0x00000001) { |
| 1095 | qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" |
| 1096 | " implemented.\n"); |
| 1097 | } |
| 1098 | break; |
| 1099 | |
| 1100 | default: |
| 1101 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
| 1102 | "register write. addr=%" HWADDR_PRIx |
| 1103 | ", val=%" PRIx64 "\n", addr, value); |
| 1104 | } |
| 1105 | } |
| 1106 | |
| 1107 | static const MemoryRegionOps sm501_system_config_ops = { |
| 1108 | .read = sm501_system_config_read, |
| 1109 | .write = sm501_system_config_write, |
| 1110 | .valid = { |
| 1111 | .min_access_size = 4, |
| 1112 | .max_access_size = 4, |
| 1113 | }, |
| 1114 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1115 | }; |
| 1116 | |
| 1117 | static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) |
| 1118 | { |
| 1119 | SM501State *s = opaque; |
| 1120 | uint8_t ret = 0; |
| 1121 | |
| 1122 | switch (addr) { |
| 1123 | case SM501_I2C_BYTE_COUNT: |
| 1124 | ret = s->i2c_byte_count; |
| 1125 | break; |
| 1126 | case SM501_I2C_STATUS: |
| 1127 | ret = s->i2c_status; |
| 1128 | break; |
| 1129 | case SM501_I2C_SLAVE_ADDRESS: |
| 1130 | ret = s->i2c_addr; |
| 1131 | break; |
| 1132 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: |
| 1133 | ret = s->i2c_data[addr - SM501_I2C_DATA]; |
| 1134 | break; |
| 1135 | default: |
| 1136 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." |
| 1137 | " addr=0x%" HWADDR_PRIx "\n", addr); |
| 1138 | } |
| 1139 | trace_sm501_i2c_read((uint32_t)addr, ret); |
| 1140 | return ret; |
| 1141 | } |
| 1142 | |
| 1143 | static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, |
| 1144 | unsigned size) |
| 1145 | { |
| 1146 | SM501State *s = opaque; |
| 1147 | |
| 1148 | trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); |
| 1149 | switch (addr) { |
| 1150 | case SM501_I2C_BYTE_COUNT: |
| 1151 | s->i2c_byte_count = value & 0xf; |
| 1152 | break; |
| 1153 | case SM501_I2C_CONTROL: |
| 1154 | if (value & SM501_I2C_CONTROL_ENABLE) { |
| 1155 | if (value & SM501_I2C_CONTROL_START) { |
| 1156 | bool is_recv = s->i2c_addr & 1; |
| 1157 | int res = i2c_start_transfer(s->i2c_bus, |
| 1158 | s->i2c_addr >> 1, |
| 1159 | is_recv); |
| 1160 | if (res) { |
| 1161 | s->i2c_status |= SM501_I2C_STATUS_ERROR; |
| 1162 | } else { |
| 1163 | int i; |
| 1164 | for (i = 0; i <= s->i2c_byte_count; i++) { |
| 1165 | if (is_recv) { |
| 1166 | s->i2c_data[i] = i2c_recv(s->i2c_bus); |
| 1167 | } else if (i2c_send(s->i2c_bus, s->i2c_data[i]) < 0) { |
| 1168 | s->i2c_status |= SM501_I2C_STATUS_ERROR; |
| 1169 | return; |
| 1170 | } |
| 1171 | } |
| 1172 | if (i) { |
| 1173 | s->i2c_status = SM501_I2C_STATUS_COMPLETE; |
| 1174 | } |
| 1175 | } |
| 1176 | } else { |
| 1177 | i2c_end_transfer(s->i2c_bus); |
| 1178 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; |
| 1179 | } |
| 1180 | } |
| 1181 | break; |
| 1182 | case SM501_I2C_RESET: |
| 1183 | if ((value & SM501_I2C_RESET_ERROR) == 0) { |
| 1184 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; |
| 1185 | } |
| 1186 | break; |
| 1187 | case SM501_I2C_SLAVE_ADDRESS: |
| 1188 | s->i2c_addr = value & 0xff; |
| 1189 | break; |
| 1190 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: |
| 1191 | s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; |
| 1192 | break; |
| 1193 | default: |
| 1194 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " |
| 1195 | "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); |
| 1196 | } |
| 1197 | } |
| 1198 | |
| 1199 | static const MemoryRegionOps sm501_i2c_ops = { |
| 1200 | .read = sm501_i2c_read, |
| 1201 | .write = sm501_i2c_write, |
| 1202 | .valid = { |
| 1203 | .min_access_size = 1, |
| 1204 | .max_access_size = 1, |
| 1205 | }, |
| 1206 | .impl = { |
| 1207 | .min_access_size = 1, |
| 1208 | .max_access_size = 1, |
| 1209 | }, |
| 1210 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1211 | }; |
| 1212 | |
| 1213 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
| 1214 | { |
| 1215 | SM501State *s = opaque; |
| 1216 | |
| 1217 | trace_sm501_palette_read((uint32_t)addr); |
| 1218 | |
| 1219 | /* TODO : consider BYTE/WORD access */ |
| 1220 | /* TODO : consider endian */ |
| 1221 | |
| 1222 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
| 1223 | return *(uint32_t *)&s->dc_palette[addr]; |
| 1224 | } |
| 1225 | |
| 1226 | static void sm501_palette_write(void *opaque, hwaddr addr, |
| 1227 | uint32_t value) |
| 1228 | { |
| 1229 | SM501State *s = opaque; |
| 1230 | |
| 1231 | trace_sm501_palette_write((uint32_t)addr, value); |
| 1232 | |
| 1233 | /* TODO : consider BYTE/WORD access */ |
| 1234 | /* TODO : consider endian */ |
| 1235 | |
| 1236 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
| 1237 | *(uint32_t *)&s->dc_palette[addr] = value; |
| 1238 | s->do_full_update = true; |
| 1239 | } |
| 1240 | |
| 1241 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
| 1242 | unsigned size) |
| 1243 | { |
| 1244 | SM501State *s = opaque; |
| 1245 | uint32_t ret = 0; |
| 1246 | |
| 1247 | switch (addr) { |
| 1248 | |
| 1249 | case SM501_DC_PANEL_CONTROL: |
| 1250 | ret = s->dc_panel_control; |
| 1251 | break; |
| 1252 | case SM501_DC_PANEL_PANNING_CONTROL: |
| 1253 | ret = s->dc_panel_panning_control; |
| 1254 | break; |
| 1255 | case SM501_DC_PANEL_COLOR_KEY: |
| 1256 | /* Not implemented yet */ |
| 1257 | break; |
| 1258 | case SM501_DC_PANEL_FB_ADDR: |
| 1259 | ret = s->dc_panel_fb_addr; |
| 1260 | break; |
| 1261 | case SM501_DC_PANEL_FB_OFFSET: |
| 1262 | ret = s->dc_panel_fb_offset; |
| 1263 | break; |
| 1264 | case SM501_DC_PANEL_FB_WIDTH: |
| 1265 | ret = s->dc_panel_fb_width; |
| 1266 | break; |
| 1267 | case SM501_DC_PANEL_FB_HEIGHT: |
| 1268 | ret = s->dc_panel_fb_height; |
| 1269 | break; |
| 1270 | case SM501_DC_PANEL_TL_LOC: |
| 1271 | ret = s->dc_panel_tl_location; |
| 1272 | break; |
| 1273 | case SM501_DC_PANEL_BR_LOC: |
| 1274 | ret = s->dc_panel_br_location; |
| 1275 | break; |
| 1276 | |
| 1277 | case SM501_DC_PANEL_H_TOT: |
| 1278 | ret = s->dc_panel_h_total; |
| 1279 | break; |
| 1280 | case SM501_DC_PANEL_H_SYNC: |
| 1281 | ret = s->dc_panel_h_sync; |
| 1282 | break; |
| 1283 | case SM501_DC_PANEL_V_TOT: |
| 1284 | ret = s->dc_panel_v_total; |
| 1285 | break; |
| 1286 | case SM501_DC_PANEL_V_SYNC: |
| 1287 | ret = s->dc_panel_v_sync; |
| 1288 | break; |
| 1289 | |
| 1290 | case SM501_DC_PANEL_HWC_ADDR: |
| 1291 | ret = s->dc_panel_hwc_addr; |
| 1292 | break; |
| 1293 | case SM501_DC_PANEL_HWC_LOC: |
| 1294 | ret = s->dc_panel_hwc_location; |
| 1295 | break; |
| 1296 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
| 1297 | ret = s->dc_panel_hwc_color_1_2; |
| 1298 | break; |
| 1299 | case SM501_DC_PANEL_HWC_COLOR_3: |
| 1300 | ret = s->dc_panel_hwc_color_3; |
| 1301 | break; |
| 1302 | |
| 1303 | case SM501_DC_VIDEO_CONTROL: |
| 1304 | ret = s->dc_video_control; |
| 1305 | break; |
| 1306 | |
| 1307 | case SM501_DC_CRT_CONTROL: |
| 1308 | ret = s->dc_crt_control; |
| 1309 | break; |
| 1310 | case SM501_DC_CRT_FB_ADDR: |
| 1311 | ret = s->dc_crt_fb_addr; |
| 1312 | break; |
| 1313 | case SM501_DC_CRT_FB_OFFSET: |
| 1314 | ret = s->dc_crt_fb_offset; |
| 1315 | break; |
| 1316 | case SM501_DC_CRT_H_TOT: |
| 1317 | ret = s->dc_crt_h_total; |
| 1318 | break; |
| 1319 | case SM501_DC_CRT_H_SYNC: |
| 1320 | ret = s->dc_crt_h_sync; |
| 1321 | break; |
| 1322 | case SM501_DC_CRT_V_TOT: |
| 1323 | ret = s->dc_crt_v_total; |
| 1324 | break; |
| 1325 | case SM501_DC_CRT_V_SYNC: |
| 1326 | ret = s->dc_crt_v_sync; |
| 1327 | break; |
| 1328 | |
| 1329 | case SM501_DC_CRT_HWC_ADDR: |
| 1330 | ret = s->dc_crt_hwc_addr; |
| 1331 | break; |
| 1332 | case SM501_DC_CRT_HWC_LOC: |
| 1333 | ret = s->dc_crt_hwc_location; |
| 1334 | break; |
| 1335 | case SM501_DC_CRT_HWC_COLOR_1_2: |
| 1336 | ret = s->dc_crt_hwc_color_1_2; |
| 1337 | break; |
| 1338 | case SM501_DC_CRT_HWC_COLOR_3: |
| 1339 | ret = s->dc_crt_hwc_color_3; |
| 1340 | break; |
| 1341 | |
| 1342 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
| 1343 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
| 1344 | break; |
| 1345 | |
| 1346 | default: |
| 1347 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
| 1348 | "read. addr=%" HWADDR_PRIx "\n", addr); |
| 1349 | } |
| 1350 | trace_sm501_disp_ctrl_read((uint32_t)addr, ret); |
| 1351 | return ret; |
| 1352 | } |
| 1353 | |
| 1354 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
| 1355 | uint64_t value, unsigned size) |
| 1356 | { |
| 1357 | SM501State *s = opaque; |
| 1358 | |
| 1359 | trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); |
| 1360 | switch (addr) { |
| 1361 | case SM501_DC_PANEL_CONTROL: |
| 1362 | s->dc_panel_control = value & 0x0FFF73FF; |
| 1363 | break; |
| 1364 | case SM501_DC_PANEL_PANNING_CONTROL: |
| 1365 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
| 1366 | break; |
| 1367 | case SM501_DC_PANEL_COLOR_KEY: |
| 1368 | /* Not implemented yet */ |
| 1369 | break; |
| 1370 | case SM501_DC_PANEL_FB_ADDR: |
| 1371 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
| 1372 | if (value & 0x8000000) { |
| 1373 | qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); |
| 1374 | } |
| 1375 | s->do_full_update = true; |
| 1376 | break; |
| 1377 | case SM501_DC_PANEL_FB_OFFSET: |
| 1378 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
| 1379 | break; |
| 1380 | case SM501_DC_PANEL_FB_WIDTH: |
| 1381 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
| 1382 | break; |
| 1383 | case SM501_DC_PANEL_FB_HEIGHT: |
| 1384 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
| 1385 | break; |
| 1386 | case SM501_DC_PANEL_TL_LOC: |
| 1387 | s->dc_panel_tl_location = value & 0x07FF07FF; |
| 1388 | break; |
| 1389 | case SM501_DC_PANEL_BR_LOC: |
| 1390 | s->dc_panel_br_location = value & 0x07FF07FF; |
| 1391 | break; |
| 1392 | |
| 1393 | case SM501_DC_PANEL_H_TOT: |
| 1394 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
| 1395 | break; |
| 1396 | case SM501_DC_PANEL_H_SYNC: |
| 1397 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
| 1398 | break; |
| 1399 | case SM501_DC_PANEL_V_TOT: |
| 1400 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
| 1401 | break; |
| 1402 | case SM501_DC_PANEL_V_SYNC: |
| 1403 | s->dc_panel_v_sync = value & 0x003F0FFF; |
| 1404 | break; |
| 1405 | |
| 1406 | case SM501_DC_PANEL_HWC_ADDR: |
| 1407 | value &= 0x8FFFFFF0; |
| 1408 | if (value != s->dc_panel_hwc_addr) { |
| 1409 | hwc_invalidate(s, 0); |
| 1410 | s->dc_panel_hwc_addr = value; |
| 1411 | } |
| 1412 | break; |
| 1413 | case SM501_DC_PANEL_HWC_LOC: |
| 1414 | value &= 0x0FFF0FFF; |
| 1415 | if (value != s->dc_panel_hwc_location) { |
| 1416 | hwc_invalidate(s, 0); |
| 1417 | s->dc_panel_hwc_location = value; |
| 1418 | } |
| 1419 | break; |
| 1420 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
| 1421 | s->dc_panel_hwc_color_1_2 = value; |
| 1422 | break; |
| 1423 | case SM501_DC_PANEL_HWC_COLOR_3: |
| 1424 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
| 1425 | break; |
| 1426 | |
| 1427 | case SM501_DC_VIDEO_CONTROL: |
| 1428 | s->dc_video_control = value & 0x00037FFF; |
| 1429 | break; |
| 1430 | |
| 1431 | case SM501_DC_CRT_CONTROL: |
| 1432 | s->dc_crt_control = value & 0x0003FFFF; |
| 1433 | break; |
| 1434 | case SM501_DC_CRT_FB_ADDR: |
| 1435 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
| 1436 | if (value & 0x8000000) { |
| 1437 | qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); |
| 1438 | } |
| 1439 | s->do_full_update = true; |
| 1440 | break; |
| 1441 | case SM501_DC_CRT_FB_OFFSET: |
| 1442 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
| 1443 | break; |
| 1444 | case SM501_DC_CRT_H_TOT: |
| 1445 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
| 1446 | break; |
| 1447 | case SM501_DC_CRT_H_SYNC: |
| 1448 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
| 1449 | break; |
| 1450 | case SM501_DC_CRT_V_TOT: |
| 1451 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
| 1452 | break; |
| 1453 | case SM501_DC_CRT_V_SYNC: |
| 1454 | s->dc_crt_v_sync = value & 0x003F0FFF; |
| 1455 | break; |
| 1456 | |
| 1457 | case SM501_DC_CRT_HWC_ADDR: |
| 1458 | value &= 0x8FFFFFF0; |
| 1459 | if (value != s->dc_crt_hwc_addr) { |
| 1460 | hwc_invalidate(s, 1); |
| 1461 | s->dc_crt_hwc_addr = value; |
| 1462 | } |
| 1463 | break; |
| 1464 | case SM501_DC_CRT_HWC_LOC: |
| 1465 | value &= 0x0FFF0FFF; |
| 1466 | if (value != s->dc_crt_hwc_location) { |
| 1467 | hwc_invalidate(s, 1); |
| 1468 | s->dc_crt_hwc_location = value; |
| 1469 | } |
| 1470 | break; |
| 1471 | case SM501_DC_CRT_HWC_COLOR_1_2: |
| 1472 | s->dc_crt_hwc_color_1_2 = value; |
| 1473 | break; |
| 1474 | case SM501_DC_CRT_HWC_COLOR_3: |
| 1475 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
| 1476 | break; |
| 1477 | |
| 1478 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
| 1479 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
| 1480 | break; |
| 1481 | |
| 1482 | default: |
| 1483 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
| 1484 | "write. addr=%" HWADDR_PRIx |
| 1485 | ", val=%" PRIx64 "\n", addr, value); |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
| 1490 | .read = sm501_disp_ctrl_read, |
| 1491 | .write = sm501_disp_ctrl_write, |
| 1492 | .valid = { |
| 1493 | .min_access_size = 4, |
| 1494 | .max_access_size = 4, |
| 1495 | }, |
| 1496 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1497 | }; |
| 1498 | |
| 1499 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
| 1500 | unsigned size) |
| 1501 | { |
| 1502 | SM501State *s = opaque; |
| 1503 | uint32_t ret = 0; |
| 1504 | |
| 1505 | switch (addr) { |
| 1506 | case SM501_2D_SOURCE: |
| 1507 | ret = s->twoD_source; |
| 1508 | break; |
| 1509 | case SM501_2D_DESTINATION: |
| 1510 | ret = s->twoD_destination; |
| 1511 | break; |
| 1512 | case SM501_2D_DIMENSION: |
| 1513 | ret = s->twoD_dimension; |
| 1514 | break; |
| 1515 | case SM501_2D_CONTROL: |
| 1516 | ret = s->twoD_control; |
| 1517 | break; |
| 1518 | case SM501_2D_PITCH: |
| 1519 | ret = s->twoD_pitch; |
| 1520 | break; |
| 1521 | case SM501_2D_FOREGROUND: |
| 1522 | ret = s->twoD_foreground; |
| 1523 | break; |
| 1524 | case SM501_2D_BACKGROUND: |
| 1525 | ret = s->twoD_background; |
| 1526 | break; |
| 1527 | case SM501_2D_STRETCH: |
| 1528 | ret = s->twoD_stretch; |
| 1529 | break; |
| 1530 | case SM501_2D_COLOR_COMPARE: |
| 1531 | ret = s->twoD_color_compare; |
| 1532 | break; |
| 1533 | case SM501_2D_COLOR_COMPARE_MASK: |
| 1534 | ret = s->twoD_color_compare_mask; |
| 1535 | break; |
| 1536 | case SM501_2D_MASK: |
| 1537 | ret = s->twoD_mask; |
| 1538 | break; |
| 1539 | case SM501_2D_CLIP_TL: |
| 1540 | ret = s->twoD_clip_tl; |
| 1541 | break; |
| 1542 | case SM501_2D_CLIP_BR: |
| 1543 | ret = s->twoD_clip_br; |
| 1544 | break; |
| 1545 | case SM501_2D_MONO_PATTERN_LOW: |
| 1546 | ret = s->twoD_mono_pattern_low; |
| 1547 | break; |
| 1548 | case SM501_2D_MONO_PATTERN_HIGH: |
| 1549 | ret = s->twoD_mono_pattern_high; |
| 1550 | break; |
| 1551 | case SM501_2D_WINDOW_WIDTH: |
| 1552 | ret = s->twoD_window_width; |
| 1553 | break; |
| 1554 | case SM501_2D_SOURCE_BASE: |
| 1555 | ret = s->twoD_source_base; |
| 1556 | break; |
| 1557 | case SM501_2D_DESTINATION_BASE: |
| 1558 | ret = s->twoD_destination_base; |
| 1559 | break; |
| 1560 | case SM501_2D_ALPHA: |
| 1561 | ret = s->twoD_alpha; |
| 1562 | break; |
| 1563 | case SM501_2D_WRAP: |
| 1564 | ret = s->twoD_wrap; |
| 1565 | break; |
| 1566 | case SM501_2D_STATUS: |
| 1567 | ret = 0; /* Should return interrupt status */ |
| 1568 | break; |
| 1569 | default: |
| 1570 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
| 1571 | "read. addr=%" HWADDR_PRIx "\n", addr); |
| 1572 | } |
| 1573 | trace_sm501_2d_engine_read((uint32_t)addr, ret); |
| 1574 | return ret; |
| 1575 | } |
| 1576 | |
| 1577 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
| 1578 | uint64_t value, unsigned size) |
| 1579 | { |
| 1580 | SM501State *s = opaque; |
| 1581 | |
| 1582 | trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); |
| 1583 | switch (addr) { |
| 1584 | case SM501_2D_SOURCE: |
| 1585 | s->twoD_source = value; |
| 1586 | break; |
| 1587 | case SM501_2D_DESTINATION: |
| 1588 | s->twoD_destination = value; |
| 1589 | break; |
| 1590 | case SM501_2D_DIMENSION: |
| 1591 | s->twoD_dimension = value; |
| 1592 | break; |
| 1593 | case SM501_2D_CONTROL: |
| 1594 | s->twoD_control = value; |
| 1595 | |
| 1596 | /* do 2d operation if start flag is set. */ |
| 1597 | if (value & 0x80000000) { |
| 1598 | sm501_2d_operation(s); |
| 1599 | s->twoD_control &= ~0x80000000; /* start flag down */ |
| 1600 | } |
| 1601 | |
| 1602 | break; |
| 1603 | case SM501_2D_PITCH: |
| 1604 | s->twoD_pitch = value; |
| 1605 | break; |
| 1606 | case SM501_2D_FOREGROUND: |
| 1607 | s->twoD_foreground = value; |
| 1608 | break; |
| 1609 | case SM501_2D_BACKGROUND: |
| 1610 | s->twoD_background = value; |
| 1611 | break; |
| 1612 | case SM501_2D_STRETCH: |
| 1613 | if (((value >> 20) & 3) == 3) { |
| 1614 | value &= ~BIT(20); |
| 1615 | } |
| 1616 | s->twoD_stretch = value; |
| 1617 | break; |
| 1618 | case SM501_2D_COLOR_COMPARE: |
| 1619 | s->twoD_color_compare = value; |
| 1620 | break; |
| 1621 | case SM501_2D_COLOR_COMPARE_MASK: |
| 1622 | s->twoD_color_compare_mask = value; |
| 1623 | break; |
| 1624 | case SM501_2D_MASK: |
| 1625 | s->twoD_mask = value; |
| 1626 | break; |
| 1627 | case SM501_2D_CLIP_TL: |
| 1628 | s->twoD_clip_tl = value; |
| 1629 | break; |
| 1630 | case SM501_2D_CLIP_BR: |
| 1631 | s->twoD_clip_br = value; |
| 1632 | break; |
| 1633 | case SM501_2D_MONO_PATTERN_LOW: |
| 1634 | s->twoD_mono_pattern_low = value; |
| 1635 | break; |
| 1636 | case SM501_2D_MONO_PATTERN_HIGH: |
| 1637 | s->twoD_mono_pattern_high = value; |
| 1638 | break; |
| 1639 | case SM501_2D_WINDOW_WIDTH: |
| 1640 | s->twoD_window_width = value; |
| 1641 | break; |
| 1642 | case SM501_2D_SOURCE_BASE: |
| 1643 | s->twoD_source_base = value; |
| 1644 | break; |
| 1645 | case SM501_2D_DESTINATION_BASE: |
| 1646 | s->twoD_destination_base = value; |
| 1647 | break; |
| 1648 | case SM501_2D_ALPHA: |
| 1649 | s->twoD_alpha = value; |
| 1650 | break; |
| 1651 | case SM501_2D_WRAP: |
| 1652 | s->twoD_wrap = value; |
| 1653 | break; |
| 1654 | case SM501_2D_STATUS: |
| 1655 | /* ignored, writing 0 should clear interrupt status */ |
| 1656 | break; |
| 1657 | default: |
| 1658 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " |
| 1659 | "write. addr=%" HWADDR_PRIx |
| 1660 | ", val=%" PRIx64 "\n", addr, value); |
| 1661 | } |
| 1662 | } |
| 1663 | |
| 1664 | static const MemoryRegionOps sm501_2d_engine_ops = { |
| 1665 | .read = sm501_2d_engine_read, |
| 1666 | .write = sm501_2d_engine_write, |
| 1667 | .valid = { |
| 1668 | .min_access_size = 4, |
| 1669 | .max_access_size = 4, |
| 1670 | }, |
| 1671 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1672 | }; |
| 1673 | |
| 1674 | /* draw line functions for all console modes */ |
| 1675 | |
| 1676 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
| 1677 | int width, const uint32_t *pal); |
| 1678 | |
| 1679 | typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, |
| 1680 | int width, const uint8_t *palette, |
| 1681 | int c_x, int c_y); |
| 1682 | |
| 1683 | static void draw_line8_32(uint8_t *d, const uint8_t *s, int width, |
| 1684 | const uint32_t *pal) |
| 1685 | { |
| 1686 | uint8_t v, r, g, b; |
| 1687 | do { |
| 1688 | v = ldub_p(s); |
| 1689 | r = (pal[v] >> 16) & 0xff; |
| 1690 | g = (pal[v] >> 8) & 0xff; |
| 1691 | b = (pal[v] >> 0) & 0xff; |
| 1692 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); |
| 1693 | s++; |
| 1694 | d += 4; |
| 1695 | } while (--width != 0); |
| 1696 | } |
| 1697 | |
| 1698 | static void draw_line16_32(uint8_t *d, const uint8_t *s, int width, |
| 1699 | const uint32_t *pal) |
| 1700 | { |
| 1701 | uint16_t rgb565; |
| 1702 | uint8_t r, g, b; |
| 1703 | |
| 1704 | do { |
| 1705 | rgb565 = lduw_le_p(s); |
| 1706 | r = (rgb565 >> 8) & 0xf8; |
| 1707 | g = (rgb565 >> 3) & 0xfc; |
| 1708 | b = (rgb565 << 3) & 0xf8; |
| 1709 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); |
| 1710 | s += 2; |
| 1711 | d += 4; |
| 1712 | } while (--width != 0); |
| 1713 | } |
| 1714 | |
| 1715 | static void draw_line32_32(uint8_t *d, const uint8_t *s, int width, |
| 1716 | const uint32_t *pal) |
| 1717 | { |
| 1718 | uint8_t r, g, b; |
| 1719 | |
| 1720 | do { |
| 1721 | r = s[2]; |
| 1722 | g = s[1]; |
| 1723 | b = s[0]; |
| 1724 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); |
| 1725 | s += 4; |
| 1726 | d += 4; |
| 1727 | } while (--width != 0); |
| 1728 | } |
| 1729 | |
| 1730 | /** |
| 1731 | * Draw hardware cursor image on the given line. |
| 1732 | */ |
| 1733 | static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, |
| 1734 | const uint8_t *palette, int c_x, int c_y) |
| 1735 | { |
| 1736 | int i; |
| 1737 | uint8_t r, g, b, v, bitset = 0; |
| 1738 | |
| 1739 | /* get cursor position */ |
| 1740 | assert(0 <= c_y && c_y < SM501_HWC_HEIGHT); |
| 1741 | s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */ |
| 1742 | d += c_x * 4; |
| 1743 | |
| 1744 | for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) { |
| 1745 | /* get pixel value */ |
| 1746 | if (i % 4 == 0) { |
| 1747 | bitset = ldub_p(s); |
| 1748 | s++; |
| 1749 | } |
| 1750 | v = bitset & 3; |
| 1751 | bitset >>= 2; |
| 1752 | |
| 1753 | /* write pixel */ |
| 1754 | if (v) { |
| 1755 | v--; |
| 1756 | r = palette[v * 3 + 0]; |
| 1757 | g = palette[v * 3 + 1]; |
| 1758 | b = palette[v * 3 + 2]; |
| 1759 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); |
| 1760 | } |
| 1761 | d += 4; |
| 1762 | } |
| 1763 | } |
| 1764 | |
| 1765 | static bool sm501_update_display(void *opaque) |
| 1766 | { |
| 1767 | SM501State *s = opaque; |
| 1768 | DisplaySurface *surface = qemu_console_surface(s->con); |
| 1769 | DirtyBitmapSnapshot *snap; |
| 1770 | int y, c_x = 0, c_y = 0; |
| 1771 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
| 1772 | int width = get_width(s, crt); |
| 1773 | int height = get_height(s, crt); |
| 1774 | int src_bpp = get_bpp(s, crt); |
| 1775 | int dst_bpp = surface_bytes_per_pixel(surface); |
| 1776 | draw_line_func *draw_line = NULL; |
| 1777 | draw_hwc_line_func *draw_hwc_line = NULL; |
| 1778 | int full_update = 0; |
| 1779 | int y_start = -1; |
| 1780 | ram_addr_t offset; |
| 1781 | uint32_t *palette; |
| 1782 | uint8_t hwc_palette[3 * 3]; |
| 1783 | uint8_t *hwc_src = NULL; |
| 1784 | |
| 1785 | assert(dst_bpp == 4); /* Output is always 32-bit RGB */ |
| 1786 | |
| 1787 | if (!((crt ? s->dc_crt_control : s->dc_panel_control) |
| 1788 | & SM501_DC_CRT_CONTROL_ENABLE)) { |
| 1789 | return true; |
| 1790 | } |
| 1791 | |
| 1792 | palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - |
| 1793 | SM501_DC_PANEL_PALETTE] |
| 1794 | : &s->dc_palette[0]); |
| 1795 | |
| 1796 | /* choose draw_line function */ |
| 1797 | switch (src_bpp) { |
| 1798 | case 1: |
| 1799 | draw_line = draw_line8_32; |
| 1800 | break; |
| 1801 | case 2: |
| 1802 | draw_line = draw_line16_32; |
| 1803 | break; |
| 1804 | case 4: |
| 1805 | draw_line = draw_line32_32; |
| 1806 | break; |
| 1807 | default: |
| 1808 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" |
| 1809 | "invalid control register value.\n"); |
| 1810 | return true; |
| 1811 | } |
| 1812 | |
| 1813 | /* set up to draw hardware cursor */ |
| 1814 | if (is_hwc_enabled(s, crt)) { |
| 1815 | /* choose cursor draw line function */ |
| 1816 | draw_hwc_line = draw_hwc_line_32; |
| 1817 | hwc_src = get_hwc_address(s, crt); |
| 1818 | c_x = get_hwc_x(s, crt); |
| 1819 | c_y = get_hwc_y(s, crt); |
| 1820 | get_hwc_palette(s, crt, hwc_palette); |
| 1821 | } |
| 1822 | |
| 1823 | /* adjust console size */ |
| 1824 | if (s->last_width != width || s->last_height != height) { |
| 1825 | qemu_console_resize(s->con, width, height); |
| 1826 | surface = qemu_console_surface(s->con); |
| 1827 | s->last_width = width; |
| 1828 | s->last_height = height; |
| 1829 | full_update = 1; |
| 1830 | } |
| 1831 | |
| 1832 | /* someone else requested a full update */ |
| 1833 | if (s->do_full_update) { |
| 1834 | s->do_full_update = false; |
| 1835 | full_update = 1; |
| 1836 | } |
| 1837 | |
| 1838 | /* draw each line according to conditions */ |
| 1839 | offset = get_fb_addr(s, crt); |
| 1840 | snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, |
| 1841 | offset, width * height * src_bpp, DIRTY_MEMORY_VGA); |
| 1842 | for (y = 0; y < height; y++, offset += width * src_bpp) { |
| 1843 | int update, update_hwc; |
| 1844 | |
| 1845 | /* check if hardware cursor is enabled and we're within its range */ |
| 1846 | update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; |
| 1847 | update = full_update || update_hwc; |
| 1848 | /* check dirty flags for each line */ |
| 1849 | update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, |
| 1850 | offset, width * src_bpp); |
| 1851 | |
| 1852 | /* draw line and change status */ |
| 1853 | if (update) { |
| 1854 | uint8_t *d = surface_data(surface); |
| 1855 | d += y * width * dst_bpp; |
| 1856 | |
| 1857 | /* draw graphics layer */ |
| 1858 | draw_line(d, s->local_mem + offset, width, palette); |
| 1859 | |
| 1860 | /* draw hardware cursor */ |
| 1861 | if (update_hwc) { |
| 1862 | draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); |
| 1863 | } |
| 1864 | |
| 1865 | if (y_start < 0) { |
| 1866 | y_start = y; |
| 1867 | } |
| 1868 | } else { |
| 1869 | if (y_start >= 0) { |
| 1870 | /* flush to display */ |
| 1871 | qemu_console_update(s->con, 0, y_start, width, y - y_start); |
| 1872 | y_start = -1; |
| 1873 | } |
| 1874 | } |
| 1875 | } |
| 1876 | g_free(snap); |
| 1877 | |
| 1878 | /* complete flush to display */ |
| 1879 | if (y_start >= 0) { |
| 1880 | qemu_console_update(s->con, 0, y_start, width, y - y_start); |
| 1881 | } |
| 1882 | |
| 1883 | return true; |
| 1884 | } |
| 1885 | |
| 1886 | static const GraphicHwOps sm501_ops = { |
| 1887 | .gfx_update = sm501_update_display, |
| 1888 | }; |
| 1889 | |
| 1890 | static void sm501_reset(SM501State *s) |
| 1891 | { |
| 1892 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
| 1893 | /* |
| 1894 | * Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed |
| 1895 | * to be determined at reset by GPIO lines which set config bits. |
| 1896 | * We hardwire them: |
| 1897 | * SH = 0 : Hitachi Ready Polarity == Active Low |
| 1898 | * CDR = 0 : do not reset clock divider |
| 1899 | * TEST = 0 : Normal mode (not testing the silicon) |
| 1900 | * BUS = 0 : Hitachi SH3/SH4 |
| 1901 | */ |
| 1902 | s->misc_control = SM501_MISC_DAC_POWER; |
| 1903 | s->gpio_31_0_control = 0; |
| 1904 | s->gpio_63_32_control = 0; |
| 1905 | s->dram_control = 0; |
| 1906 | s->arbitration_control = 0x05146732; |
| 1907 | s->irq_mask = 0; |
| 1908 | s->misc_timing = 0; |
| 1909 | s->power_mode_control = 0; |
| 1910 | s->i2c_byte_count = 0; |
| 1911 | s->i2c_status = 0; |
| 1912 | s->i2c_addr = 0; |
| 1913 | memset(s->i2c_data, 0, 16); |
| 1914 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ |
| 1915 | s->dc_video_control = 0; |
| 1916 | s->dc_crt_control = 0x00010000; |
| 1917 | s->twoD_source = 0; |
| 1918 | s->twoD_destination = 0; |
| 1919 | s->twoD_dimension = 0; |
| 1920 | s->twoD_control = 0; |
| 1921 | s->twoD_pitch = 0; |
| 1922 | s->twoD_foreground = 0; |
| 1923 | s->twoD_background = 0; |
| 1924 | s->twoD_stretch = 0; |
| 1925 | s->twoD_color_compare = 0; |
| 1926 | s->twoD_color_compare_mask = 0; |
| 1927 | s->twoD_mask = 0; |
| 1928 | s->twoD_clip_tl = 0; |
| 1929 | s->twoD_clip_br = 0; |
| 1930 | s->twoD_mono_pattern_low = 0; |
| 1931 | s->twoD_mono_pattern_high = 0; |
| 1932 | s->twoD_window_width = 0; |
| 1933 | s->twoD_source_base = 0; |
| 1934 | s->twoD_destination_base = 0; |
| 1935 | s->twoD_alpha = 0; |
| 1936 | s->twoD_wrap = 0; |
| 1937 | } |
| 1938 | |
| 1939 | static void sm501_init(SM501State *s, DeviceState *dev, |
| 1940 | uint32_t local_mem_bytes) |
| 1941 | { |
| 1942 | #ifndef CONFIG_PIXMAN |
| 1943 | if (s->use_pixman != 0) { |
| 1944 | warn_report("x-pixman != 0, not effective without PIXMAN"); |
| 1945 | } |
| 1946 | #endif |
| 1947 | |
| 1948 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
| 1949 | |
| 1950 | /* local memory */ |
| 1951 | memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", |
| 1952 | get_local_mem_size(s), &error_fatal); |
| 1953 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
| 1954 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
| 1955 | |
| 1956 | /* i2c */ |
| 1957 | s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); |
| 1958 | /* ddc */ |
| 1959 | I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC)); |
| 1960 | i2c_slave_set_address(I2C_SLAVE(ddc), 0x50); |
| 1961 | qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort); |
| 1962 | |
| 1963 | /* mmio */ |
| 1964 | memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); |
| 1965 | memory_region_init_io(&s->system_config_region, OBJECT(dev), |
| 1966 | &sm501_system_config_ops, s, |
| 1967 | "sm501-system-config", 0x6c); |
| 1968 | memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, |
| 1969 | &s->system_config_region); |
| 1970 | memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, |
| 1971 | "sm501-i2c", 0x14); |
| 1972 | memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); |
| 1973 | memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), |
| 1974 | &sm501_disp_ctrl_ops, s, |
| 1975 | "sm501-disp-ctrl", 0x1000); |
| 1976 | memory_region_add_subregion(&s->mmio_region, SM501_DC, |
| 1977 | &s->disp_ctrl_region); |
| 1978 | memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), |
| 1979 | &sm501_2d_engine_ops, s, |
| 1980 | "sm501-2d-engine", 0x54); |
| 1981 | memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, |
| 1982 | &s->twoD_engine_region); |
| 1983 | |
| 1984 | /* create qemu graphic console */ |
| 1985 | s->con = qemu_graphic_console_create(dev, 0, &sm501_ops, s); |
| 1986 | } |
| 1987 | |
| 1988 | static const VMStateDescription vmstate_sm501_state = { |
| 1989 | .name = "sm501-state", |
| 1990 | .version_id = 1, |
| 1991 | .minimum_version_id = 1, |
| 1992 | .fields = (const VMStateField[]) { |
| 1993 | VMSTATE_UINT32(local_mem_size_index, SM501State), |
| 1994 | VMSTATE_UINT32(system_control, SM501State), |
| 1995 | VMSTATE_UINT32(misc_control, SM501State), |
| 1996 | VMSTATE_UINT32(gpio_31_0_control, SM501State), |
| 1997 | VMSTATE_UINT32(gpio_63_32_control, SM501State), |
| 1998 | VMSTATE_UINT32(dram_control, SM501State), |
| 1999 | VMSTATE_UINT32(arbitration_control, SM501State), |
| 2000 | VMSTATE_UINT32(irq_mask, SM501State), |
| 2001 | VMSTATE_UINT32(misc_timing, SM501State), |
| 2002 | VMSTATE_UINT32(power_mode_control, SM501State), |
| 2003 | VMSTATE_UINT32(uart0_ier, SM501State), |
| 2004 | VMSTATE_UINT32(uart0_lcr, SM501State), |
| 2005 | VMSTATE_UINT32(uart0_mcr, SM501State), |
| 2006 | VMSTATE_UINT32(uart0_scr, SM501State), |
| 2007 | VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), |
| 2008 | VMSTATE_UINT32(dc_panel_control, SM501State), |
| 2009 | VMSTATE_UINT32(dc_panel_panning_control, SM501State), |
| 2010 | VMSTATE_UINT32(dc_panel_fb_addr, SM501State), |
| 2011 | VMSTATE_UINT32(dc_panel_fb_offset, SM501State), |
| 2012 | VMSTATE_UINT32(dc_panel_fb_width, SM501State), |
| 2013 | VMSTATE_UINT32(dc_panel_fb_height, SM501State), |
| 2014 | VMSTATE_UINT32(dc_panel_tl_location, SM501State), |
| 2015 | VMSTATE_UINT32(dc_panel_br_location, SM501State), |
| 2016 | VMSTATE_UINT32(dc_panel_h_total, SM501State), |
| 2017 | VMSTATE_UINT32(dc_panel_h_sync, SM501State), |
| 2018 | VMSTATE_UINT32(dc_panel_v_total, SM501State), |
| 2019 | VMSTATE_UINT32(dc_panel_v_sync, SM501State), |
| 2020 | VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), |
| 2021 | VMSTATE_UINT32(dc_panel_hwc_location, SM501State), |
| 2022 | VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), |
| 2023 | VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), |
| 2024 | VMSTATE_UINT32(dc_video_control, SM501State), |
| 2025 | VMSTATE_UINT32(dc_crt_control, SM501State), |
| 2026 | VMSTATE_UINT32(dc_crt_fb_addr, SM501State), |
| 2027 | VMSTATE_UINT32(dc_crt_fb_offset, SM501State), |
| 2028 | VMSTATE_UINT32(dc_crt_h_total, SM501State), |
| 2029 | VMSTATE_UINT32(dc_crt_h_sync, SM501State), |
| 2030 | VMSTATE_UINT32(dc_crt_v_total, SM501State), |
| 2031 | VMSTATE_UINT32(dc_crt_v_sync, SM501State), |
| 2032 | VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), |
| 2033 | VMSTATE_UINT32(dc_crt_hwc_location, SM501State), |
| 2034 | VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), |
| 2035 | VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), |
| 2036 | VMSTATE_UINT32(twoD_source, SM501State), |
| 2037 | VMSTATE_UINT32(twoD_destination, SM501State), |
| 2038 | VMSTATE_UINT32(twoD_dimension, SM501State), |
| 2039 | VMSTATE_UINT32(twoD_control, SM501State), |
| 2040 | VMSTATE_UINT32(twoD_pitch, SM501State), |
| 2041 | VMSTATE_UINT32(twoD_foreground, SM501State), |
| 2042 | VMSTATE_UINT32(twoD_background, SM501State), |
| 2043 | VMSTATE_UINT32(twoD_stretch, SM501State), |
| 2044 | VMSTATE_UINT32(twoD_color_compare, SM501State), |
| 2045 | VMSTATE_UINT32(twoD_color_compare_mask, SM501State), |
| 2046 | VMSTATE_UINT32(twoD_mask, SM501State), |
| 2047 | VMSTATE_UINT32(twoD_clip_tl, SM501State), |
| 2048 | VMSTATE_UINT32(twoD_clip_br, SM501State), |
| 2049 | VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), |
| 2050 | VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), |
| 2051 | VMSTATE_UINT32(twoD_window_width, SM501State), |
| 2052 | VMSTATE_UINT32(twoD_source_base, SM501State), |
| 2053 | VMSTATE_UINT32(twoD_destination_base, SM501State), |
| 2054 | VMSTATE_UINT32(twoD_alpha, SM501State), |
| 2055 | VMSTATE_UINT32(twoD_wrap, SM501State), |
| 2056 | /* Added in version 2 */ |
| 2057 | VMSTATE_UINT8(i2c_byte_count, SM501State), |
| 2058 | VMSTATE_UINT8(i2c_status, SM501State), |
| 2059 | VMSTATE_UINT8(i2c_addr, SM501State), |
| 2060 | VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), |
| 2061 | VMSTATE_END_OF_LIST() |
| 2062 | } |
| 2063 | }; |
| 2064 | |
| 2065 | #define TYPE_SYSBUS_SM501 "sysbus-sm501" |
| 2066 | OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501) |
| 2067 | |
| 2068 | struct SM501SysBusState { |
| 2069 | /*< private >*/ |
| 2070 | SysBusDevice parent_obj; |
| 2071 | /*< public >*/ |
| 2072 | SM501State state; |
| 2073 | uint32_t vram_size; |
| 2074 | SerialMM serial; |
| 2075 | OHCISysBusState ohci; |
| 2076 | }; |
| 2077 | |
| 2078 | static void sm501_realize_sysbus(DeviceState *dev, Error **errp) |
| 2079 | { |
| 2080 | SM501SysBusState *s = SYSBUS_SM501(dev); |
| 2081 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 2082 | MemoryRegion *mr; |
| 2083 | |
| 2084 | sm501_init(&s->state, dev, s->vram_size); |
| 2085 | if (get_local_mem_size(&s->state) != s->vram_size) { |
| 2086 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, |
| 2087 | get_local_mem_size(&s->state)); |
| 2088 | return; |
| 2089 | } |
| 2090 | sysbus_init_mmio(sbd, &s->state.local_mem_region); |
| 2091 | sysbus_init_mmio(sbd, &s->state.mmio_region); |
| 2092 | |
| 2093 | /* bridge to usb host emulation module */ |
| 2094 | sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); |
| 2095 | memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, |
| 2096 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)); |
| 2097 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); |
| 2098 | |
| 2099 | /* bridge to serial emulation module */ |
| 2100 | sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); |
| 2101 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); |
| 2102 | memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); |
| 2103 | /* TODO : chain irq to IRL */ |
| 2104 | } |
| 2105 | |
| 2106 | static const Property sm501_sysbus_properties[] = { |
| 2107 | DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), |
| 2108 | /* this a debug option, prefer PROP_UINT over PROP_BIT for simplicity */ |
| 2109 | DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, DEFAULT_X_PIXMAN), |
| 2110 | }; |
| 2111 | |
| 2112 | static void sm501_reset_sysbus(DeviceState *dev) |
| 2113 | { |
| 2114 | SM501SysBusState *s = SYSBUS_SM501(dev); |
| 2115 | sm501_reset(&s->state); |
| 2116 | } |
| 2117 | |
| 2118 | static const VMStateDescription vmstate_sm501_sysbus = { |
| 2119 | .name = TYPE_SYSBUS_SM501, |
| 2120 | .version_id = 2, |
| 2121 | .minimum_version_id = 2, |
| 2122 | .fields = (const VMStateField[]) { |
| 2123 | VMSTATE_STRUCT(state, SM501SysBusState, 1, |
| 2124 | vmstate_sm501_state, SM501State), |
| 2125 | VMSTATE_END_OF_LIST() |
| 2126 | } |
| 2127 | }; |
| 2128 | |
| 2129 | static void sm501_sysbus_class_init(ObjectClass *klass, const void *data) |
| 2130 | { |
| 2131 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 2132 | |
| 2133 | dc->realize = sm501_realize_sysbus; |
| 2134 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
| 2135 | dc->desc = "SM501 Multimedia Companion"; |
| 2136 | device_class_set_props(dc, sm501_sysbus_properties); |
| 2137 | device_class_set_legacy_reset(dc, sm501_reset_sysbus); |
| 2138 | dc->vmsd = &vmstate_sm501_sysbus; |
| 2139 | } |
| 2140 | |
| 2141 | static void sm501_sysbus_init(Object *o) |
| 2142 | { |
| 2143 | SM501SysBusState *sm501 = SYSBUS_SM501(o); |
| 2144 | OHCISysBusState *ohci = &sm501->ohci; |
| 2145 | SerialMM *smm = &sm501->serial; |
| 2146 | |
| 2147 | object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); |
| 2148 | object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset"); |
| 2149 | qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); |
| 2150 | |
| 2151 | object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); |
| 2152 | qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); |
| 2153 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); |
| 2154 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); |
| 2155 | |
| 2156 | object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); |
| 2157 | } |
| 2158 | |
| 2159 | static const TypeInfo sm501_sysbus_info = { |
| 2160 | .name = TYPE_SYSBUS_SM501, |
| 2161 | .parent = TYPE_SYS_BUS_DEVICE, |
| 2162 | .instance_size = sizeof(SM501SysBusState), |
| 2163 | .class_init = sm501_sysbus_class_init, |
| 2164 | .instance_init = sm501_sysbus_init, |
| 2165 | }; |
| 2166 | |
| 2167 | #define TYPE_PCI_SM501 "sm501" |
| 2168 | OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501) |
| 2169 | |
| 2170 | struct SM501PCIState { |
| 2171 | /*< private >*/ |
| 2172 | PCIDevice parent_obj; |
| 2173 | /*< public >*/ |
| 2174 | SM501State state; |
| 2175 | uint32_t vram_size; |
| 2176 | }; |
| 2177 | |
| 2178 | static void sm501_realize_pci(PCIDevice *dev, Error **errp) |
| 2179 | { |
| 2180 | SM501PCIState *s = PCI_SM501(dev); |
| 2181 | |
| 2182 | sm501_init(&s->state, DEVICE(dev), s->vram_size); |
| 2183 | if (get_local_mem_size(&s->state) != s->vram_size) { |
| 2184 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, |
| 2185 | get_local_mem_size(&s->state)); |
| 2186 | return; |
| 2187 | } |
| 2188 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 2189 | &s->state.local_mem_region); |
| 2190 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 2191 | &s->state.mmio_region); |
| 2192 | } |
| 2193 | |
| 2194 | static const Property sm501_pci_properties[] = { |
| 2195 | DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), |
| 2196 | DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, DEFAULT_X_PIXMAN), |
| 2197 | }; |
| 2198 | |
| 2199 | static void sm501_reset_pci(DeviceState *dev) |
| 2200 | { |
| 2201 | SM501PCIState *s = PCI_SM501(dev); |
| 2202 | sm501_reset(&s->state); |
| 2203 | /* Bits 2:0 of misc_control register is 001 for PCI */ |
| 2204 | s->state.misc_control |= 1; |
| 2205 | } |
| 2206 | |
| 2207 | static const VMStateDescription vmstate_sm501_pci = { |
| 2208 | .name = TYPE_PCI_SM501, |
| 2209 | .version_id = 2, |
| 2210 | .minimum_version_id = 2, |
| 2211 | .fields = (const VMStateField[]) { |
| 2212 | VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), |
| 2213 | VMSTATE_STRUCT(state, SM501PCIState, 1, |
| 2214 | vmstate_sm501_state, SM501State), |
| 2215 | VMSTATE_END_OF_LIST() |
| 2216 | } |
| 2217 | }; |
| 2218 | |
| 2219 | static void sm501_pci_class_init(ObjectClass *klass, const void *data) |
| 2220 | { |
| 2221 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 2222 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 2223 | |
| 2224 | k->realize = sm501_realize_pci; |
| 2225 | k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; |
| 2226 | k->device_id = PCI_DEVICE_ID_SM501; |
| 2227 | k->class_id = PCI_CLASS_DISPLAY_OTHER; |
| 2228 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
| 2229 | dc->desc = "SM501 Display Controller"; |
| 2230 | device_class_set_props(dc, sm501_pci_properties); |
| 2231 | device_class_set_legacy_reset(dc, sm501_reset_pci); |
| 2232 | dc->hotpluggable = false; |
| 2233 | dc->vmsd = &vmstate_sm501_pci; |
| 2234 | } |
| 2235 | |
| 2236 | static void sm501_pci_init(Object *o) |
| 2237 | { |
| 2238 | object_property_set_description(o, "x-pixman", "Use pixman for: " |
| 2239 | "1: fill, 2: blit, 4: overlap blit"); |
| 2240 | } |
| 2241 | |
| 2242 | static const TypeInfo sm501_pci_info = { |
| 2243 | .name = TYPE_PCI_SM501, |
| 2244 | .parent = TYPE_PCI_DEVICE, |
| 2245 | .instance_size = sizeof(SM501PCIState), |
| 2246 | .class_init = sm501_pci_class_init, |
| 2247 | .instance_init = sm501_pci_init, |
| 2248 | .interfaces = (const InterfaceInfo[]) { |
| 2249 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 2250 | { }, |
| 2251 | }, |
| 2252 | }; |
| 2253 | |
| 2254 | static void sm501_register_types(void) |
| 2255 | { |
| 2256 | type_register_static(&sm501_sysbus_info); |
| 2257 | type_register_static(&sm501_pci_info); |
| 2258 | } |
| 2259 | |
| 2260 | type_init(sm501_register_types) |