@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 901 lines 24.7 KB
Raw
1 /*
2 * QEMU TCX Frame buffer
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/datadir.h"
27 #include "qapi/error.h"
28 #include "ui/console.h"
29 #include "ui/pixel_ops.h"
30 #include "hw/core/loader.h"
31 #include "hw/core/qdev-properties.h"
32 #include "hw/core/sysbus.h"
33 #include "migration/vmstate.h"
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qom/object.h"
37
38 #define TCX_ROM_FILE "QEMU,tcx.bin"
39 #define FCODE_MAX_ROM_SIZE 0x10000
40
41 #define MAXX 1024
42 #define MAXY 768
43 #define TCX_DAC_NREGS 16
44 #define TCX_THC_NREGS 0x1000
45 #define TCX_DHC_NREGS 0x4000
46 #define TCX_TEC_NREGS 0x1000
47 #define TCX_ALT_NREGS 0x8000
48 #define TCX_STIP_NREGS 0x800000
49 #define TCX_BLIT_NREGS 0x800000
50 #define TCX_RSTIP_NREGS 0x800000
51 #define TCX_RBLIT_NREGS 0x800000
52
53 #define TCX_THC_MISC 0x818
54 #define TCX_THC_CURSXY 0x8fc
55 #define TCX_THC_CURSMASK 0x900
56 #define TCX_THC_CURSBITS 0x980
57
58 #define TYPE_TCX "sun-tcx"
59 OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX)
60
61 struct TCXState {
62 SysBusDevice parent_obj;
63
64 QemuConsole *con;
65 qemu_irq irq;
66 uint8_t *vram;
67 uint32_t *vram24, *cplane;
68 hwaddr prom_addr;
69 MemoryRegion rom;
70 MemoryRegion vram_mem;
71 MemoryRegion vram_8bit;
72 MemoryRegion vram_24bit;
73 MemoryRegion stip;
74 MemoryRegion blit;
75 MemoryRegion vram_cplane;
76 MemoryRegion rstip;
77 MemoryRegion rblit;
78 MemoryRegion tec;
79 MemoryRegion dac;
80 MemoryRegion thc;
81 MemoryRegion dhc;
82 MemoryRegion alt;
83 MemoryRegion thc24;
84
85 ram_addr_t vram24_offset, cplane_offset;
86 uint32_t tmpblit;
87 uint32_t vram_size;
88 uint32_t palette[260];
89 uint8_t r[260], g[260], b[260];
90 uint16_t width, height, depth;
91 uint8_t dac_index, dac_state;
92 uint32_t thcmisc;
93 uint32_t cursmask[32];
94 uint32_t cursbits[32];
95 uint16_t cursx;
96 uint16_t cursy;
97 };
98
99 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
100 {
101 memory_region_set_dirty(&s->vram_mem, addr, len);
102
103 if (s->depth == 24) {
104 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
105 len * 4);
106 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
107 len * 4);
108 }
109 }
110
111 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
112 ram_addr_t addr, int len)
113 {
114 int ret;
115
116 ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len);
117
118 if (s->depth == 24) {
119 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
120 s->vram24_offset + addr * 4, len * 4);
121 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
122 s->cplane_offset + addr * 4, len * 4);
123 }
124
125 return ret;
126 }
127
128 static void update_palette_entries(TCXState *s, int start, int end)
129 {
130 int i;
131
132 for (i = start; i < end; i++) {
133 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
134 }
135 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
136 }
137
138 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
139 const uint8_t *s, int width)
140 {
141 int x;
142 uint8_t val;
143 uint32_t *p = (uint32_t *)d;
144
145 for (x = 0; x < width; x++) {
146 val = *s++;
147 *p++ = s1->palette[val];
148 }
149 }
150
151 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
152 int y, int width)
153 {
154 int x, len;
155 uint32_t mask, bits;
156 uint32_t *p = (uint32_t *)d;
157
158 y = y - s1->cursy;
159 mask = s1->cursmask[y];
160 bits = s1->cursbits[y];
161 len = MIN(width - s1->cursx, 32);
162 p = &p[s1->cursx];
163 for (x = 0; x < len; x++) {
164 if (mask & 0x80000000) {
165 if (bits & 0x80000000) {
166 *p = s1->palette[259];
167 } else {
168 *p = s1->palette[258];
169 }
170 }
171 p++;
172 mask <<= 1;
173 bits <<= 1;
174 }
175 }
176
177 /*
178 * XXX Could be much more optimal:
179 * detect if line/page/whole screen is in 24 bit mode
180 */
181 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
182 const uint8_t *s, int width,
183 const uint32_t *cplane,
184 const uint32_t *s24)
185 {
186 int x, r, g, b;
187 uint8_t val, *p8;
188 uint32_t *p = (uint32_t *)d;
189 uint32_t dval;
190 for(x = 0; x < width; x++, s++, s24++) {
191 if (be32_to_cpu(*cplane) & 0x03000000) {
192 /* 24-bit direct, BGR order */
193 p8 = (uint8_t *)s24;
194 p8++;
195 b = *p8++;
196 g = *p8++;
197 r = *p8;
198 dval = rgb_to_pixel32(r, g, b);
199 } else {
200 /* 8-bit pseudocolor */
201 val = *s;
202 dval = s1->palette[val];
203 }
204 *p++ = dval;
205 cplane++;
206 }
207 }
208
209 /* Fixed line length 1024 allows us to do nice tricks not possible on
210 VGA... */
211
212 static bool tcx_update_display(void *opaque)
213 {
214 TCXState *ts = opaque;
215 DisplaySurface *surface = qemu_console_surface(ts->con);
216 ram_addr_t page;
217 DirtyBitmapSnapshot *snap = NULL;
218 int y, y_start, dd, ds;
219 uint8_t *d, *s;
220
221 assert(surface_bits_per_pixel(surface) == 32);
222
223 page = 0;
224 y_start = -1;
225 d = surface_data(surface);
226 s = ts->vram;
227 dd = surface_stride(surface);
228 ds = 1024;
229
230 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
231 memory_region_size(&ts->vram_mem),
232 DIRTY_MEMORY_VGA);
233
234 for (y = 0; y < ts->height; y++, page += ds) {
235 if (tcx_check_dirty(ts, snap, page, ds)) {
236 if (y_start < 0)
237 y_start = y;
238
239 tcx_draw_line32(ts, d, s, ts->width);
240 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
241 tcx_draw_cursor32(ts, d, y, ts->width);
242 }
243 } else {
244 if (y_start >= 0) {
245 /* flush to display */
246 qemu_console_update(ts->con, 0, y_start, ts->width, y - y_start);
247 y_start = -1;
248 }
249 }
250 s += ds;
251 d += dd;
252 }
253 if (y_start >= 0) {
254 /* flush to display */
255 qemu_console_update(ts->con, 0, y_start, ts->width, y - y_start);
256 }
257 g_free(snap);
258 return true;
259 }
260
261 static bool tcx24_update_display(void *opaque)
262 {
263 TCXState *ts = opaque;
264 DisplaySurface *surface = qemu_console_surface(ts->con);
265 ram_addr_t page;
266 DirtyBitmapSnapshot *snap = NULL;
267 int y, y_start, dd, ds;
268 uint8_t *d, *s;
269 uint32_t *cptr, *s24;
270
271 assert(surface_bits_per_pixel(surface) == 32);
272
273 page = 0;
274 y_start = -1;
275 d = surface_data(surface);
276 s = ts->vram;
277 s24 = ts->vram24;
278 cptr = ts->cplane;
279 dd = surface_stride(surface);
280 ds = 1024;
281
282 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
283 memory_region_size(&ts->vram_mem),
284 DIRTY_MEMORY_VGA);
285
286 for (y = 0; y < ts->height; y++, page += ds) {
287 if (tcx_check_dirty(ts, snap, page, ds)) {
288 if (y_start < 0)
289 y_start = y;
290
291 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
292 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
293 tcx_draw_cursor32(ts, d, y, ts->width);
294 }
295 } else {
296 if (y_start >= 0) {
297 /* flush to display */
298 qemu_console_update(ts->con, 0, y_start, ts->width, y - y_start);
299 y_start = -1;
300 }
301 }
302 d += dd;
303 s += ds;
304 cptr += ds;
305 s24 += ds;
306 }
307 if (y_start >= 0) {
308 /* flush to display */
309 qemu_console_update(ts->con, 0, y_start, ts->width, y - y_start);
310 }
311 g_free(snap);
312 return true;
313 }
314
315 static void tcx_invalidate_display(void *opaque)
316 {
317 TCXState *s = opaque;
318
319 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
320 qemu_console_resize(s->con, s->width, s->height);
321 }
322
323 static void tcx24_invalidate_display(void *opaque)
324 {
325 TCXState *s = opaque;
326
327 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
328 qemu_console_resize(s->con, s->width, s->height);
329 }
330
331 static int vmstate_tcx_post_load(void *opaque, int version_id)
332 {
333 TCXState *s = opaque;
334
335 update_palette_entries(s, 0, 256);
336 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
337 return 0;
338 }
339
340 static const VMStateDescription vmstate_tcx = {
341 .name ="tcx",
342 .version_id = 4,
343 .minimum_version_id = 4,
344 .post_load = vmstate_tcx_post_load,
345 .fields = (const VMStateField[]) {
346 VMSTATE_UINT16(height, TCXState),
347 VMSTATE_UINT16(width, TCXState),
348 VMSTATE_UINT16(depth, TCXState),
349 VMSTATE_BUFFER(r, TCXState),
350 VMSTATE_BUFFER(g, TCXState),
351 VMSTATE_BUFFER(b, TCXState),
352 VMSTATE_UINT8(dac_index, TCXState),
353 VMSTATE_UINT8(dac_state, TCXState),
354 VMSTATE_END_OF_LIST()
355 }
356 };
357
358 static void tcx_reset(DeviceState *d)
359 {
360 TCXState *s = TCX(d);
361
362 /* Initialize palette */
363 memset(s->r, 0, 260);
364 memset(s->g, 0, 260);
365 memset(s->b, 0, 260);
366 s->r[255] = s->g[255] = s->b[255] = 255;
367 s->r[256] = s->g[256] = s->b[256] = 255;
368 s->r[258] = s->g[258] = s->b[258] = 255;
369 update_palette_entries(s, 0, 260);
370 memset(s->vram, 0, MAXX*MAXY);
371 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
372 DIRTY_MEMORY_VGA);
373 s->dac_index = 0;
374 s->dac_state = 0;
375 s->cursx = 0xf000; /* Put cursor off screen */
376 s->cursy = 0xf000;
377 }
378
379 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
380 unsigned size)
381 {
382 TCXState *s = opaque;
383 uint32_t val = 0;
384
385 switch (s->dac_state) {
386 case 0:
387 val = s->r[s->dac_index] << 24;
388 s->dac_state++;
389 break;
390 case 1:
391 val = s->g[s->dac_index] << 24;
392 s->dac_state++;
393 break;
394 case 2:
395 val = s->b[s->dac_index] << 24;
396 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
397 /* fall through */
398 default:
399 s->dac_state = 0;
400 break;
401 }
402
403 return val;
404 }
405
406 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
407 unsigned size)
408 {
409 TCXState *s = opaque;
410 unsigned index;
411
412 switch (addr) {
413 case 0: /* Address */
414 s->dac_index = val >> 24;
415 s->dac_state = 0;
416 break;
417 case 4: /* Pixel colours */
418 case 12: /* Overlay (cursor) colours */
419 if (addr & 8) {
420 index = (s->dac_index & 3) + 256;
421 } else {
422 index = s->dac_index;
423 }
424 switch (s->dac_state) {
425 case 0:
426 s->r[index] = val >> 24;
427 update_palette_entries(s, index, index + 1);
428 s->dac_state++;
429 break;
430 case 1:
431 s->g[index] = val >> 24;
432 update_palette_entries(s, index, index + 1);
433 s->dac_state++;
434 break;
435 case 2:
436 s->b[index] = val >> 24;
437 update_palette_entries(s, index, index + 1);
438 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
439 /* fall through */
440 default:
441 s->dac_state = 0;
442 break;
443 }
444 break;
445 default: /* Control registers */
446 break;
447 }
448 }
449
450 static const MemoryRegionOps tcx_dac_ops = {
451 .read = tcx_dac_readl,
452 .write = tcx_dac_writel,
453 .endianness = DEVICE_BIG_ENDIAN,
454 .valid = {
455 .min_access_size = 4,
456 .max_access_size = 4,
457 },
458 };
459
460 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
461 unsigned size)
462 {
463 return 0;
464 }
465
466 static void tcx_stip_writel(void *opaque, hwaddr addr,
467 uint64_t val, unsigned size)
468 {
469 TCXState *s = opaque;
470 int i;
471 uint32_t col;
472
473 if (!(addr & 4)) {
474 s->tmpblit = val;
475 } else {
476 addr = (addr >> 3) & 0xfffff;
477 col = cpu_to_be32(s->tmpblit);
478 if (s->depth == 24) {
479 for (i = 0; i < 32; i++) {
480 if (val & 0x80000000) {
481 s->vram[addr + i] = s->tmpblit;
482 s->vram24[addr + i] = col;
483 }
484 val <<= 1;
485 }
486 } else {
487 for (i = 0; i < 32; i++) {
488 if (val & 0x80000000) {
489 s->vram[addr + i] = s->tmpblit;
490 }
491 val <<= 1;
492 }
493 }
494 tcx_set_dirty(s, addr, 32);
495 }
496 }
497
498 static void tcx_rstip_writel(void *opaque, hwaddr addr,
499 uint64_t val, unsigned size)
500 {
501 TCXState *s = opaque;
502 int i;
503 uint32_t col;
504
505 if (!(addr & 4)) {
506 s->tmpblit = val;
507 } else {
508 addr = (addr >> 3) & 0xfffff;
509 col = cpu_to_be32(s->tmpblit);
510 if (s->depth == 24) {
511 for (i = 0; i < 32; i++) {
512 if (val & 0x80000000) {
513 s->vram[addr + i] = s->tmpblit;
514 s->vram24[addr + i] = col;
515 s->cplane[addr + i] = col;
516 }
517 val <<= 1;
518 }
519 } else {
520 for (i = 0; i < 32; i++) {
521 if (val & 0x80000000) {
522 s->vram[addr + i] = s->tmpblit;
523 }
524 val <<= 1;
525 }
526 }
527 tcx_set_dirty(s, addr, 32);
528 }
529 }
530
531 static const MemoryRegionOps tcx_stip_ops = {
532 .read = tcx_stip_readl,
533 .write = tcx_stip_writel,
534 .endianness = DEVICE_BIG_ENDIAN,
535 .impl = {
536 .min_access_size = 4,
537 .max_access_size = 4,
538 },
539 .valid = {
540 .min_access_size = 4,
541 .max_access_size = 8,
542 },
543 };
544
545 static const MemoryRegionOps tcx_rstip_ops = {
546 .read = tcx_stip_readl,
547 .write = tcx_rstip_writel,
548 .endianness = DEVICE_BIG_ENDIAN,
549 .impl = {
550 .min_access_size = 4,
551 .max_access_size = 4,
552 },
553 .valid = {
554 .min_access_size = 4,
555 .max_access_size = 8,
556 },
557 };
558
559 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
560 unsigned size)
561 {
562 return 0;
563 }
564
565 static void tcx_blit_writel(void *opaque, hwaddr addr,
566 uint64_t val, unsigned size)
567 {
568 TCXState *s = opaque;
569 uint32_t adsr, len;
570 int i;
571
572 if (!(addr & 4)) {
573 s->tmpblit = val;
574 } else {
575 addr = (addr >> 3) & 0xfffff;
576 adsr = val & 0xffffff;
577 len = ((val >> 24) & 0x1f) + 1;
578 if (adsr == 0xffffff) {
579 memset(&s->vram[addr], s->tmpblit, len);
580 if (s->depth == 24) {
581 val = s->tmpblit & 0xffffff;
582 val = cpu_to_be32(val);
583 for (i = 0; i < len; i++) {
584 s->vram24[addr + i] = val;
585 }
586 }
587 } else {
588 memcpy(&s->vram[addr], &s->vram[adsr], len);
589 if (s->depth == 24) {
590 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
591 }
592 }
593 tcx_set_dirty(s, addr, len);
594 }
595 }
596
597 static void tcx_rblit_writel(void *opaque, hwaddr addr,
598 uint64_t val, unsigned size)
599 {
600 TCXState *s = opaque;
601 uint32_t adsr, len;
602 int i;
603
604 if (!(addr & 4)) {
605 s->tmpblit = val;
606 } else {
607 addr = (addr >> 3) & 0xfffff;
608 adsr = val & 0xffffff;
609 len = ((val >> 24) & 0x1f) + 1;
610 if (adsr == 0xffffff) {
611 memset(&s->vram[addr], s->tmpblit, len);
612 if (s->depth == 24) {
613 val = s->tmpblit & 0xffffff;
614 val = cpu_to_be32(val);
615 for (i = 0; i < len; i++) {
616 s->vram24[addr + i] = val;
617 s->cplane[addr + i] = val;
618 }
619 }
620 } else {
621 memcpy(&s->vram[addr], &s->vram[adsr], len);
622 if (s->depth == 24) {
623 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
624 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
625 }
626 }
627 tcx_set_dirty(s, addr, len);
628 }
629 }
630
631 static const MemoryRegionOps tcx_blit_ops = {
632 .read = tcx_blit_readl,
633 .write = tcx_blit_writel,
634 .endianness = DEVICE_BIG_ENDIAN,
635 .impl = {
636 .min_access_size = 4,
637 .max_access_size = 4,
638 },
639 .valid = {
640 .min_access_size = 4,
641 .max_access_size = 8,
642 },
643 };
644
645 static const MemoryRegionOps tcx_rblit_ops = {
646 .read = tcx_blit_readl,
647 .write = tcx_rblit_writel,
648 .endianness = DEVICE_BIG_ENDIAN,
649 .impl = {
650 .min_access_size = 4,
651 .max_access_size = 4,
652 },
653 .valid = {
654 .min_access_size = 4,
655 .max_access_size = 8,
656 },
657 };
658
659 static void tcx_invalidate_cursor_position(TCXState *s)
660 {
661 int ymin, ymax, start, end;
662
663 /* invalidate only near the cursor */
664 ymin = s->cursy;
665 if (ymin >= s->height) {
666 return;
667 }
668 ymax = MIN(s->height, ymin + 32);
669 start = ymin * 1024;
670 end = ymax * 1024;
671
672 tcx_set_dirty(s, start, end - start);
673 }
674
675 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
676 unsigned size)
677 {
678 TCXState *s = opaque;
679 uint64_t val;
680
681 if (addr == TCX_THC_MISC) {
682 val = s->thcmisc | 0x02000000;
683 } else {
684 val = 0;
685 }
686 return val;
687 }
688
689 static void tcx_thc_writel(void *opaque, hwaddr addr,
690 uint64_t val, unsigned size)
691 {
692 TCXState *s = opaque;
693
694 if (addr == TCX_THC_CURSXY) {
695 tcx_invalidate_cursor_position(s);
696 s->cursx = val >> 16;
697 s->cursy = val;
698 tcx_invalidate_cursor_position(s);
699 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
700 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
701 tcx_invalidate_cursor_position(s);
702 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
703 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
704 tcx_invalidate_cursor_position(s);
705 } else if (addr == TCX_THC_MISC) {
706 s->thcmisc = val;
707 }
708
709 }
710
711 static const MemoryRegionOps tcx_thc_ops = {
712 .read = tcx_thc_readl,
713 .write = tcx_thc_writel,
714 .endianness = DEVICE_BIG_ENDIAN,
715 .valid = {
716 .min_access_size = 4,
717 .max_access_size = 4,
718 },
719 };
720
721 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
722 unsigned size)
723 {
724 return 0;
725 }
726
727 static void tcx_dummy_writel(void *opaque, hwaddr addr,
728 uint64_t val, unsigned size)
729 {
730 }
731
732 static const MemoryRegionOps tcx_dummy_ops = {
733 .read = tcx_dummy_readl,
734 .write = tcx_dummy_writel,
735 .endianness = DEVICE_BIG_ENDIAN,
736 .valid = {
737 .min_access_size = 4,
738 .max_access_size = 4,
739 },
740 };
741
742 static const GraphicHwOps tcx_ops = {
743 .invalidate = tcx_invalidate_display,
744 .gfx_update = tcx_update_display,
745 };
746
747 static const GraphicHwOps tcx24_ops = {
748 .invalidate = tcx24_invalidate_display,
749 .gfx_update = tcx24_update_display,
750 };
751
752 static void tcx_realize(DeviceState *dev, Error **errp)
753 {
754 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
755 TCXState *s = TCX(dev);
756 Object *obj = OBJECT(dev);
757 ram_addr_t vram_offset = 0;
758 int size, ret;
759 uint8_t *vram_base;
760 char *fcode_filename;
761
762 memory_region_init_rom(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE,
763 &error_fatal);
764 sysbus_init_mmio(sbd, &s->rom);
765
766 /* 2/STIP : Stippler */
767 memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
768 TCX_STIP_NREGS);
769 sysbus_init_mmio(sbd, &s->stip);
770
771 /* 3/BLIT : Blitter */
772 memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
773 TCX_BLIT_NREGS);
774 sysbus_init_mmio(sbd, &s->blit);
775
776 /* 5/RSTIP : Raw Stippler */
777 memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
778 TCX_RSTIP_NREGS);
779 sysbus_init_mmio(sbd, &s->rstip);
780
781 /* 6/RBLIT : Raw Blitter */
782 memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
783 TCX_RBLIT_NREGS);
784 sysbus_init_mmio(sbd, &s->rblit);
785
786 /* 7/TEC : ??? */
787 memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
788 TCX_TEC_NREGS);
789 sysbus_init_mmio(sbd, &s->tec);
790
791 /* 8/CMAP : DAC */
792 memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
793 TCX_DAC_NREGS);
794 sysbus_init_mmio(sbd, &s->dac);
795
796 /* 9/THC : Cursor */
797 memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
798 TCX_THC_NREGS);
799 sysbus_init_mmio(sbd, &s->thc);
800
801 /* 11/DHC : ??? */
802 memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
803 TCX_DHC_NREGS);
804 sysbus_init_mmio(sbd, &s->dhc);
805
806 /* 12/ALT : ??? */
807 memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
808 TCX_ALT_NREGS);
809 sysbus_init_mmio(sbd, &s->alt);
810
811 memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
812 s->vram_size * (1 + 4 + 4), &error_fatal);
813 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
814 vram_base = memory_region_get_ram_ptr(&s->vram_mem);
815
816 /* 10/ROM : FCode ROM */
817 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
818 if (fcode_filename) {
819 ret = load_image_mr(fcode_filename, &s->rom);
820 g_free(fcode_filename);
821 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
822 warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
823 }
824 }
825
826 /* 0/DFB8 : 8-bit plane */
827 s->vram = vram_base;
828 size = s->vram_size;
829 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
830 &s->vram_mem, vram_offset, size);
831 sysbus_init_mmio(sbd, &s->vram_8bit);
832 vram_offset += size;
833 vram_base += size;
834
835 /* 1/DFB24 : 24bit plane */
836 size = s->vram_size * 4;
837 s->vram24 = (uint32_t *)vram_base;
838 s->vram24_offset = vram_offset;
839 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
840 &s->vram_mem, vram_offset, size);
841 sysbus_init_mmio(sbd, &s->vram_24bit);
842 vram_offset += size;
843 vram_base += size;
844
845 /* 4/RDFB32 : Raw Framebuffer */
846 size = s->vram_size * 4;
847 s->cplane = (uint32_t *)vram_base;
848 s->cplane_offset = vram_offset;
849 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
850 &s->vram_mem, vram_offset, size);
851 sysbus_init_mmio(sbd, &s->vram_cplane);
852
853 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
854 if (s->depth == 8) {
855 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
856 "tcx.thc24", TCX_THC_NREGS);
857 sysbus_init_mmio(sbd, &s->thc24);
858 }
859
860 sysbus_init_irq(sbd, &s->irq);
861
862 if (s->depth == 8) {
863 s->con = qemu_graphic_console_create(dev, 0, &tcx_ops, s);
864 } else {
865 s->con = qemu_graphic_console_create(dev, 0, &tcx24_ops, s);
866 }
867 s->thcmisc = 0;
868
869 qemu_console_resize(s->con, s->width, s->height);
870 }
871
872 static const Property tcx_properties[] = {
873 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
874 DEFINE_PROP_UINT16("width", TCXState, width, -1),
875 DEFINE_PROP_UINT16("height", TCXState, height, -1),
876 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
877 };
878
879 static void tcx_class_init(ObjectClass *klass, const void *data)
880 {
881 DeviceClass *dc = DEVICE_CLASS(klass);
882
883 dc->realize = tcx_realize;
884 device_class_set_legacy_reset(dc, tcx_reset);
885 dc->vmsd = &vmstate_tcx;
886 device_class_set_props(dc, tcx_properties);
887 }
888
889 static const TypeInfo tcx_info = {
890 .name = TYPE_TCX,
891 .parent = TYPE_SYS_BUS_DEVICE,
892 .instance_size = sizeof(TCXState),
893 .class_init = tcx_class_init,
894 };
895
896 static void tcx_register_types(void)
897 {
898 type_register_static(&tcx_info);
899 }
900
901 type_init(tcx_register_types)