| 1 | /* |
| 2 | * Virtio GPU Device |
| 3 | * |
| 4 | * Copyright Red Hat, Inc. 2013-2014 |
| 5 | * |
| 6 | * Authors: |
| 7 | * Dave Airlie <airlied@redhat.com> |
| 8 | * Gerd Hoffmann <kraxel@redhat.com> |
| 9 | * |
| 10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 11 | * See the COPYING file in the top-level directory. |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | |
| 16 | #include "hw/virtio/virtio-gpu.h" |
| 17 | #include "migration/blocker.h" |
| 18 | #include "qapi/error.h" |
| 19 | #include "qemu/error-report.h" |
| 20 | #include "hw/display/edid.h" |
| 21 | #include "trace.h" |
| 22 | #include "qapi/qapi-types-virtio.h" |
| 23 | |
| 24 | void |
| 25 | virtio_gpu_base_reset(VirtIOGPUBase *g) |
| 26 | { |
| 27 | int i; |
| 28 | |
| 29 | g->enable = 0; |
| 30 | |
| 31 | for (i = 0; i < g->conf.max_outputs; i++) { |
| 32 | g->scanout[i].resource_id = 0; |
| 33 | g->scanout[i].width = 0; |
| 34 | g->scanout[i].height = 0; |
| 35 | g->scanout[i].x = 0; |
| 36 | g->scanout[i].y = 0; |
| 37 | g->scanout[i].ds = NULL; |
| 38 | } |
| 39 | } |
| 40 | |
| 41 | void |
| 42 | virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, |
| 43 | struct virtio_gpu_resp_display_info *dpy_info) |
| 44 | { |
| 45 | int i; |
| 46 | |
| 47 | for (i = 0; i < g->conf.max_outputs; i++) { |
| 48 | if (g->enabled_output_bitmask & (1 << i)) { |
| 49 | dpy_info->pmodes[i].enabled = 1; |
| 50 | dpy_info->pmodes[i].r.width = cpu_to_le32(g->req_state[i].width); |
| 51 | dpy_info->pmodes[i].r.height = cpu_to_le32(g->req_state[i].height); |
| 52 | } |
| 53 | } |
| 54 | } |
| 55 | |
| 56 | void |
| 57 | virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout, |
| 58 | struct virtio_gpu_resp_edid *edid) |
| 59 | { |
| 60 | size_t output_idx; |
| 61 | VirtIOGPUOutputList *node; |
| 62 | qemu_edid_info info = { |
| 63 | .width_mm = g->req_state[scanout].width_mm, |
| 64 | .height_mm = g->req_state[scanout].height_mm, |
| 65 | .prefx = g->req_state[scanout].width, |
| 66 | .prefy = g->req_state[scanout].height, |
| 67 | .refresh_rate = g->req_state[scanout].refresh_rate, |
| 68 | }; |
| 69 | |
| 70 | for (output_idx = 0, node = g->conf.outputs; |
| 71 | output_idx <= scanout && node; output_idx++, node = node->next) { |
| 72 | if (output_idx == scanout && node->value->name) { |
| 73 | info.name = node->value->name; |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | edid->size = cpu_to_le32(sizeof(edid->edid)); |
| 79 | qemu_edid_generate(edid->edid, sizeof(edid->edid), &info); |
| 80 | } |
| 81 | |
| 82 | static void virtio_gpu_invalidate_display(void *opaque) |
| 83 | { |
| 84 | } |
| 85 | |
| 86 | static bool virtio_gpu_update_display(void *opaque) |
| 87 | { |
| 88 | return true; |
| 89 | } |
| 90 | |
| 91 | static void virtio_gpu_text_update(void *opaque, uint32_t *chardata) |
| 92 | { |
| 93 | } |
| 94 | |
| 95 | static void virtio_gpu_notify_event(VirtIOGPUBase *g, uint32_t event_type) |
| 96 | { |
| 97 | g->virtio_config.events_read |= event_type; |
| 98 | virtio_notify_config(&g->parent_obj); |
| 99 | } |
| 100 | |
| 101 | static void virtio_gpu_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info) |
| 102 | { |
| 103 | VirtIOGPUBase *g = opaque; |
| 104 | |
| 105 | if (idx >= g->conf.max_outputs) { |
| 106 | return; |
| 107 | } |
| 108 | |
| 109 | g->req_state[idx].x = info->xoff; |
| 110 | g->req_state[idx].y = info->yoff; |
| 111 | g->req_state[idx].refresh_rate = info->refresh_rate; |
| 112 | g->req_state[idx].width = info->width; |
| 113 | g->req_state[idx].height = info->height; |
| 114 | g->req_state[idx].width_mm = info->width_mm; |
| 115 | g->req_state[idx].height_mm = info->height_mm; |
| 116 | |
| 117 | if (info->width && info->height) { |
| 118 | g->enabled_output_bitmask |= (1 << idx); |
| 119 | } else { |
| 120 | g->enabled_output_bitmask &= ~(1 << idx); |
| 121 | } |
| 122 | |
| 123 | /* send event to guest */ |
| 124 | virtio_gpu_notify_event(g, VIRTIO_GPU_EVENT_DISPLAY); |
| 125 | } |
| 126 | |
| 127 | static void |
| 128 | virtio_gpu_gl_flushed(void *opaque) |
| 129 | { |
| 130 | VirtIOGPUBase *g = opaque; |
| 131 | VirtIOGPUBaseClass *vgc = VIRTIO_GPU_BASE_GET_CLASS(g); |
| 132 | |
| 133 | if (vgc->gl_flushed) { |
| 134 | vgc->gl_flushed(g); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | static void |
| 139 | virtio_gpu_gl_block(void *opaque, bool block) |
| 140 | { |
| 141 | VirtIOGPUBase *g = opaque; |
| 142 | |
| 143 | if (block) { |
| 144 | g->renderer_blocked++; |
| 145 | } else { |
| 146 | g->renderer_blocked--; |
| 147 | } |
| 148 | assert(g->renderer_blocked >= 0); |
| 149 | |
| 150 | if (!block && g->renderer_blocked == 0) { |
| 151 | virtio_gpu_gl_flushed(g); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static int |
| 156 | virtio_gpu_get_flags(void *opaque) |
| 157 | { |
| 158 | VirtIOGPUBase *g = opaque; |
| 159 | int flags = GRAPHIC_FLAGS_NONE; |
| 160 | |
| 161 | if (virtio_gpu_virgl_enabled(g->conf)) { |
| 162 | flags |= GRAPHIC_FLAGS_GL; |
| 163 | } |
| 164 | |
| 165 | if (virtio_gpu_dmabuf_enabled(g->conf)) { |
| 166 | flags |= GRAPHIC_FLAGS_DMABUF; |
| 167 | } |
| 168 | |
| 169 | return flags; |
| 170 | } |
| 171 | |
| 172 | static const GraphicHwOps virtio_gpu_ops = { |
| 173 | .get_flags = virtio_gpu_get_flags, |
| 174 | .invalidate = virtio_gpu_invalidate_display, |
| 175 | .gfx_update = virtio_gpu_update_display, |
| 176 | .text_update = virtio_gpu_text_update, |
| 177 | .ui_info = virtio_gpu_ui_info, |
| 178 | .gl_block = virtio_gpu_gl_block, |
| 179 | }; |
| 180 | |
| 181 | bool |
| 182 | virtio_gpu_base_device_realize(DeviceState *qdev, |
| 183 | VirtIOHandleOutput ctrl_cb, |
| 184 | VirtIOHandleOutput cursor_cb, |
| 185 | Error **errp) |
| 186 | { |
| 187 | size_t output_idx; |
| 188 | VirtIOGPUOutputList *node; |
| 189 | VirtIODevice *vdev = VIRTIO_DEVICE(qdev); |
| 190 | VirtIOGPUBase *g = VIRTIO_GPU_BASE(qdev); |
| 191 | int i; |
| 192 | |
| 193 | if (g->conf.max_outputs > VIRTIO_GPU_MAX_SCANOUTS) { |
| 194 | error_setg(errp, "invalid max_outputs > %d", VIRTIO_GPU_MAX_SCANOUTS); |
| 195 | return false; |
| 196 | } |
| 197 | |
| 198 | g->enabled_output_bitmask = 1; |
| 199 | |
| 200 | g->req_state[0].width = g->conf.xres; |
| 201 | g->req_state[0].height = g->conf.yres; |
| 202 | |
| 203 | for (output_idx = 0, node = g->conf.outputs; |
| 204 | node; output_idx++, node = node->next) { |
| 205 | if (output_idx == g->conf.max_outputs) { |
| 206 | error_setg(errp, "invalid outputs > %d", g->conf.max_outputs); |
| 207 | return false; |
| 208 | } |
| 209 | if (node->value->name && |
| 210 | strlen(node->value->name) > EDID_NAME_MAX_LENGTH) { |
| 211 | error_setg(errp, "invalid output name '%s' > %d", |
| 212 | node->value->name, EDID_NAME_MAX_LENGTH); |
| 213 | return false; |
| 214 | } |
| 215 | if (node->value->has_xres != node->value->has_yres) { |
| 216 | error_setg(errp, |
| 217 | "must set both outputs[%zd].xres and outputs[%zd].yres", |
| 218 | output_idx, output_idx); |
| 219 | return false; |
| 220 | } |
| 221 | if (node->value->has_xres && node->value->has_yres) { |
| 222 | g->enabled_output_bitmask |= (1 << output_idx); |
| 223 | g->req_state[output_idx].width = node->value->xres; |
| 224 | g->req_state[output_idx].height = node->value->yres; |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | if (virtio_gpu_virgl_enabled(g->conf)) { |
| 229 | error_setg(&g->migration_blocker, "virgl is not yet migratable"); |
| 230 | if (migrate_add_blocker(&g->migration_blocker, errp) < 0) { |
| 231 | return false; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | g->virtio_config.num_scanouts = cpu_to_le32(g->conf.max_outputs); |
| 236 | virtio_init(VIRTIO_DEVICE(g), VIRTIO_ID_GPU, |
| 237 | sizeof(struct virtio_gpu_config)); |
| 238 | |
| 239 | if (virtio_gpu_virgl_enabled(g->conf)) { |
| 240 | /* use larger control queue in 3d mode */ |
| 241 | virtio_add_queue(vdev, 256, ctrl_cb); |
| 242 | virtio_add_queue(vdev, 16, cursor_cb); |
| 243 | } else { |
| 244 | virtio_add_queue(vdev, 64, ctrl_cb); |
| 245 | virtio_add_queue(vdev, 16, cursor_cb); |
| 246 | } |
| 247 | |
| 248 | g->hw_ops = &virtio_gpu_ops; |
| 249 | for (i = 0; i < g->conf.max_outputs; i++) { |
| 250 | g->scanout[i].con = |
| 251 | qemu_graphic_console_create(DEVICE(g), i, &virtio_gpu_ops, g); |
| 252 | } |
| 253 | |
| 254 | return true; |
| 255 | } |
| 256 | |
| 257 | static uint64_t |
| 258 | virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features, |
| 259 | Error **errp) |
| 260 | { |
| 261 | VirtIOGPUBase *g = VIRTIO_GPU_BASE(vdev); |
| 262 | |
| 263 | if (virtio_gpu_virgl_enabled(g->conf) || |
| 264 | virtio_gpu_rutabaga_enabled(g->conf)) { |
| 265 | features |= (1 << VIRTIO_GPU_F_VIRGL); |
| 266 | } |
| 267 | if (virtio_gpu_edid_enabled(g->conf)) { |
| 268 | features |= (1 << VIRTIO_GPU_F_EDID); |
| 269 | } |
| 270 | if (virtio_gpu_blob_enabled(g->conf)) { |
| 271 | features |= (1 << VIRTIO_GPU_F_RESOURCE_BLOB); |
| 272 | } |
| 273 | if (virtio_gpu_context_init_enabled(g->conf)) { |
| 274 | features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT); |
| 275 | } |
| 276 | if (virtio_gpu_resource_uuid_enabled(g->conf)) { |
| 277 | features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID); |
| 278 | } |
| 279 | |
| 280 | return features; |
| 281 | } |
| 282 | |
| 283 | static void |
| 284 | virtio_gpu_base_set_features(VirtIODevice *vdev, uint64_t features) |
| 285 | { |
| 286 | static const uint32_t virgl = (1 << VIRTIO_GPU_F_VIRGL); |
| 287 | |
| 288 | trace_virtio_gpu_features(((features & virgl) == virgl)); |
| 289 | } |
| 290 | |
| 291 | void |
| 292 | virtio_gpu_base_device_unrealize(DeviceState *qdev) |
| 293 | { |
| 294 | VirtIOGPUBase *g = VIRTIO_GPU_BASE(qdev); |
| 295 | VirtIODevice *vdev = VIRTIO_DEVICE(qdev); |
| 296 | |
| 297 | virtio_del_queue(vdev, 0); |
| 298 | virtio_del_queue(vdev, 1); |
| 299 | virtio_cleanup(vdev); |
| 300 | migrate_del_blocker(&g->migration_blocker); |
| 301 | } |
| 302 | |
| 303 | static void |
| 304 | virtio_gpu_base_class_init(ObjectClass *klass, const void *data) |
| 305 | { |
| 306 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 307 | VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); |
| 308 | |
| 309 | vdc->unrealize = virtio_gpu_base_device_unrealize; |
| 310 | vdc->get_features = virtio_gpu_base_get_features; |
| 311 | vdc->set_features = virtio_gpu_base_set_features; |
| 312 | |
| 313 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
| 314 | dc->hotpluggable = false; |
| 315 | } |
| 316 | |
| 317 | static const TypeInfo virtio_gpu_base_info = { |
| 318 | .name = TYPE_VIRTIO_GPU_BASE, |
| 319 | .parent = TYPE_VIRTIO_DEVICE, |
| 320 | .instance_size = sizeof(VirtIOGPUBase), |
| 321 | .class_size = sizeof(VirtIOGPUBaseClass), |
| 322 | .class_init = virtio_gpu_base_class_init, |
| 323 | .abstract = true |
| 324 | }; |
| 325 | module_obj(TYPE_VIRTIO_GPU_BASE); |
| 326 | module_kconfig(VIRTIO_GPU); |
| 327 | |
| 328 | static void |
| 329 | virtio_register_types(void) |
| 330 | { |
| 331 | type_register_static(&virtio_gpu_base_info); |
| 332 | } |
| 333 | |
| 334 | type_init(virtio_register_types) |
| 335 | |
| 336 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctrl_hdr) != 24); |
| 337 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_update_cursor) != 56); |
| 338 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_unref) != 32); |
| 339 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_2d) != 40); |
| 340 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_set_scanout) != 48); |
| 341 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_flush) != 48); |
| 342 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_to_host_2d) != 56); |
| 343 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_mem_entry) != 16); |
| 344 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_attach_backing) != 32); |
| 345 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_detach_backing) != 32); |
| 346 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_display_info) != 408); |
| 347 | |
| 348 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_host_3d) != 72); |
| 349 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_3d) != 72); |
| 350 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_create) != 96); |
| 351 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_destroy) != 24); |
| 352 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_resource) != 32); |
| 353 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_cmd_submit) != 32); |
| 354 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset_info) != 32); |
| 355 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset_info) != 40); |
| 356 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset) != 32); |
| 357 | QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset) != 24); |