| 1 | /* |
| 2 | * QEMU DMA emulation |
| 3 | * |
| 4 | * Copyright (c) 2003-2004 Vassili Karpov (malc) |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/isa/isa.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "migration/vmstate.h" |
| 29 | #include "hw/dma/i8257.h" |
| 30 | #include "exec/cpu-common.h" |
| 31 | #include "system/physmem.h" |
| 32 | #include "qapi/error.h" |
| 33 | #include "qemu/main-loop.h" |
| 34 | #include "qemu/module.h" |
| 35 | #include "qemu/log.h" |
| 36 | #include "trace.h" |
| 37 | |
| 38 | |
| 39 | /* #define DEBUG_DMA */ |
| 40 | |
| 41 | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
| 42 | #ifdef DEBUG_DMA |
| 43 | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
| 44 | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
| 45 | #else |
| 46 | #define linfo(...) |
| 47 | #define ldebug(...) |
| 48 | #endif |
| 49 | |
| 50 | #define ADDR 0 |
| 51 | #define COUNT 1 |
| 52 | |
| 53 | enum { |
| 54 | CMD_MEMORY_TO_MEMORY = 0x01, |
| 55 | CMD_FIXED_ADDRESS = 0x02, |
| 56 | CMD_BLOCK_CONTROLLER = 0x04, |
| 57 | CMD_COMPRESSED_TIME = 0x08, |
| 58 | CMD_CYCLIC_PRIORITY = 0x10, |
| 59 | CMD_EXTENDED_WRITE = 0x20, |
| 60 | CMD_LOW_DREQ = 0x40, |
| 61 | CMD_LOW_DACK = 0x80, |
| 62 | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
| 63 | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
| 64 | | CMD_LOW_DREQ | CMD_LOW_DACK |
| 65 | |
| 66 | }; |
| 67 | |
| 68 | static void i8257_dma_run(void *opaque); |
| 69 | |
| 70 | static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
| 71 | |
| 72 | static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data) |
| 73 | { |
| 74 | I8257State *d = opaque; |
| 75 | int ichan; |
| 76 | |
| 77 | ichan = channels[nport & 7]; |
| 78 | if (-1 == ichan) { |
| 79 | dolog ("invalid channel %#x %#x\n", nport, data); |
| 80 | return; |
| 81 | } |
| 82 | d->regs[ichan].page = data; |
| 83 | } |
| 84 | |
| 85 | static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data) |
| 86 | { |
| 87 | I8257State *d = opaque; |
| 88 | int ichan; |
| 89 | |
| 90 | ichan = channels[nport & 7]; |
| 91 | if (-1 == ichan) { |
| 92 | dolog ("invalid channel %#x %#x\n", nport, data); |
| 93 | return; |
| 94 | } |
| 95 | d->regs[ichan].pageh = data; |
| 96 | } |
| 97 | |
| 98 | static uint32_t i8257_read_page(void *opaque, uint32_t nport) |
| 99 | { |
| 100 | I8257State *d = opaque; |
| 101 | int ichan; |
| 102 | |
| 103 | ichan = channels[nport & 7]; |
| 104 | if (-1 == ichan) { |
| 105 | dolog ("invalid channel read %#x\n", nport); |
| 106 | return 0; |
| 107 | } |
| 108 | return d->regs[ichan].page; |
| 109 | } |
| 110 | |
| 111 | static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) |
| 112 | { |
| 113 | I8257State *d = opaque; |
| 114 | int ichan; |
| 115 | |
| 116 | ichan = channels[nport & 7]; |
| 117 | if (-1 == ichan) { |
| 118 | dolog ("invalid channel read %#x\n", nport); |
| 119 | return 0; |
| 120 | } |
| 121 | return d->regs[ichan].pageh; |
| 122 | } |
| 123 | |
| 124 | static inline void i8257_init_chan(I8257State *d, int ichan) |
| 125 | { |
| 126 | I8257Regs *r; |
| 127 | |
| 128 | r = d->regs + ichan; |
| 129 | r->now[ADDR] = r->base[ADDR] << d->dshift; |
| 130 | r->now[COUNT] = 0; |
| 131 | } |
| 132 | |
| 133 | static inline int i8257_getff(I8257State *d) |
| 134 | { |
| 135 | int ff; |
| 136 | |
| 137 | ff = d->flip_flop; |
| 138 | d->flip_flop = !ff; |
| 139 | return ff; |
| 140 | } |
| 141 | |
| 142 | static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size) |
| 143 | { |
| 144 | I8257State *d = opaque; |
| 145 | int ichan, nreg, iport, ff, val, dir; |
| 146 | I8257Regs *r; |
| 147 | |
| 148 | iport = (nport >> d->dshift) & 0x0f; |
| 149 | ichan = iport >> 1; |
| 150 | nreg = iport & 1; |
| 151 | r = d->regs + ichan; |
| 152 | |
| 153 | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
| 154 | ff = i8257_getff(d); |
| 155 | if (nreg) |
| 156 | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
| 157 | else |
| 158 | val = r->now[ADDR] + r->now[COUNT] * dir; |
| 159 | |
| 160 | ldebug ("read_chan %#x -> %d\n", iport, val); |
| 161 | return (val >> (d->dshift + (ff << 3))) & 0xff; |
| 162 | } |
| 163 | |
| 164 | static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, |
| 165 | unsigned int size) |
| 166 | { |
| 167 | I8257State *d = opaque; |
| 168 | int iport, ichan, nreg; |
| 169 | I8257Regs *r; |
| 170 | |
| 171 | iport = (nport >> d->dshift) & 0x0f; |
| 172 | ichan = iport >> 1; |
| 173 | nreg = iport & 1; |
| 174 | r = d->regs + ichan; |
| 175 | if (i8257_getff(d)) { |
| 176 | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
| 177 | i8257_init_chan(d, ichan); |
| 178 | } else { |
| 179 | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, |
| 184 | unsigned int size) |
| 185 | { |
| 186 | I8257State *d = opaque; |
| 187 | int iport, ichan = 0; |
| 188 | |
| 189 | iport = (nport >> d->dshift) & 0x0f; |
| 190 | switch (iport) { |
| 191 | case 0x00: /* command */ |
| 192 | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
| 193 | qemu_log_mask(LOG_UNIMP, "%s: cmd 0x%02"PRIx64" not supported\n", |
| 194 | __func__, data); |
| 195 | return; |
| 196 | } |
| 197 | d->command = data; |
| 198 | break; |
| 199 | |
| 200 | case 0x01: |
| 201 | ichan = data & 3; |
| 202 | if (data & 4) { |
| 203 | d->status |= 1 << (ichan + 4); |
| 204 | } |
| 205 | else { |
| 206 | d->status &= ~(1 << (ichan + 4)); |
| 207 | } |
| 208 | d->status &= ~(1 << ichan); |
| 209 | i8257_dma_run(d); |
| 210 | break; |
| 211 | |
| 212 | case 0x02: /* single mask */ |
| 213 | if (data & 4) |
| 214 | d->mask |= 1 << (data & 3); |
| 215 | else |
| 216 | d->mask &= ~(1 << (data & 3)); |
| 217 | i8257_dma_run(d); |
| 218 | break; |
| 219 | |
| 220 | case 0x03: /* mode */ |
| 221 | { |
| 222 | ichan = data & 3; |
| 223 | #ifdef DEBUG_DMA |
| 224 | { |
| 225 | int op, ai, dir, opmode; |
| 226 | op = (data >> 2) & 3; |
| 227 | ai = (data >> 4) & 1; |
| 228 | dir = (data >> 5) & 1; |
| 229 | opmode = (data >> 6) & 3; |
| 230 | |
| 231 | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", |
| 232 | ichan, op, ai, dir, opmode); |
| 233 | } |
| 234 | #endif |
| 235 | d->regs[ichan].mode = data; |
| 236 | break; |
| 237 | } |
| 238 | |
| 239 | case 0x04: /* clear flip flop */ |
| 240 | d->flip_flop = 0; |
| 241 | break; |
| 242 | |
| 243 | case 0x05: /* reset */ |
| 244 | d->flip_flop = 0; |
| 245 | d->mask = ~0; |
| 246 | d->status = 0; |
| 247 | d->command = 0; |
| 248 | break; |
| 249 | |
| 250 | case 0x06: /* clear mask for all channels */ |
| 251 | d->mask = 0; |
| 252 | i8257_dma_run(d); |
| 253 | break; |
| 254 | |
| 255 | case 0x07: /* write mask for all channels */ |
| 256 | d->mask = data; |
| 257 | i8257_dma_run(d); |
| 258 | break; |
| 259 | |
| 260 | default: |
| 261 | dolog ("unknown iport %#x\n", iport); |
| 262 | break; |
| 263 | } |
| 264 | |
| 265 | #ifdef DEBUG_DMA |
| 266 | if (0xc != iport) { |
| 267 | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", |
| 268 | nport, ichan, data); |
| 269 | } |
| 270 | #endif |
| 271 | } |
| 272 | |
| 273 | static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size) |
| 274 | { |
| 275 | I8257State *d = opaque; |
| 276 | int iport, val; |
| 277 | |
| 278 | iport = (nport >> d->dshift) & 0x0f; |
| 279 | switch (iport) { |
| 280 | case 0x00: /* status */ |
| 281 | val = d->status; |
| 282 | d->status &= 0xf0; |
| 283 | break; |
| 284 | case 0x01: /* mask */ |
| 285 | val = d->mask; |
| 286 | break; |
| 287 | default: |
| 288 | val = 0; |
| 289 | break; |
| 290 | } |
| 291 | |
| 292 | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); |
| 293 | return val; |
| 294 | } |
| 295 | |
| 296 | static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan) |
| 297 | { |
| 298 | I8257State *d = I8257(obj); |
| 299 | return (d->regs[nchan & 3].mode >> 4) & 1; |
| 300 | } |
| 301 | |
| 302 | static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan) |
| 303 | { |
| 304 | I8257State *d = I8257(obj); |
| 305 | int ichan; |
| 306 | |
| 307 | ichan = nchan & 3; |
| 308 | d->status |= 1 << (ichan + 4); |
| 309 | i8257_dma_run(d); |
| 310 | } |
| 311 | |
| 312 | static void i8257_dma_release_DREQ(IsaDma *obj, int nchan) |
| 313 | { |
| 314 | I8257State *d = I8257(obj); |
| 315 | int ichan; |
| 316 | |
| 317 | ichan = nchan & 3; |
| 318 | d->status &= ~(1 << (ichan + 4)); |
| 319 | i8257_dma_run(d); |
| 320 | } |
| 321 | |
| 322 | static void i8257_channel_run(I8257State *d, int ichan) |
| 323 | { |
| 324 | int ncont = d->dshift; |
| 325 | int n; |
| 326 | I8257Regs *r = &d->regs[ichan]; |
| 327 | #ifdef DEBUG_DMA |
| 328 | int dir, opmode; |
| 329 | |
| 330 | dir = (r->mode >> 5) & 1; |
| 331 | opmode = (r->mode >> 6) & 3; |
| 332 | |
| 333 | if (dir) { |
| 334 | dolog ("DMA in address decrement mode\n"); |
| 335 | } |
| 336 | if (opmode != 1) { |
| 337 | dolog ("DMA not in single mode select %#x\n", opmode); |
| 338 | } |
| 339 | #endif |
| 340 | |
| 341 | n = r->transfer_handler (r->opaque, ichan + (ncont << 2), |
| 342 | r->now[COUNT], (r->base[COUNT] + 1) << ncont); |
| 343 | r->now[COUNT] = n; |
| 344 | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
| 345 | if (n == (r->base[COUNT] + 1) << ncont) { |
| 346 | ldebug("transfer done\n"); |
| 347 | d->status |= (1 << ichan); |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | static void i8257_dma_run(void *opaque) |
| 352 | { |
| 353 | I8257State *d = opaque; |
| 354 | int ichan; |
| 355 | int rearm = 0; |
| 356 | |
| 357 | if (d->running) { |
| 358 | rearm = 1; |
| 359 | goto out; |
| 360 | } else { |
| 361 | d->running = 1; |
| 362 | } |
| 363 | |
| 364 | for (ichan = 0; ichan < 4; ichan++) { |
| 365 | int mask; |
| 366 | |
| 367 | mask = 1 << ichan; |
| 368 | |
| 369 | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
| 370 | i8257_channel_run(d, ichan); |
| 371 | rearm = 1; |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | d->running = 0; |
| 376 | out: |
| 377 | if (rearm) { |
| 378 | qemu_bh_schedule_idle(d->dma_bh); |
| 379 | d->dma_bh_scheduled = true; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static void i8257_dma_register_channel(IsaDma *obj, int nchan, |
| 384 | IsaDmaTransferHandler transfer_handler, |
| 385 | void *opaque) |
| 386 | { |
| 387 | I8257State *d = I8257(obj); |
| 388 | I8257Regs *r; |
| 389 | int ichan; |
| 390 | |
| 391 | ichan = nchan & 3; |
| 392 | |
| 393 | r = d->regs + ichan; |
| 394 | r->transfer_handler = transfer_handler; |
| 395 | r->opaque = opaque; |
| 396 | } |
| 397 | |
| 398 | static bool i8257_is_verify_transfer(I8257Regs *r) |
| 399 | { |
| 400 | return (r->mode & 0x0c) == 0; |
| 401 | } |
| 402 | |
| 403 | static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos, |
| 404 | int len) |
| 405 | { |
| 406 | I8257State *d = I8257(obj); |
| 407 | I8257Regs *r = &d->regs[nchan & 3]; |
| 408 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
| 409 | |
| 410 | if (i8257_is_verify_transfer(r)) { |
| 411 | /* |
| 412 | * If the device is expecting this verify operation then |
| 413 | * it won't care about the nonexistent data. But if it |
| 414 | * is expecting a real read (i.e. the guest has misprogrammed |
| 415 | * the DMA controller and the device) it's going to try to do |
| 416 | * something with the buffer contents. Give it zeroes. |
| 417 | * (It's not clear whether this is exactly what happens if |
| 418 | * you do this on real hardware. In practice no device QEMU |
| 419 | * emulates has a use for verify on a memory-read transfer, |
| 420 | * so we don't care beyond avoiding the guest being able to |
| 421 | * trigger the caller reading uninitialized data.) |
| 422 | */ |
| 423 | memset(buf, 0, len); |
| 424 | return len; |
| 425 | } |
| 426 | |
| 427 | if (r->mode & 0x20) { |
| 428 | int i; |
| 429 | uint8_t *p = buf; |
| 430 | |
| 431 | physical_memory_read(addr - pos - len, buf, len); |
| 432 | /* What about 16bit transfers? */ |
| 433 | for (i = 0; i < len >> 1; i++) { |
| 434 | uint8_t b = p[len - i - 1]; |
| 435 | p[i] = b; |
| 436 | } |
| 437 | } |
| 438 | else |
| 439 | physical_memory_read(addr + pos, buf, len); |
| 440 | |
| 441 | return len; |
| 442 | } |
| 443 | |
| 444 | static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos, |
| 445 | int len) |
| 446 | { |
| 447 | I8257State *s = I8257(obj); |
| 448 | I8257Regs *r = &s->regs[nchan & 3]; |
| 449 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
| 450 | |
| 451 | if (i8257_is_verify_transfer(r)) { |
| 452 | return len; |
| 453 | } |
| 454 | |
| 455 | if (r->mode & 0x20) { |
| 456 | int i; |
| 457 | uint8_t *p = buf; |
| 458 | |
| 459 | physical_memory_write(addr - pos - len, buf, len); |
| 460 | /* What about 16bit transfers? */ |
| 461 | for (i = 0; i < len; i++) { |
| 462 | uint8_t b = p[len - i - 1]; |
| 463 | p[i] = b; |
| 464 | } |
| 465 | } |
| 466 | else |
| 467 | physical_memory_write(addr + pos, buf, len); |
| 468 | |
| 469 | return len; |
| 470 | } |
| 471 | |
| 472 | /* request the emulator to transfer a new DMA memory block ASAP (even |
| 473 | * if the idle bottom half would not have exited the iothread yet). |
| 474 | */ |
| 475 | static void i8257_dma_schedule(IsaDma *obj) |
| 476 | { |
| 477 | I8257State *d = I8257(obj); |
| 478 | if (d->dma_bh_scheduled) { |
| 479 | qemu_notify_event(); |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | static void i8257_reset(DeviceState *dev) |
| 484 | { |
| 485 | I8257State *d = I8257(dev); |
| 486 | i8257_write_cont(d, (0x05 << d->dshift), 0, 1); |
| 487 | } |
| 488 | |
| 489 | static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, |
| 490 | int dma_len) |
| 491 | { |
| 492 | trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); |
| 493 | return dma_pos; |
| 494 | } |
| 495 | |
| 496 | |
| 497 | static const MemoryRegionOps channel_io_ops = { |
| 498 | .read = i8257_read_chan, |
| 499 | .write = i8257_write_chan, |
| 500 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 501 | .impl = { |
| 502 | .min_access_size = 1, |
| 503 | .max_access_size = 1, |
| 504 | }, |
| 505 | }; |
| 506 | |
| 507 | /* IOport from page_base */ |
| 508 | static const MemoryRegionPortio page_portio_list[] = { |
| 509 | { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, }, |
| 510 | { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, }, |
| 511 | PORTIO_END_OF_LIST(), |
| 512 | }; |
| 513 | |
| 514 | /* IOport from pageh_base */ |
| 515 | static const MemoryRegionPortio pageh_portio_list[] = { |
| 516 | { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, |
| 517 | { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, |
| 518 | PORTIO_END_OF_LIST(), |
| 519 | }; |
| 520 | |
| 521 | static const MemoryRegionOps cont_io_ops = { |
| 522 | .read = i8257_read_cont, |
| 523 | .write = i8257_write_cont, |
| 524 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 525 | .impl = { |
| 526 | .min_access_size = 1, |
| 527 | .max_access_size = 1, |
| 528 | }, |
| 529 | }; |
| 530 | |
| 531 | static const VMStateDescription vmstate_i8257_regs = { |
| 532 | .name = "dma_regs", |
| 533 | .version_id = 1, |
| 534 | .minimum_version_id = 1, |
| 535 | .fields = (const VMStateField[]) { |
| 536 | VMSTATE_INT32_ARRAY(now, I8257Regs, 2), |
| 537 | VMSTATE_UINT16_ARRAY(base, I8257Regs, 2), |
| 538 | VMSTATE_UINT8(mode, I8257Regs), |
| 539 | VMSTATE_UINT8(page, I8257Regs), |
| 540 | VMSTATE_UINT8(pageh, I8257Regs), |
| 541 | VMSTATE_UINT8(dack, I8257Regs), |
| 542 | VMSTATE_UINT8(eop, I8257Regs), |
| 543 | VMSTATE_END_OF_LIST() |
| 544 | } |
| 545 | }; |
| 546 | |
| 547 | static int i8257_post_load(void *opaque, int version_id) |
| 548 | { |
| 549 | I8257State *d = opaque; |
| 550 | i8257_dma_run(d); |
| 551 | |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | static const VMStateDescription vmstate_i8257 = { |
| 556 | .name = "dma", |
| 557 | .version_id = 1, |
| 558 | .minimum_version_id = 1, |
| 559 | .post_load = i8257_post_load, |
| 560 | .fields = (const VMStateField[]) { |
| 561 | VMSTATE_UINT8(command, I8257State), |
| 562 | VMSTATE_UINT8(mask, I8257State), |
| 563 | VMSTATE_UINT8(flip_flop, I8257State), |
| 564 | VMSTATE_INT32(dshift, I8257State), |
| 565 | VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs, |
| 566 | I8257Regs), |
| 567 | VMSTATE_END_OF_LIST() |
| 568 | } |
| 569 | }; |
| 570 | |
| 571 | static void i8257_realize(DeviceState *dev, Error **errp) |
| 572 | { |
| 573 | ISADevice *isa = ISA_DEVICE(dev); |
| 574 | I8257State *d = I8257(dev); |
| 575 | int i; |
| 576 | |
| 577 | memory_region_init_io(&d->channel_io, OBJECT(dev), &channel_io_ops, d, |
| 578 | "dma-chan", 8 << d->dshift); |
| 579 | memory_region_add_subregion(isa_address_space_io(isa), |
| 580 | d->base, &d->channel_io); |
| 581 | |
| 582 | isa_register_portio_list(isa, &d->portio_page, |
| 583 | d->page_base, page_portio_list, d, |
| 584 | "dma-page"); |
| 585 | if (d->pageh_base >= 0) { |
| 586 | isa_register_portio_list(isa, &d->portio_pageh, |
| 587 | d->pageh_base, pageh_portio_list, d, |
| 588 | "dma-pageh"); |
| 589 | } |
| 590 | |
| 591 | memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d, |
| 592 | "dma-cont", 8 << d->dshift); |
| 593 | memory_region_add_subregion(isa_address_space_io(isa), |
| 594 | d->base + (8 << d->dshift), &d->cont_io); |
| 595 | |
| 596 | for (i = 0; i < ARRAY_SIZE(d->regs); ++i) { |
| 597 | d->regs[i].transfer_handler = i8257_phony_handler; |
| 598 | } |
| 599 | |
| 600 | d->dma_bh = qemu_bh_new(i8257_dma_run, d); |
| 601 | } |
| 602 | |
| 603 | static const Property i8257_properties[] = { |
| 604 | DEFINE_PROP_INT32("base", I8257State, base, 0x00), |
| 605 | DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), |
| 606 | DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), |
| 607 | DEFINE_PROP_INT32("dshift", I8257State, dshift, 0), |
| 608 | }; |
| 609 | |
| 610 | static void i8257_class_init(ObjectClass *klass, const void *data) |
| 611 | { |
| 612 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 613 | IsaDmaClass *idc = ISADMA_CLASS(klass); |
| 614 | |
| 615 | dc->realize = i8257_realize; |
| 616 | device_class_set_legacy_reset(dc, i8257_reset); |
| 617 | dc->vmsd = &vmstate_i8257; |
| 618 | device_class_set_props(dc, i8257_properties); |
| 619 | |
| 620 | idc->has_autoinitialization = i8257_dma_has_autoinitialization; |
| 621 | idc->read_memory = i8257_dma_read_memory; |
| 622 | idc->write_memory = i8257_dma_write_memory; |
| 623 | idc->hold_DREQ = i8257_dma_hold_DREQ; |
| 624 | idc->release_DREQ = i8257_dma_release_DREQ; |
| 625 | idc->schedule = i8257_dma_schedule; |
| 626 | idc->register_channel = i8257_dma_register_channel; |
| 627 | /* Reason: needs to be wired up by isa_bus_dma() to work */ |
| 628 | dc->user_creatable = false; |
| 629 | } |
| 630 | |
| 631 | static const TypeInfo i8257_info = { |
| 632 | .name = TYPE_I8257, |
| 633 | .parent = TYPE_ISA_DEVICE, |
| 634 | .instance_size = sizeof(I8257State), |
| 635 | .class_init = i8257_class_init, |
| 636 | .interfaces = (const InterfaceInfo[]) { |
| 637 | { TYPE_ISADMA }, |
| 638 | { } |
| 639 | } |
| 640 | }; |
| 641 | |
| 642 | static void i8257_register_types(void) |
| 643 | { |
| 644 | type_register_static(&i8257_info); |
| 645 | } |
| 646 | |
| 647 | type_init(i8257_register_types) |
| 648 | |
| 649 | void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable) |
| 650 | { |
| 651 | ISADevice *isa1, *isa2; |
| 652 | DeviceState *d; |
| 653 | |
| 654 | isa1 = isa_new(TYPE_I8257); |
| 655 | object_property_add_child(parent, "dma[*]", OBJECT(isa1)); |
| 656 | d = DEVICE(isa1); |
| 657 | qdev_prop_set_int32(d, "base", 0x00); |
| 658 | qdev_prop_set_int32(d, "page-base", 0x80); |
| 659 | qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1); |
| 660 | qdev_prop_set_int32(d, "dshift", 0); |
| 661 | isa_realize_and_unref(isa1, bus, &error_fatal); |
| 662 | |
| 663 | isa2 = isa_new(TYPE_I8257); |
| 664 | object_property_add_child(parent, "dma[*]", OBJECT(isa2)); |
| 665 | d = DEVICE(isa2); |
| 666 | qdev_prop_set_int32(d, "base", 0xc0); |
| 667 | qdev_prop_set_int32(d, "page-base", 0x88); |
| 668 | qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1); |
| 669 | qdev_prop_set_int32(d, "dshift", 1); |
| 670 | isa_realize_and_unref(isa2, bus, &error_fatal); |
| 671 | |
| 672 | isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2)); |
| 673 | } |