| 1 | /* |
| 2 | * Arm PrimeCell PL080/PL081 DMA controller |
| 3 | * |
| 4 | * Copyright (c) 2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This code is licensed under the GPL. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "hw/core/sysbus.h" |
| 12 | #include "migration/vmstate.h" |
| 13 | #include "qemu/log.h" |
| 14 | #include "qemu/module.h" |
| 15 | #include "hw/dma/pl080.h" |
| 16 | #include "hw/core/irq.h" |
| 17 | #include "hw/core/qdev-properties.h" |
| 18 | #include "qapi/error.h" |
| 19 | |
| 20 | #define PL080_CONF_E 0x1 |
| 21 | #define PL080_CONF_M1 0x2 |
| 22 | #define PL080_CONF_M2 0x4 |
| 23 | |
| 24 | #define PL080_CCONF_H 0x40000 |
| 25 | #define PL080_CCONF_A 0x20000 |
| 26 | #define PL080_CCONF_L 0x10000 |
| 27 | #define PL080_CCONF_ITC 0x08000 |
| 28 | #define PL080_CCONF_IE 0x04000 |
| 29 | #define PL080_CCONF_E 0x00001 |
| 30 | |
| 31 | #define PL080_CCTRL_I 0x80000000 |
| 32 | #define PL080_CCTRL_DI 0x08000000 |
| 33 | #define PL080_CCTRL_SI 0x04000000 |
| 34 | #define PL080_CCTRL_D 0x02000000 |
| 35 | #define PL080_CCTRL_S 0x01000000 |
| 36 | |
| 37 | static const VMStateDescription vmstate_pl080_channel = { |
| 38 | .name = "pl080_channel", |
| 39 | .version_id = 1, |
| 40 | .minimum_version_id = 1, |
| 41 | .fields = (const VMStateField[]) { |
| 42 | VMSTATE_UINT32(src, pl080_channel), |
| 43 | VMSTATE_UINT32(dest, pl080_channel), |
| 44 | VMSTATE_UINT32(lli, pl080_channel), |
| 45 | VMSTATE_UINT32(ctrl, pl080_channel), |
| 46 | VMSTATE_UINT32(conf, pl080_channel), |
| 47 | VMSTATE_END_OF_LIST() |
| 48 | } |
| 49 | }; |
| 50 | |
| 51 | static const VMStateDescription vmstate_pl080 = { |
| 52 | .name = "pl080", |
| 53 | .version_id = 1, |
| 54 | .minimum_version_id = 1, |
| 55 | .fields = (const VMStateField[]) { |
| 56 | VMSTATE_UINT8(tc_int, PL080State), |
| 57 | VMSTATE_UINT8(tc_mask, PL080State), |
| 58 | VMSTATE_UINT8(err_int, PL080State), |
| 59 | VMSTATE_UINT8(err_mask, PL080State), |
| 60 | VMSTATE_UINT32(conf, PL080State), |
| 61 | VMSTATE_UINT32(sync, PL080State), |
| 62 | VMSTATE_UINT32(req_single, PL080State), |
| 63 | VMSTATE_UINT32(req_burst, PL080State), |
| 64 | VMSTATE_UINT8(tc_int, PL080State), |
| 65 | VMSTATE_UINT8(tc_int, PL080State), |
| 66 | VMSTATE_UINT8(tc_int, PL080State), |
| 67 | VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS, |
| 68 | 1, vmstate_pl080_channel, pl080_channel), |
| 69 | VMSTATE_INT32(running, PL080State), |
| 70 | VMSTATE_END_OF_LIST() |
| 71 | } |
| 72 | }; |
| 73 | |
| 74 | static const unsigned char pl080_id[] = |
| 75 | { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
| 76 | |
| 77 | static const unsigned char pl081_id[] = |
| 78 | { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
| 79 | |
| 80 | static void pl080_update(PL080State *s) |
| 81 | { |
| 82 | bool tclevel = (s->tc_int & s->tc_mask); |
| 83 | bool errlevel = (s->err_int & s->err_mask); |
| 84 | |
| 85 | qemu_set_irq(s->interr, errlevel); |
| 86 | qemu_set_irq(s->inttc, tclevel); |
| 87 | qemu_set_irq(s->irq, errlevel || tclevel); |
| 88 | } |
| 89 | |
| 90 | static void pl080_run(PL080State *s) |
| 91 | { |
| 92 | int c; |
| 93 | int flow; |
| 94 | pl080_channel *ch; |
| 95 | int swidth; |
| 96 | int dwidth; |
| 97 | int xsize; |
| 98 | int n; |
| 99 | int src_id; |
| 100 | int dest_id; |
| 101 | int size; |
| 102 | uint8_t buff[4]; |
| 103 | uint32_t req; |
| 104 | uint32_t next_lli; |
| 105 | |
| 106 | s->tc_mask = 0; |
| 107 | for (c = 0; c < s->nchannels; c++) { |
| 108 | if (s->chan[c].conf & PL080_CCONF_ITC) |
| 109 | s->tc_mask |= 1 << c; |
| 110 | if (s->chan[c].conf & PL080_CCONF_IE) |
| 111 | s->err_mask |= 1 << c; |
| 112 | } |
| 113 | |
| 114 | if ((s->conf & PL080_CONF_E) == 0) |
| 115 | return; |
| 116 | |
| 117 | /* If we are already in the middle of a DMA operation then indicate that |
| 118 | there may be new DMA requests and return immediately. */ |
| 119 | if (s->running) { |
| 120 | s->running++; |
| 121 | return; |
| 122 | } |
| 123 | s->running = 1; |
| 124 | while (s->running) { |
| 125 | for (c = 0; c < s->nchannels; c++) { |
| 126 | ch = &s->chan[c]; |
| 127 | again: |
| 128 | /* Test if thiws channel has any pending DMA requests. */ |
| 129 | if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E)) |
| 130 | != PL080_CCONF_E) |
| 131 | continue; |
| 132 | flow = (ch->conf >> 11) & 7; |
| 133 | if (flow >= 4) { |
| 134 | qemu_log_mask(LOG_UNIMP, |
| 135 | "pl080_run: Peripheral flow control not implemented\n"); |
| 136 | continue; |
| 137 | } |
| 138 | src_id = (ch->conf >> 1) & 0x1f; |
| 139 | dest_id = (ch->conf >> 6) & 0x1f; |
| 140 | size = ch->ctrl & 0xfff; |
| 141 | req = s->req_single | s->req_burst; |
| 142 | switch (flow) { |
| 143 | case 0: |
| 144 | break; |
| 145 | case 1: |
| 146 | if ((req & (1u << dest_id)) == 0) |
| 147 | size = 0; |
| 148 | break; |
| 149 | case 2: |
| 150 | if ((req & (1u << src_id)) == 0) |
| 151 | size = 0; |
| 152 | break; |
| 153 | case 3: |
| 154 | if ((req & (1u << src_id)) == 0 |
| 155 | || (req & (1u << dest_id)) == 0) |
| 156 | size = 0; |
| 157 | break; |
| 158 | } |
| 159 | if (!size) |
| 160 | continue; |
| 161 | |
| 162 | /* Transfer one element. */ |
| 163 | /* ??? Should transfer multiple elements for a burst request. */ |
| 164 | /* ??? Unclear what the proper behavior is when source and |
| 165 | destination widths are different. */ |
| 166 | swidth = 1 << ((ch->ctrl >> 18) & 7); |
| 167 | dwidth = 1 << ((ch->ctrl >> 21) & 7); |
| 168 | |
| 169 | /* Only widths of 1, 2 or 4 are valid */ |
| 170 | if (swidth > 4) { |
| 171 | qemu_log_mask(LOG_GUEST_ERROR, |
| 172 | "pl080: channel %d: invalid SWidth %d\n", |
| 173 | c, extract32(ch->ctrl, 18, 3)); |
| 174 | continue; |
| 175 | } |
| 176 | if (dwidth > 4) { |
| 177 | qemu_log_mask(LOG_GUEST_ERROR, |
| 178 | "pl080: channel %d: invalid DWidth %d\n", |
| 179 | c, extract32(ch->ctrl, 21, 3)); |
| 180 | continue; |
| 181 | } |
| 182 | if ((size * swidth) % dwidth) { |
| 183 | qemu_log_mask(LOG_GUEST_ERROR, |
| 184 | "pl080: channel %d: transfer size mismatch: size=%d swidth=%d dwidth=%d\n", |
| 185 | c, size, swidth, dwidth); |
| 186 | continue; |
| 187 | } |
| 188 | xsize = MAX(swidth, dwidth); |
| 189 | for (n = 0; n < xsize; n += swidth) { |
| 190 | address_space_read(&s->downstream_as, ch->src, |
| 191 | MEMTXATTRS_UNSPECIFIED, buff + n, swidth); |
| 192 | if (ch->ctrl & PL080_CCTRL_SI) |
| 193 | ch->src += swidth; |
| 194 | } |
| 195 | /* ??? This may pad the value incorrectly for dwidth < 32. */ |
| 196 | for (n = 0; n < xsize; n += dwidth) { |
| 197 | address_space_write(&s->downstream_as, ch->dest, |
| 198 | MEMTXATTRS_UNSPECIFIED, buff + n, dwidth); |
| 199 | if (ch->ctrl & PL080_CCTRL_DI) |
| 200 | ch->dest += dwidth; |
| 201 | } |
| 202 | |
| 203 | size -= xsize / swidth; |
| 204 | ch->ctrl = (ch->ctrl & 0xfffff000) | size; |
| 205 | if (size == 0) { |
| 206 | /* Transfer complete. */ |
| 207 | next_lli = (ch->lli & ~3); |
| 208 | if (next_lli) { |
| 209 | ch->src = address_space_ldl_le(&s->downstream_as, |
| 210 | next_lli, |
| 211 | MEMTXATTRS_UNSPECIFIED, |
| 212 | NULL); |
| 213 | ch->dest = address_space_ldl_le(&s->downstream_as, |
| 214 | next_lli + 4, |
| 215 | MEMTXATTRS_UNSPECIFIED, |
| 216 | NULL); |
| 217 | ch->ctrl = address_space_ldl_le(&s->downstream_as, |
| 218 | next_lli + 12, |
| 219 | MEMTXATTRS_UNSPECIFIED, |
| 220 | NULL); |
| 221 | ch->lli = address_space_ldl_le(&s->downstream_as, |
| 222 | next_lli + 8, |
| 223 | MEMTXATTRS_UNSPECIFIED, |
| 224 | NULL); |
| 225 | } else { |
| 226 | ch->conf &= ~PL080_CCONF_E; |
| 227 | } |
| 228 | if (ch->ctrl & PL080_CCTRL_I) { |
| 229 | s->tc_int |= 1 << c; |
| 230 | } |
| 231 | } |
| 232 | goto again; |
| 233 | } |
| 234 | if (--s->running) |
| 235 | s->running = 1; |
| 236 | } |
| 237 | pl080_update(s); |
| 238 | } |
| 239 | |
| 240 | static uint64_t pl080_read(void *opaque, hwaddr offset, |
| 241 | unsigned size) |
| 242 | { |
| 243 | PL080State *s = (PL080State *)opaque; |
| 244 | uint32_t i; |
| 245 | uint32_t mask; |
| 246 | |
| 247 | if (offset >= 0xfe0 && offset < 0x1000) { |
| 248 | if (s->nchannels == 8) { |
| 249 | return pl080_id[(offset - 0xfe0) >> 2]; |
| 250 | } else { |
| 251 | return pl081_id[(offset - 0xfe0) >> 2]; |
| 252 | } |
| 253 | } |
| 254 | if (offset >= 0x100 && offset < 0x200) { |
| 255 | i = (offset & 0xe0) >> 5; |
| 256 | if (i >= s->nchannels) |
| 257 | goto bad_offset; |
| 258 | switch ((offset >> 2) & 7) { |
| 259 | case 0: /* SrcAddr */ |
| 260 | return s->chan[i].src; |
| 261 | case 1: /* DestAddr */ |
| 262 | return s->chan[i].dest; |
| 263 | case 2: /* LLI */ |
| 264 | return s->chan[i].lli; |
| 265 | case 3: /* Control */ |
| 266 | return s->chan[i].ctrl; |
| 267 | case 4: /* Configuration */ |
| 268 | return s->chan[i].conf; |
| 269 | default: |
| 270 | goto bad_offset; |
| 271 | } |
| 272 | } |
| 273 | switch (offset >> 2) { |
| 274 | case 0: /* IntStatus */ |
| 275 | return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask); |
| 276 | case 1: /* IntTCStatus */ |
| 277 | return (s->tc_int & s->tc_mask); |
| 278 | case 3: /* IntErrorStatus */ |
| 279 | return (s->err_int & s->err_mask); |
| 280 | case 5: /* RawIntTCStatus */ |
| 281 | return s->tc_int; |
| 282 | case 6: /* RawIntErrorStatus */ |
| 283 | return s->err_int; |
| 284 | case 7: /* EnbldChns */ |
| 285 | mask = 0; |
| 286 | for (i = 0; i < s->nchannels; i++) { |
| 287 | if (s->chan[i].conf & PL080_CCONF_E) |
| 288 | mask |= 1 << i; |
| 289 | } |
| 290 | return mask; |
| 291 | case 8: /* SoftBReq */ |
| 292 | case 9: /* SoftSReq */ |
| 293 | case 10: /* SoftLBReq */ |
| 294 | case 11: /* SoftLSReq */ |
| 295 | /* ??? Implement these. */ |
| 296 | return 0; |
| 297 | case 12: /* Configuration */ |
| 298 | return s->conf; |
| 299 | case 13: /* Sync */ |
| 300 | return s->sync; |
| 301 | default: |
| 302 | bad_offset: |
| 303 | qemu_log_mask(LOG_GUEST_ERROR, |
| 304 | "pl080_read: Bad offset %x\n", (int)offset); |
| 305 | return 0; |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | static void pl080_write(void *opaque, hwaddr offset, |
| 310 | uint64_t value, unsigned size) |
| 311 | { |
| 312 | PL080State *s = (PL080State *)opaque; |
| 313 | int i; |
| 314 | |
| 315 | if (offset >= 0x100 && offset < 0x200) { |
| 316 | i = (offset & 0xe0) >> 5; |
| 317 | if (i >= s->nchannels) |
| 318 | goto bad_offset; |
| 319 | switch ((offset >> 2) & 7) { |
| 320 | case 0: /* SrcAddr */ |
| 321 | s->chan[i].src = value; |
| 322 | break; |
| 323 | case 1: /* DestAddr */ |
| 324 | s->chan[i].dest = value; |
| 325 | break; |
| 326 | case 2: /* LLI */ |
| 327 | s->chan[i].lli = value; |
| 328 | break; |
| 329 | case 3: /* Control */ |
| 330 | s->chan[i].ctrl = value; |
| 331 | break; |
| 332 | case 4: /* Configuration */ |
| 333 | s->chan[i].conf = value; |
| 334 | pl080_run(s); |
| 335 | break; |
| 336 | } |
| 337 | return; |
| 338 | } |
| 339 | switch (offset >> 2) { |
| 340 | case 2: /* IntTCClear */ |
| 341 | s->tc_int &= ~value; |
| 342 | break; |
| 343 | case 4: /* IntErrorClear */ |
| 344 | s->err_int &= ~value; |
| 345 | break; |
| 346 | case 8: /* SoftBReq */ |
| 347 | case 9: /* SoftSReq */ |
| 348 | case 10: /* SoftLBReq */ |
| 349 | case 11: /* SoftLSReq */ |
| 350 | /* ??? Implement these. */ |
| 351 | qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n"); |
| 352 | break; |
| 353 | case 12: /* Configuration */ |
| 354 | s->conf = value; |
| 355 | if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) { |
| 356 | qemu_log_mask(LOG_UNIMP, |
| 357 | "pl080_write: Big-endian DMA not implemented\n"); |
| 358 | } |
| 359 | pl080_run(s); |
| 360 | break; |
| 361 | case 13: /* Sync */ |
| 362 | s->sync = value; |
| 363 | break; |
| 364 | default: |
| 365 | bad_offset: |
| 366 | qemu_log_mask(LOG_GUEST_ERROR, |
| 367 | "pl080_write: Bad offset %x\n", (int)offset); |
| 368 | } |
| 369 | pl080_update(s); |
| 370 | } |
| 371 | |
| 372 | static const MemoryRegionOps pl080_ops = { |
| 373 | .read = pl080_read, |
| 374 | .write = pl080_write, |
| 375 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 376 | }; |
| 377 | |
| 378 | static void pl080_reset(DeviceState *dev) |
| 379 | { |
| 380 | PL080State *s = PL080(dev); |
| 381 | int i; |
| 382 | |
| 383 | s->tc_int = 0; |
| 384 | s->tc_mask = 0; |
| 385 | s->err_int = 0; |
| 386 | s->err_mask = 0; |
| 387 | s->conf = 0; |
| 388 | s->sync = 0; |
| 389 | s->req_single = 0; |
| 390 | s->req_burst = 0; |
| 391 | s->running = 0; |
| 392 | |
| 393 | for (i = 0; i < s->nchannels; i++) { |
| 394 | s->chan[i].src = 0; |
| 395 | s->chan[i].dest = 0; |
| 396 | s->chan[i].lli = 0; |
| 397 | s->chan[i].ctrl = 0; |
| 398 | s->chan[i].conf = 0; |
| 399 | } |
| 400 | } |
| 401 | |
| 402 | static void pl080_init(Object *obj) |
| 403 | { |
| 404 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 405 | PL080State *s = PL080(obj); |
| 406 | |
| 407 | memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000); |
| 408 | sysbus_init_mmio(sbd, &s->iomem); |
| 409 | sysbus_init_irq(sbd, &s->irq); |
| 410 | sysbus_init_irq(sbd, &s->interr); |
| 411 | sysbus_init_irq(sbd, &s->inttc); |
| 412 | s->nchannels = 8; |
| 413 | } |
| 414 | |
| 415 | static void pl080_realize(DeviceState *dev, Error **errp) |
| 416 | { |
| 417 | PL080State *s = PL080(dev); |
| 418 | |
| 419 | if (!s->downstream) { |
| 420 | error_setg(errp, "PL080 'downstream' link not set"); |
| 421 | return; |
| 422 | } |
| 423 | |
| 424 | address_space_init(&s->downstream_as, s->downstream, "pl080-downstream"); |
| 425 | } |
| 426 | |
| 427 | static void pl081_init(Object *obj) |
| 428 | { |
| 429 | PL080State *s = PL080(obj); |
| 430 | |
| 431 | s->nchannels = 2; |
| 432 | } |
| 433 | |
| 434 | static const Property pl080_properties[] = { |
| 435 | DEFINE_PROP_LINK("downstream", PL080State, downstream, |
| 436 | TYPE_MEMORY_REGION, MemoryRegion *), |
| 437 | }; |
| 438 | |
| 439 | static void pl080_class_init(ObjectClass *oc, const void *data) |
| 440 | { |
| 441 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 442 | |
| 443 | dc->vmsd = &vmstate_pl080; |
| 444 | dc->realize = pl080_realize; |
| 445 | device_class_set_props(dc, pl080_properties); |
| 446 | device_class_set_legacy_reset(dc, pl080_reset); |
| 447 | } |
| 448 | |
| 449 | static const TypeInfo pl080_info = { |
| 450 | .name = TYPE_PL080, |
| 451 | .parent = TYPE_SYS_BUS_DEVICE, |
| 452 | .instance_size = sizeof(PL080State), |
| 453 | .instance_init = pl080_init, |
| 454 | .class_init = pl080_class_init, |
| 455 | }; |
| 456 | |
| 457 | static const TypeInfo pl081_info = { |
| 458 | .name = TYPE_PL081, |
| 459 | .parent = TYPE_PL080, |
| 460 | .instance_init = pl081_init, |
| 461 | }; |
| 462 | |
| 463 | /* The PL080 and PL081 are the same except for the number of channels |
| 464 | they implement (8 and 2 respectively). */ |
| 465 | static void pl080_register_types(void) |
| 466 | { |
| 467 | type_register_static(&pl080_info); |
| 468 | type_register_static(&pl081_info); |
| 469 | } |
| 470 | |
| 471 | type_init(pl080_register_types) |