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1 /*
2 * ARM PrimeCell PL330 DMA Controller
3 *
4 * Copyright (c) 2009 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
7 * Copyright (c) 2012 PetaLogix Pty Ltd.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 or later.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include "qemu/osdep.h"
18 #include "qemu/cutils.h"
19 #include "hw/core/irq.h"
20 #include "hw/core/qdev-properties.h"
21 #include "hw/core/sysbus.h"
22 #include "migration/vmstate.h"
23 #include "qapi/error.h"
24 #include "qemu/timer.h"
25 #include "system/dma.h"
26 #include "qemu/log.h"
27 #include "qemu/module.h"
28 #include "trace.h"
29 #include "qom/object.h"
30
31 #ifndef PL330_ERR_DEBUG
32 #define PL330_ERR_DEBUG 0
33 #endif
34
35 #define PL330_PERIPH_NUM 32
36 #define PL330_MAX_BURST_LEN 128
37 #define PL330_INSN_MAXSIZE 6
38
39 #define PL330_FIFO_OK 0
40 #define PL330_FIFO_STALL 1
41 #define PL330_FIFO_ERR (-1)
42
43 #define PL330_FAULT_UNDEF_INSTR (1 << 0)
44 #define PL330_FAULT_OPERAND_INVALID (1 << 1)
45 #define PL330_FAULT_DMAGO_ERR (1 << 4)
46 #define PL330_FAULT_EVENT_ERR (1 << 5)
47 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6)
48 #define PL330_FAULT_CH_RDWR_ERR (1 << 7)
49 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12)
50 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13)
51 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16)
52 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17)
53 #define PL330_FAULT_DATA_READ_ERR (1 << 18)
54 #define PL330_FAULT_DBG_INSTR (1 << 30)
55 #define PL330_FAULT_LOCKUP_ERR (1 << 31)
56
57 #define PL330_UNTAGGED 0xff
58
59 #define PL330_SINGLE 0x0
60 #define PL330_BURST 0x1
61
62 #define PL330_WATCHDOG_LIMIT 1024
63
64 /* IOMEM mapped registers */
65 #define PL330_REG_DSR 0x000
66 #define PL330_REG_DPC 0x004
67 #define PL330_REG_INTEN 0x020
68 #define PL330_REG_INT_EVENT_RIS 0x024
69 #define PL330_REG_INTMIS 0x028
70 #define PL330_REG_INTCLR 0x02C
71 #define PL330_REG_FSRD 0x030
72 #define PL330_REG_FSRC 0x034
73 #define PL330_REG_FTRD 0x038
74 #define PL330_REG_FTR_BASE 0x040
75 #define PL330_REG_CSR_BASE 0x100
76 #define PL330_REG_CPC_BASE 0x104
77 #define PL330_REG_CHANCTRL 0x400
78 #define PL330_REG_DBGSTATUS 0xD00
79 #define PL330_REG_DBGCMD 0xD04
80 #define PL330_REG_DBGINST0 0xD08
81 #define PL330_REG_DBGINST1 0xD0C
82 #define PL330_REG_CR0_BASE 0xE00
83 #define PL330_REG_PERIPH_ID 0xFE0
84
85 #define PL330_IOMEM_SIZE 0x1000
86
87 #define CFG_BOOT_ADDR 2
88 #define CFG_INS 3
89 #define CFG_PNS 4
90 #define CFG_CRD 5
91
92 static const uint32_t pl330_id[] = {
93 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1
94 };
95
96 /* DMA channel states as they are described in PL330 Technical Reference Manual
97 * Most of them will not be used in emulation.
98 */
99 typedef enum {
100 pl330_chan_stopped = 0,
101 pl330_chan_executing = 1,
102 pl330_chan_cache_miss = 2,
103 pl330_chan_updating_pc = 3,
104 pl330_chan_waiting_event = 4,
105 pl330_chan_at_barrier = 5,
106 pl330_chan_queue_busy = 6,
107 pl330_chan_waiting_periph = 7,
108 pl330_chan_killing = 8,
109 pl330_chan_completing = 9,
110 pl330_chan_fault_completing = 14,
111 pl330_chan_fault = 15,
112 } PL330ChanState;
113
114 #define TYPE_PL330 "pl330"
115 OBJECT_DECLARE_SIMPLE_TYPE(PL330State, PL330)
116
117 typedef struct PL330Chan {
118 uint32_t src;
119 uint32_t dst;
120 uint32_t pc;
121 uint32_t control;
122 uint32_t status;
123 uint32_t lc[2];
124 uint32_t fault_type;
125 uint32_t watchdog_timer;
126
127 bool ns;
128 uint8_t request_flag;
129 uint8_t wakeup;
130 uint8_t wfp_sbp;
131
132 uint8_t state;
133 uint8_t stall;
134
135 bool is_manager;
136 PL330State *parent;
137 uint8_t tag;
138 } PL330Chan;
139
140 static const VMStateDescription vmstate_pl330_chan = {
141 .name = "pl330_chan",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (const VMStateField[]) {
145 VMSTATE_UINT32(src, PL330Chan),
146 VMSTATE_UINT32(dst, PL330Chan),
147 VMSTATE_UINT32(pc, PL330Chan),
148 VMSTATE_UINT32(control, PL330Chan),
149 VMSTATE_UINT32(status, PL330Chan),
150 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2),
151 VMSTATE_UINT32(fault_type, PL330Chan),
152 VMSTATE_UINT32(watchdog_timer, PL330Chan),
153 VMSTATE_BOOL(ns, PL330Chan),
154 VMSTATE_UINT8(request_flag, PL330Chan),
155 VMSTATE_UINT8(wakeup, PL330Chan),
156 VMSTATE_UINT8(wfp_sbp, PL330Chan),
157 VMSTATE_UINT8(state, PL330Chan),
158 VMSTATE_UINT8(stall, PL330Chan),
159 VMSTATE_END_OF_LIST()
160 }
161 };
162
163 typedef struct PL330Fifo {
164 uint8_t *buf;
165 uint8_t *tag;
166 uint32_t head;
167 uint32_t num;
168 uint32_t buf_size;
169 } PL330Fifo;
170
171 static const VMStateDescription vmstate_pl330_fifo = {
172 .name = "pl330_chan",
173 .version_id = 1,
174 .minimum_version_id = 1,
175 .fields = (const VMStateField[]) {
176 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size),
177 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size),
178 VMSTATE_UINT32(head, PL330Fifo),
179 VMSTATE_UINT32(num, PL330Fifo),
180 VMSTATE_UINT32(buf_size, PL330Fifo),
181 VMSTATE_END_OF_LIST()
182 }
183 };
184
185 typedef struct PL330QueueEntry {
186 uint32_t addr;
187 uint32_t len;
188 uint8_t n;
189 bool inc;
190 bool z;
191 uint8_t tag;
192 uint8_t seqn;
193 } PL330QueueEntry;
194
195 static const VMStateDescription vmstate_pl330_queue_entry = {
196 .name = "pl330_queue_entry",
197 .version_id = 1,
198 .minimum_version_id = 1,
199 .fields = (const VMStateField[]) {
200 VMSTATE_UINT32(addr, PL330QueueEntry),
201 VMSTATE_UINT32(len, PL330QueueEntry),
202 VMSTATE_UINT8(n, PL330QueueEntry),
203 VMSTATE_BOOL(inc, PL330QueueEntry),
204 VMSTATE_BOOL(z, PL330QueueEntry),
205 VMSTATE_UINT8(tag, PL330QueueEntry),
206 VMSTATE_UINT8(seqn, PL330QueueEntry),
207 VMSTATE_END_OF_LIST()
208 }
209 };
210
211 typedef struct PL330Queue {
212 PL330State *parent;
213 PL330QueueEntry *queue;
214 uint32_t queue_size;
215 } PL330Queue;
216
217 static const VMStateDescription vmstate_pl330_queue = {
218 .name = "pl330_queue",
219 .version_id = 2,
220 .minimum_version_id = 2,
221 .fields = (const VMStateField[]) {
222 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size,
223 vmstate_pl330_queue_entry,
224 PL330QueueEntry),
225 VMSTATE_END_OF_LIST()
226 }
227 };
228
229 struct PL330State {
230 SysBusDevice parent_obj;
231
232 MemoryRegion iomem;
233 qemu_irq irq_abort;
234 qemu_irq *irq;
235
236 /* Config registers. cfg[5] = CfgDn. */
237 uint32_t cfg[6];
238 #define EVENT_SEC_STATE 3
239 #define PERIPH_SEC_STATE 4
240 /* cfg 0 bits and pieces */
241 uint32_t num_chnls;
242 uint8_t num_periph_req;
243 uint8_t num_events;
244 uint8_t mgr_ns_at_rst;
245 /* cfg 1 bits and pieces */
246 uint8_t i_cache_len;
247 uint8_t num_i_cache_lines;
248 /* CRD bits and pieces */
249 uint8_t data_width;
250 uint8_t wr_cap;
251 uint8_t wr_q_dep;
252 uint8_t rd_cap;
253 uint8_t rd_q_dep;
254 uint16_t data_buffer_dep;
255
256 PL330Chan manager;
257 PL330Chan *chan;
258 PL330Fifo fifo;
259 PL330Queue read_queue;
260 PL330Queue write_queue;
261 uint8_t *lo_seqn;
262 uint8_t *hi_seqn;
263 QEMUTimer *timer; /* is used for restore dma. */
264
265 uint32_t inten;
266 uint32_t int_status;
267 uint32_t ev_status;
268 uint32_t dbg[2];
269 uint8_t debug_status;
270 uint8_t num_faulting;
271 uint8_t periph_busy[PL330_PERIPH_NUM];
272
273 /* Memory region that DMA operation access */
274 MemoryRegion *mem_mr;
275 AddressSpace *mem_as;
276 };
277
278 static const VMStateDescription vmstate_pl330 = {
279 .name = "pl330",
280 .version_id = 2,
281 .minimum_version_id = 2,
282 .fields = (const VMStateField[]) {
283 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
284 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls,
285 vmstate_pl330_chan, PL330Chan),
286 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls),
287 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls),
288 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
289 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue,
290 PL330Queue),
291 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
292 PL330Queue),
293 VMSTATE_TIMER_PTR(timer, PL330State),
294 VMSTATE_UINT32(inten, PL330State),
295 VMSTATE_UINT32(int_status, PL330State),
296 VMSTATE_UINT32(ev_status, PL330State),
297 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2),
298 VMSTATE_UINT8(debug_status, PL330State),
299 VMSTATE_UINT8(num_faulting, PL330State),
300 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM),
301 VMSTATE_END_OF_LIST()
302 }
303 };
304
305 typedef struct PL330InsnDesc {
306 /* OPCODE of the instruction */
307 uint8_t opcode;
308 /* Mask so we can select several sibling instructions, such as
309 DMALD, DMALDS and DMALDB */
310 uint8_t opmask;
311 /* Size of instruction in bytes */
312 uint8_t size;
313 /* Interpreter */
314 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len);
315 } PL330InsnDesc;
316
317 static void pl330_hexdump(uint8_t *buf, size_t size)
318 {
319 g_autoptr(GString) str = g_string_sized_new(64);
320 size_t b, len;
321
322 for (b = 0; b < size; b += len) {
323 len = MIN(16, size - b);
324 g_string_truncate(str, 0);
325 qemu_hexdump_line(str, buf + b, len, 1, 4);
326 trace_pl330_hexdump(b, str->str);
327 }
328 }
329
330 /* MFIFO Implementation
331 *
332 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are
333 * stored in this buffer. Data is stored in BUF field, tags - in the
334 * corresponding array elements of TAG field.
335 */
336
337 /* Initialize queue. */
338
339 static void pl330_fifo_init(PL330Fifo *s, uint32_t size)
340 {
341 s->buf = g_malloc0(size);
342 s->tag = g_malloc0(size);
343 s->buf_size = size;
344 }
345
346 /* Cyclic increment */
347
348 static inline int pl330_fifo_inc(PL330Fifo *s, int x)
349 {
350 return (x + 1) % s->buf_size;
351 }
352
353 /* Number of empty bytes in MFIFO */
354
355 static inline int pl330_fifo_num_free(PL330Fifo *s)
356 {
357 return s->buf_size - s->num;
358 }
359
360 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG.
361 * Zero returned on success, PL330_FIFO_STALL if there is no enough free
362 * space in MFIFO to store requested amount of data. If push was unsuccessful
363 * no data is stored to MFIFO.
364 */
365
366 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
367 {
368 int i;
369
370 if (s->buf_size - s->num < len) {
371 return PL330_FIFO_STALL;
372 }
373 for (i = 0; i < len; i++) {
374 int push_idx = (s->head + s->num + i) % s->buf_size;
375 s->buf[push_idx] = buf[i];
376 s->tag[push_idx] = tag;
377 }
378 s->num += len;
379 return PL330_FIFO_OK;
380 }
381
382 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each
383 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch
384 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was
385 * unsuccessful no data is removed from MFIFO.
386 */
387
388 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
389 {
390 int i;
391
392 if (s->num < len) {
393 return PL330_FIFO_STALL;
394 }
395 for (i = 0; i < len; i++) {
396 if (s->tag[s->head] == tag) {
397 int get_idx = (s->head + i) % s->buf_size;
398 buf[i] = s->buf[get_idx];
399 } else { /* Tag mismatch - Rollback transaction */
400 return PL330_FIFO_ERR;
401 }
402 }
403 s->head = (s->head + len) % s->buf_size;
404 s->num -= len;
405 return PL330_FIFO_OK;
406 }
407
408 /* Reset MFIFO. This completely erases all data in it. */
409
410 static inline void pl330_fifo_reset(PL330Fifo *s)
411 {
412 s->head = 0;
413 s->num = 0;
414 }
415
416 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty
417 * PL330_UNTAGGED is returned.
418 */
419
420 static inline uint8_t pl330_fifo_tag(PL330Fifo *s)
421 {
422 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head];
423 }
424
425 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */
426
427 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag)
428 {
429 int i, n;
430
431 i = s->head;
432 for (n = 0; n < s->num; n++) {
433 if (s->tag[i] == tag) {
434 return 1;
435 }
436 i = pl330_fifo_inc(s, i);
437 }
438 return 0;
439 }
440
441 /* Remove all entry tagged with TAG from MFIFO */
442
443 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag)
444 {
445 int i, t, n;
446
447 t = i = s->head;
448 for (n = 0; n < s->num; n++) {
449 if (s->tag[i] != tag) {
450 s->buf[t] = s->buf[i];
451 s->tag[t] = s->tag[i];
452 t = pl330_fifo_inc(s, t);
453 } else {
454 s->num = s->num - 1;
455 }
456 i = pl330_fifo_inc(s, i);
457 }
458 }
459
460 /* Read-Write Queue implementation
461 *
462 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores).
463 * Each instruction is described by source (for loads) or destination (for
464 * stores) address ADDR, width of data to be loaded/stored LEN, number of
465 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel
466 * this instruction belongs to. Queue does not store any information about
467 * nature of the instruction: is it load or store. PL330 has different queues
468 * for loads and stores so this is already known at the top level where it
469 * matters.
470 *
471 * Queue works as FIFO for instructions with equivalent tags, but can issue
472 * instructions with different tags in arbitrary order. SEQN field attached to
473 * each instruction helps to achieve this. For each TAG queue contains
474 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to
475 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is
476 * followed by SEQN=0.
477 *
478 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed
479 * in this case.
480 */
481
482 static void pl330_queue_reset(PL330Queue *s)
483 {
484 int i;
485
486 for (i = 0; i < s->queue_size; i++) {
487 s->queue[i].tag = PL330_UNTAGGED;
488 }
489 }
490
491 /* Initialize queue */
492 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent)
493 {
494 s->parent = parent;
495 s->queue = g_new0(PL330QueueEntry, size);
496 s->queue_size = size;
497 }
498
499 /* Returns pointer to an empty slot or NULL if queue is full */
500 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s)
501 {
502 int i;
503
504 for (i = 0; i < s->queue_size; i++) {
505 if (s->queue[i].tag == PL330_UNTAGGED) {
506 return &s->queue[i];
507 }
508 }
509 return NULL;
510 }
511
512 /* Put instruction in queue.
513 * Return value:
514 * - zero - OK
515 * - non-zero - queue is full
516 */
517
518 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr,
519 int len, int n, bool inc, bool z, uint8_t tag)
520 {
521 PL330QueueEntry *entry = pl330_queue_find_empty(s);
522
523 if (!entry) {
524 return 1;
525 }
526 entry->tag = tag;
527 entry->addr = addr;
528 entry->len = len;
529 entry->n = n;
530 entry->z = z;
531 entry->inc = inc;
532 entry->seqn = s->parent->hi_seqn[tag];
533 s->parent->hi_seqn[tag]++;
534 return 0;
535 }
536
537 /* Returns a pointer to queue slot containing instruction which satisfies
538 * following conditions:
539 * - it has valid tag value (not PL330_UNTAGGED)
540 * - if enforce_seq is set it has to be issuable without violating queue
541 * logic (see above)
542 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value
543 * equivalent to the argument TAG value.
544 * If such instruction cannot be found NULL is returned.
545 */
546
547 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag,
548 bool enforce_seq)
549 {
550 int i;
551
552 for (i = 0; i < s->queue_size; i++) {
553 if (s->queue[i].tag != PL330_UNTAGGED) {
554 if ((!enforce_seq ||
555 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) &&
556 (s->queue[i].tag == tag || tag == PL330_UNTAGGED ||
557 s->queue[i].z)) {
558 return &s->queue[i];
559 }
560 }
561 }
562 return NULL;
563 }
564
565 /* Removes instruction from queue. */
566
567 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e)
568 {
569 s->parent->lo_seqn[e->tag]++;
570 e->tag = PL330_UNTAGGED;
571 }
572
573 /* Removes all instructions tagged with TAG from queue. */
574
575 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag)
576 {
577 int i;
578
579 for (i = 0; i < s->queue_size; i++) {
580 if (s->queue[i].tag == tag) {
581 s->queue[i].tag = PL330_UNTAGGED;
582 }
583 }
584 }
585
586 /* DMA instruction execution engine */
587
588 /* Moves DMA channel to the FAULT state and updates it's status. */
589
590 static inline void pl330_fault(PL330Chan *ch, uint32_t flags)
591 {
592 trace_pl330_fault(ch, flags);
593 ch->fault_type |= flags;
594 if (ch->state == pl330_chan_fault) {
595 return;
596 }
597 ch->state = pl330_chan_fault;
598 ch->parent->num_faulting++;
599 if (ch->parent->num_faulting == 1) {
600 trace_pl330_fault_abort();
601 qemu_irq_raise(ch->parent->irq_abort);
602 }
603 }
604
605 /*
606 * For information about instructions see PL330 Technical Reference Manual.
607 *
608 * Arguments:
609 * CH - channel executing the instruction
610 * OPCODE - opcode
611 * ARGS - array of 8-bit arguments
612 * LEN - number of elements in ARGS array
613 */
614
615 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg)
616 {
617 uint32_t im = (args[1] << 8) | args[0];
618 if (neg) {
619 im |= 0xffffu << 16;
620 }
621
622 if (ch->is_manager) {
623 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
624 return;
625 }
626 if (ra) {
627 ch->dst += im;
628 } else {
629 ch->src += im;
630 }
631 }
632
633 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
634 {
635 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false);
636 }
637
638 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
639 {
640 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true);
641 }
642
643 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode,
644 uint8_t *args, int len)
645 {
646 PL330State *s = ch->parent;
647
648 if (ch->state == pl330_chan_executing && !ch->is_manager) {
649 /* Wait for all transfers to complete */
650 if (pl330_fifo_has_tag(&s->fifo, ch->tag) ||
651 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL ||
652 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) {
653
654 ch->stall = 1;
655 return;
656 }
657 }
658 trace_pl330_dmaend();
659 pl330_fifo_tagged_remove(&s->fifo, ch->tag);
660 pl330_queue_remove_tagged(&s->read_queue, ch->tag);
661 pl330_queue_remove_tagged(&s->write_queue, ch->tag);
662 ch->state = pl330_chan_stopped;
663 }
664
665 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode,
666 uint8_t *args, int len)
667 {
668 uint8_t periph_id;
669
670 if (args[0] & 7) {
671 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
672 return;
673 }
674 periph_id = (args[0] >> 3) & 0x1f;
675 if (periph_id >= ch->parent->num_periph_req) {
676 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
677 return;
678 }
679 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
680 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
681 return;
682 }
683 /* Do nothing */
684 }
685
686 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
687 {
688 uint8_t chan_id;
689 uint8_t ns;
690 uint32_t pc;
691 PL330Chan *s;
692
693 trace_pl330_dmago();
694
695 if (!ch->is_manager) {
696 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
697 return;
698 }
699 ns = !!(opcode & 2);
700 chan_id = args[0] & 7;
701 if ((args[0] >> 3)) {
702 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
703 return;
704 }
705 if (chan_id >= ch->parent->num_chnls) {
706 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
707 return;
708 }
709 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
710 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
711 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) {
712 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
713 return;
714 }
715 if (ch->ns && !ns) {
716 pl330_fault(ch, PL330_FAULT_DMAGO_ERR);
717 return;
718 }
719 s = &ch->parent->chan[chan_id];
720 s->ns = ns;
721 s->pc = pc;
722 s->state = pl330_chan_executing;
723 }
724
725 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
726 {
727 uint8_t bs = opcode & 3;
728 uint32_t size, num;
729 bool inc;
730
731 if (bs == 2) {
732 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
733 return;
734 }
735 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
736 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
737 /* Perform NOP */
738 return;
739 }
740 if (bs == 1 && ch->request_flag == PL330_SINGLE) {
741 num = 1;
742 } else {
743 num = ((ch->control >> 4) & 0xf) + 1;
744 }
745 size = (uint32_t)1 << ((ch->control >> 1) & 0x7);
746 inc = !!(ch->control & 1);
747 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src,
748 size, num, inc, 0, ch->tag);
749 if (!ch->stall) {
750 trace_pl330_dmald(ch->tag, ch->src, size, num, inc ? 'Y' : 'N');
751 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0;
752 }
753 }
754
755 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
756 {
757 uint8_t periph_id;
758
759 if (args[0] & 7) {
760 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
761 return;
762 }
763 periph_id = (args[0] >> 3) & 0x1f;
764 if (periph_id >= ch->parent->num_periph_req) {
765 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
766 return;
767 }
768 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
769 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
770 return;
771 }
772 pl330_dmald(ch, opcode, args, len);
773 }
774
775 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
776 {
777 uint8_t lc = (opcode & 2) >> 1;
778
779 ch->lc[lc] = args[0];
780 }
781
782 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
783 {
784 if (ch->state == pl330_chan_fault ||
785 ch->state == pl330_chan_fault_completing) {
786 /* This is the only way for a channel to leave the faulting state */
787 ch->fault_type = 0;
788 ch->parent->num_faulting--;
789 if (ch->parent->num_faulting == 0) {
790 trace_pl330_dmakill();
791 qemu_irq_lower(ch->parent->irq_abort);
792 }
793 }
794 ch->state = pl330_chan_killing;
795 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag);
796 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag);
797 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag);
798 ch->state = pl330_chan_stopped;
799 }
800
801 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode,
802 uint8_t *args, int len)
803 {
804 uint8_t nf = (opcode & 0x10) >> 4;
805 uint8_t bs = opcode & 3;
806 uint8_t lc = (opcode & 4) >> 2;
807
808 trace_pl330_dmalpend(nf, bs, lc, ch->lc[lc], ch->request_flag);
809
810 if (bs == 2) {
811 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
812 return;
813 }
814 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
815 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
816 /* Perform NOP */
817 return;
818 }
819 if (!nf || ch->lc[lc]) {
820 if (nf) {
821 ch->lc[lc]--;
822 }
823 trace_pl330_dmalpiter();
824 ch->pc -= args[0];
825 ch->pc -= len + 1;
826 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */
827 } else {
828 trace_pl330_dmalpfallthrough();
829 }
830 }
831
832
833 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
834 {
835 uint8_t rd = args[0] & 7;
836 uint32_t im;
837
838 if ((args[0] >> 3)) {
839 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
840 return;
841 }
842 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
843 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
844 switch (rd) {
845 case 0:
846 ch->src = im;
847 break;
848 case 1:
849 ch->control = im;
850 break;
851 case 2:
852 ch->dst = im;
853 break;
854 default:
855 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
856 return;
857 }
858 }
859
860 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode,
861 uint8_t *args, int len)
862 {
863 /* NOP is NOP. */
864 }
865
866 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
867 {
868 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) {
869 ch->state = pl330_chan_at_barrier;
870 ch->stall = 1;
871 return;
872 } else {
873 ch->state = pl330_chan_executing;
874 }
875 }
876
877 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
878 {
879 uint8_t ev_id;
880
881 if (args[0] & 7) {
882 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
883 return;
884 }
885 ev_id = (args[0] >> 3) & 0x1f;
886 if (ev_id >= ch->parent->num_events) {
887 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
888 return;
889 }
890 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
891 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
892 return;
893 }
894 if (ch->parent->inten & (1 << ev_id)) {
895 ch->parent->int_status |= (1 << ev_id);
896 trace_pl330_dmasev_evirq(ev_id);
897 qemu_irq_raise(ch->parent->irq[ev_id]);
898 }
899 trace_pl330_dmasev_event(ev_id);
900 ch->parent->ev_status |= (1 << ev_id);
901 }
902
903 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
904 {
905 uint8_t bs = opcode & 3;
906 uint32_t size, num;
907 bool inc;
908
909 if (bs == 2) {
910 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
911 return;
912 }
913 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
914 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
915 /* Perform NOP */
916 return;
917 }
918 num = ((ch->control >> 18) & 0xf) + 1;
919 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
920 inc = !!((ch->control >> 14) & 1);
921 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
922 size, num, inc, 0, ch->tag);
923 if (!ch->stall) {
924 trace_pl330_dmast(ch->tag, ch->dst, size, num, inc ? 'Y' : 'N');
925 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0;
926 }
927 }
928
929 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode,
930 uint8_t *args, int len)
931 {
932 uint8_t periph_id;
933
934 if (args[0] & 7) {
935 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
936 return;
937 }
938 periph_id = (args[0] >> 3) & 0x1f;
939 if (periph_id >= ch->parent->num_periph_req) {
940 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
941 return;
942 }
943 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
944 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
945 return;
946 }
947 pl330_dmast(ch, opcode, args, len);
948 }
949
950 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode,
951 uint8_t *args, int len)
952 {
953 uint32_t size, num;
954 bool inc;
955
956 num = ((ch->control >> 18) & 0xf) + 1;
957 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
958 inc = !!((ch->control >> 14) & 1);
959 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
960 size, num, inc, 1, ch->tag);
961 if (inc) {
962 ch->dst += size * num;
963 }
964 }
965
966 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode,
967 uint8_t *args, int len)
968 {
969 uint8_t ev_id;
970 int i;
971
972 if (args[0] & 5) {
973 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
974 return;
975 }
976 ev_id = (args[0] >> 3) & 0x1f;
977 if (ev_id >= ch->parent->num_events) {
978 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
979 return;
980 }
981 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
982 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
983 return;
984 }
985 ch->wakeup = ev_id;
986 ch->state = pl330_chan_waiting_event;
987 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) {
988 ch->state = pl330_chan_executing;
989 /* If anyone else is currently waiting on the same event, let them
990 * clear the ev_status so they pick up event as well
991 */
992 for (i = 0; i < ch->parent->num_chnls; ++i) {
993 PL330Chan *peer = &ch->parent->chan[i];
994 if (peer->state == pl330_chan_waiting_event &&
995 peer->wakeup == ev_id) {
996 return;
997 }
998 }
999 ch->parent->ev_status &= ~(1 << ev_id);
1000 trace_pl330_dmawfe(ev_id);
1001 } else {
1002 ch->stall = 1;
1003 }
1004 }
1005
1006 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode,
1007 uint8_t *args, int len)
1008 {
1009 uint8_t bs = opcode & 3;
1010 uint8_t periph_id;
1011
1012 if (args[0] & 7) {
1013 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1014 return;
1015 }
1016 periph_id = (args[0] >> 3) & 0x1f;
1017 if (periph_id >= ch->parent->num_periph_req) {
1018 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1019 return;
1020 }
1021 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
1022 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
1023 return;
1024 }
1025 switch (bs) {
1026 case 0: /* S */
1027 ch->request_flag = PL330_SINGLE;
1028 ch->wfp_sbp = 0;
1029 break;
1030 case 1: /* P */
1031 ch->request_flag = PL330_BURST;
1032 ch->wfp_sbp = 2;
1033 break;
1034 case 2: /* B */
1035 ch->request_flag = PL330_BURST;
1036 ch->wfp_sbp = 1;
1037 break;
1038 default:
1039 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1040 return;
1041 }
1042
1043 if (ch->parent->periph_busy[periph_id]) {
1044 ch->state = pl330_chan_waiting_periph;
1045 ch->stall = 1;
1046 } else if (ch->state == pl330_chan_waiting_periph) {
1047 ch->state = pl330_chan_executing;
1048 }
1049 }
1050
1051 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode,
1052 uint8_t *args, int len)
1053 {
1054 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) {
1055 ch->state = pl330_chan_at_barrier;
1056 ch->stall = 1;
1057 return;
1058 } else {
1059 ch->state = pl330_chan_executing;
1060 }
1061 }
1062
1063 /* NULL terminated array of the instruction descriptions. */
1064 static const PL330InsnDesc insn_desc[] = {
1065 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, },
1066 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, },
1067 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, },
1068 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, },
1069 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1070 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, },
1071 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, },
1072 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, },
1073 /* dmastp must be before dmalpend in this list, because their maps
1074 * are overlapping
1075 */
1076 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, },
1077 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, },
1078 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1079 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, },
1080 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, },
1081 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, },
1082 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1083 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, },
1084 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, },
1085 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, },
1086 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, },
1087 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, },
1088 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1089 };
1090
1091 /* Instructions which can be issued via debug registers. */
1092 static const PL330InsnDesc debug_insn_desc[] = {
1093 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1094 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1095 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1096 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1097 };
1098
1099 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)
1100 {
1101 uint8_t opcode;
1102 int i;
1103
1104 dma_memory_read(ch->parent->mem_as, ch->pc, &opcode, 1,
1105 MEMTXATTRS_UNSPECIFIED);
1106 for (i = 0; insn_desc[i].size; i++) {
1107 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
1108 return &insn_desc[i];
1109 }
1110 }
1111 return NULL;
1112 }
1113
1114 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)
1115 {
1116 uint8_t buf[PL330_INSN_MAXSIZE];
1117
1118 assert(insn->size <= PL330_INSN_MAXSIZE);
1119 dma_memory_read(ch->parent->mem_as, ch->pc, buf, insn->size,
1120 MEMTXATTRS_UNSPECIFIED);
1121 insn->exec(ch, buf[0], &buf[1], insn->size - 1);
1122 }
1123
1124 static inline void pl330_update_pc(PL330Chan *ch,
1125 const PL330InsnDesc *insn)
1126 {
1127 ch->pc += insn->size;
1128 }
1129
1130 /* Try to execute current instruction in channel CH. Number of executed
1131 instructions is returned (0 or 1). */
1132 static int pl330_chan_exec(PL330Chan *ch)
1133 {
1134 const PL330InsnDesc *insn;
1135
1136 if (ch->state != pl330_chan_executing &&
1137 ch->state != pl330_chan_waiting_periph &&
1138 ch->state != pl330_chan_at_barrier &&
1139 ch->state != pl330_chan_waiting_event) {
1140 return 0;
1141 }
1142 ch->stall = 0;
1143 insn = pl330_fetch_insn(ch);
1144 if (!insn) {
1145 trace_pl330_chan_exec_undef();
1146 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
1147 return 0;
1148 }
1149 pl330_exec_insn(ch, insn);
1150 if (!ch->stall) {
1151 pl330_update_pc(ch, insn);
1152 ch->watchdog_timer = 0;
1153 return 1;
1154 /* WDT only active in exec state */
1155 } else if (ch->state == pl330_chan_executing) {
1156 ch->watchdog_timer++;
1157 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) {
1158 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR);
1159 }
1160 }
1161 return 0;
1162 }
1163
1164 /* Try to execute 1 instruction in each channel, one instruction from read
1165 queue and one instruction from write queue. Number of successfully executed
1166 instructions is returned. */
1167 static int pl330_exec_cycle(PL330Chan *channel)
1168 {
1169 PL330State *s = channel->parent;
1170 PL330QueueEntry *q;
1171 int i;
1172 int num_exec = 0;
1173 int fifo_res = 0;
1174 uint8_t buf[PL330_MAX_BURST_LEN];
1175
1176 /* Execute one instruction in each channel */
1177 num_exec += pl330_chan_exec(channel);
1178
1179 /* Execute one instruction from read queue */
1180 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true);
1181 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) {
1182 int len = q->len - (q->addr & (q->len - 1));
1183
1184 dma_memory_read(s->mem_as, q->addr, buf, len,
1185 MEMTXATTRS_UNSPECIFIED);
1186 trace_pl330_exec_cycle(q->addr, len);
1187 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
1188 pl330_hexdump(buf, len);
1189 }
1190 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag);
1191 if (fifo_res == PL330_FIFO_OK) {
1192 if (q->inc) {
1193 q->addr += len;
1194 }
1195 q->n--;
1196 if (!q->n) {
1197 pl330_queue_remove_insn(&s->read_queue, q);
1198 }
1199 num_exec++;
1200 }
1201 }
1202
1203 /* Execute one instruction from write queue. */
1204 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true);
1205 if (q != NULL) {
1206 int len = q->len - (q->addr & (q->len - 1));
1207
1208 if (q->z) {
1209 for (i = 0; i < len; i++) {
1210 buf[i] = 0;
1211 }
1212 } else {
1213 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag);
1214 }
1215 if (fifo_res == PL330_FIFO_OK || q->z) {
1216 dma_memory_write(s->mem_as, q->addr, buf, len,
1217 MEMTXATTRS_UNSPECIFIED);
1218 trace_pl330_exec_cycle(q->addr, len);
1219 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
1220 pl330_hexdump(buf, len);
1221 }
1222 if (q->inc) {
1223 q->addr += len;
1224 }
1225 num_exec++;
1226 } else if (fifo_res == PL330_FIFO_STALL) {
1227 pl330_fault(&channel->parent->chan[q->tag],
1228 PL330_FAULT_FIFOEMPTY_ERR);
1229 }
1230 q->n--;
1231 if (!q->n) {
1232 pl330_queue_remove_insn(&s->write_queue, q);
1233 }
1234 }
1235
1236 return num_exec;
1237 }
1238
1239 static int pl330_exec_channel(PL330Chan *channel)
1240 {
1241 int insr_exec = 0;
1242
1243 /* TODO: Is it all right to execute everything or should we do per-cycle
1244 simulation? */
1245 while (pl330_exec_cycle(channel)) {
1246 insr_exec++;
1247 }
1248
1249 /* Detect deadlock */
1250 if (channel->state == pl330_chan_executing) {
1251 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR);
1252 }
1253 /* Situation when one of the queues has deadlocked but all channels
1254 * have finished their programs should be impossible.
1255 */
1256
1257 return insr_exec;
1258 }
1259
1260 static inline void pl330_exec(PL330State *s)
1261 {
1262 int i, insr_exec;
1263 trace_pl330_exec();
1264 do {
1265 insr_exec = pl330_exec_channel(&s->manager);
1266
1267 for (i = 0; i < s->num_chnls; i++) {
1268 insr_exec += pl330_exec_channel(&s->chan[i]);
1269 }
1270 } while (insr_exec);
1271 }
1272
1273 static void pl330_exec_cycle_timer(void *opaque)
1274 {
1275 PL330State *s = (PL330State *)opaque;
1276 pl330_exec(s);
1277 }
1278
1279 /* Stop or restore dma operations */
1280
1281 static void pl330_dma_stop_irq(void *opaque, int irq, int level)
1282 {
1283 PL330State *s = (PL330State *)opaque;
1284
1285 if (s->periph_busy[irq] != level) {
1286 s->periph_busy[irq] = level;
1287 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
1288 }
1289 }
1290
1291 static void pl330_debug_exec(PL330State *s)
1292 {
1293 uint8_t args[5];
1294 uint8_t opcode;
1295 uint8_t chan_id;
1296 int i;
1297 PL330Chan *ch;
1298 const PL330InsnDesc *insn;
1299
1300 s->debug_status = 1;
1301 chan_id = (s->dbg[0] >> 8) & 0x07;
1302 opcode = (s->dbg[0] >> 16) & 0xff;
1303 args[0] = (s->dbg[0] >> 24) & 0xff;
1304 args[1] = (s->dbg[1] >> 0) & 0xff;
1305 args[2] = (s->dbg[1] >> 8) & 0xff;
1306 args[3] = (s->dbg[1] >> 16) & 0xff;
1307 args[4] = (s->dbg[1] >> 24) & 0xff;
1308 trace_pl330_debug_exec(chan_id);
1309 if (s->dbg[0] & 1) {
1310 ch = &s->chan[chan_id];
1311 } else {
1312 ch = &s->manager;
1313 }
1314 insn = NULL;
1315 for (i = 0; debug_insn_desc[i].size; i++) {
1316 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) {
1317 insn = &debug_insn_desc[i];
1318 }
1319 }
1320 if (!insn) {
1321 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR);
1322 return;
1323 }
1324 ch->stall = 0;
1325 insn->exec(ch, opcode, args, insn->size - 1);
1326 if (ch->fault_type) {
1327 ch->fault_type |= PL330_FAULT_DBG_INSTR;
1328 }
1329 if (ch->stall) {
1330 trace_pl330_debug_exec_stall();
1331 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not "
1332 "implemented\n");
1333 }
1334 s->debug_status = 0;
1335 }
1336
1337 /* IOMEM mapped registers */
1338
1339 static void pl330_iomem_write(void *opaque, hwaddr offset,
1340 uint64_t value, unsigned size)
1341 {
1342 PL330State *s = (PL330State *) opaque;
1343 int i;
1344
1345 trace_pl330_iomem_write((unsigned)offset, (unsigned)value);
1346
1347 switch (offset) {
1348 case PL330_REG_INTEN:
1349 s->inten = value;
1350 break;
1351 case PL330_REG_INTCLR:
1352 for (i = 0; i < s->num_events; i++) {
1353 if (s->int_status & s->inten & value & (1 << i)) {
1354 trace_pl330_iomem_write_clr(i);
1355 qemu_irq_lower(s->irq[i]);
1356 }
1357 }
1358 s->ev_status &= ~(value & s->inten);
1359 s->int_status &= ~(value & s->inten);
1360 break;
1361 case PL330_REG_DBGCMD:
1362 if ((value & 3) == 0) {
1363 pl330_debug_exec(s);
1364 pl330_exec(s);
1365 } else {
1366 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
1367 "for offset " HWADDR_FMT_plx "\n", (unsigned)value,
1368 offset);
1369 }
1370 break;
1371 case PL330_REG_DBGINST0:
1372 s->dbg[0] = value;
1373 break;
1374 case PL330_REG_DBGINST1:
1375 s->dbg[1] = value;
1376 break;
1377 default:
1378 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx
1379 "\n", offset);
1380 break;
1381 }
1382 }
1383
1384 static inline uint32_t pl330_iomem_read_imp(void *opaque,
1385 hwaddr offset)
1386 {
1387 PL330State *s = (PL330State *)opaque;
1388 int chan_id;
1389 int i;
1390 uint32_t res;
1391
1392 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) {
1393 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2];
1394 }
1395 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) {
1396 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2];
1397 }
1398 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) {
1399 offset -= PL330_REG_CHANCTRL;
1400 chan_id = offset >> 5;
1401 if (chan_id >= s->num_chnls) {
1402 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1403 HWADDR_FMT_plx "\n", offset);
1404 return 0;
1405 }
1406 switch (offset & 0x1f) {
1407 case 0x00:
1408 return s->chan[chan_id].src;
1409 case 0x04:
1410 return s->chan[chan_id].dst;
1411 case 0x08:
1412 return s->chan[chan_id].control;
1413 case 0x0C:
1414 return s->chan[chan_id].lc[0];
1415 case 0x10:
1416 return s->chan[chan_id].lc[1];
1417 default:
1418 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1419 HWADDR_FMT_plx "\n", offset);
1420 return 0;
1421 }
1422 }
1423 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) {
1424 offset -= PL330_REG_CSR_BASE;
1425 chan_id = offset >> 3;
1426 if (chan_id >= s->num_chnls) {
1427 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1428 HWADDR_FMT_plx "\n", offset);
1429 return 0;
1430 }
1431 switch ((offset >> 2) & 1) {
1432 case 0x0:
1433 res = (s->chan[chan_id].ns << 21) |
1434 (s->chan[chan_id].wakeup << 4) |
1435 (s->chan[chan_id].state) |
1436 (s->chan[chan_id].wfp_sbp << 14);
1437 return res;
1438 case 0x1:
1439 return s->chan[chan_id].pc;
1440 default:
1441 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n");
1442 return 0;
1443 }
1444 }
1445 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) {
1446 offset -= PL330_REG_FTR_BASE;
1447 chan_id = offset >> 2;
1448 if (chan_id >= s->num_chnls) {
1449 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1450 HWADDR_FMT_plx "\n", offset);
1451 return 0;
1452 }
1453 return s->chan[chan_id].fault_type;
1454 }
1455 switch (offset) {
1456 case PL330_REG_DSR:
1457 return (s->manager.ns << 9) | (s->manager.wakeup << 4) |
1458 (s->manager.state & 0xf);
1459 case PL330_REG_DPC:
1460 return s->manager.pc;
1461 case PL330_REG_INTEN:
1462 return s->inten;
1463 case PL330_REG_INT_EVENT_RIS:
1464 return s->ev_status;
1465 case PL330_REG_INTMIS:
1466 return s->int_status;
1467 case PL330_REG_INTCLR:
1468 /* Documentation says that we can't read this register
1469 * but linux kernel does it
1470 */
1471 return 0;
1472 case PL330_REG_FSRD:
1473 return s->manager.state ? 1 : 0;
1474 case PL330_REG_FSRC:
1475 res = 0;
1476 for (i = 0; i < s->num_chnls; i++) {
1477 if (s->chan[i].state == pl330_chan_fault ||
1478 s->chan[i].state == pl330_chan_fault_completing) {
1479 res |= 1 << i;
1480 }
1481 }
1482 return res;
1483 case PL330_REG_FTRD:
1484 return s->manager.fault_type;
1485 case PL330_REG_DBGSTATUS:
1486 return s->debug_status;
1487 default:
1488 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1489 HWADDR_FMT_plx "\n", offset);
1490 }
1491 return 0;
1492 }
1493
1494 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset,
1495 unsigned size)
1496 {
1497 uint32_t ret = pl330_iomem_read_imp(opaque, offset);
1498 trace_pl330_iomem_read((uint32_t)offset, ret);
1499 return ret;
1500 }
1501
1502 static const MemoryRegionOps pl330_ops = {
1503 .read = pl330_iomem_read,
1504 .write = pl330_iomem_write,
1505 .endianness = DEVICE_NATIVE_ENDIAN,
1506 .impl = {
1507 .min_access_size = 4,
1508 .max_access_size = 4,
1509 }
1510 };
1511
1512 /* Controller logic and initialization */
1513
1514 static void pl330_chan_reset(PL330Chan *ch)
1515 {
1516 ch->src = 0;
1517 ch->dst = 0;
1518 ch->pc = 0;
1519 ch->state = pl330_chan_stopped;
1520 ch->watchdog_timer = 0;
1521 ch->stall = 0;
1522 ch->control = 0;
1523 ch->status = 0;
1524 ch->fault_type = 0;
1525 }
1526
1527 static void pl330_reset(DeviceState *d)
1528 {
1529 int i;
1530 PL330State *s = PL330(d);
1531
1532 s->inten = 0;
1533 s->int_status = 0;
1534 s->ev_status = 0;
1535 s->debug_status = 0;
1536 s->num_faulting = 0;
1537 s->manager.ns = s->mgr_ns_at_rst;
1538 pl330_fifo_reset(&s->fifo);
1539 pl330_queue_reset(&s->read_queue);
1540 pl330_queue_reset(&s->write_queue);
1541
1542 for (i = 0; i < s->num_chnls; i++) {
1543 pl330_chan_reset(&s->chan[i]);
1544 }
1545 for (i = 0; i < s->num_periph_req; i++) {
1546 s->periph_busy[i] = 0;
1547 }
1548
1549 timer_del(s->timer);
1550 }
1551
1552 static void pl330_realize(DeviceState *dev, Error **errp)
1553 {
1554 int i;
1555 PL330State *s = PL330(dev);
1556
1557 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
1558 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s,
1559 "dma", PL330_IOMEM_SIZE);
1560 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1561
1562 if (!s->mem_mr) {
1563 error_setg(errp, "'memory' link is not set");
1564 return;
1565 } else if (s->mem_mr == get_system_memory()) {
1566 /* Avoid creating new AS for system memory. */
1567 s->mem_as = &address_space_memory;
1568 } else {
1569 s->mem_as = g_new0(AddressSpace, 1);
1570 address_space_init(s->mem_as, s->mem_mr,
1571 memory_region_name(s->mem_mr));
1572 }
1573
1574 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);
1575
1576 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
1577 (s->num_periph_req > 0 ? 1 : 0) |
1578 ((s->num_chnls - 1) & 0x7) << 4 |
1579 ((s->num_periph_req - 1) & 0x1f) << 12 |
1580 ((s->num_events - 1) & 0x1f) << 17;
1581
1582 switch (s->i_cache_len) {
1583 case (4):
1584 s->cfg[1] |= 2;
1585 break;
1586 case (8):
1587 s->cfg[1] |= 3;
1588 break;
1589 case (16):
1590 s->cfg[1] |= 4;
1591 break;
1592 case (32):
1593 s->cfg[1] |= 5;
1594 break;
1595 default:
1596 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8,
1597 s->i_cache_len);
1598 return;
1599 }
1600 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4;
1601
1602 s->chan = g_new0(PL330Chan, s->num_chnls);
1603 s->hi_seqn = g_new0(uint8_t, s->num_chnls);
1604 s->lo_seqn = g_new0(uint8_t, s->num_chnls);
1605 for (i = 0; i < s->num_chnls; i++) {
1606 s->chan[i].parent = s;
1607 s->chan[i].tag = (uint8_t)i;
1608 }
1609 s->manager.parent = s;
1610 s->manager.tag = s->num_chnls;
1611 s->manager.is_manager = true;
1612
1613 s->irq = g_new0(qemu_irq, s->num_events);
1614 for (i = 0; i < s->num_events; i++) {
1615 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1616 }
1617
1618 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM);
1619
1620 switch (s->data_width) {
1621 case (32):
1622 s->cfg[CFG_CRD] |= 0x2;
1623 break;
1624 case (64):
1625 s->cfg[CFG_CRD] |= 0x3;
1626 break;
1627 case (128):
1628 s->cfg[CFG_CRD] |= 0x4;
1629 break;
1630 default:
1631 error_setg(errp, "Bad value for data_width property: %" PRIx8,
1632 s->data_width);
1633 return;
1634 }
1635
1636 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 |
1637 ((s->wr_q_dep - 1) & 0xf) << 8 |
1638 ((s->rd_cap - 1) & 0x7) << 12 |
1639 ((s->rd_q_dep - 1) & 0xf) << 16 |
1640 ((s->data_buffer_dep - 1) & 0x1ff) << 20;
1641
1642 pl330_queue_init(&s->read_queue, s->rd_q_dep, s);
1643 pl330_queue_init(&s->write_queue, s->wr_q_dep, s);
1644 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep);
1645 }
1646
1647 static const Property pl330_properties[] = {
1648 /* CR0 */
1649 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8),
1650 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4),
1651 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16),
1652 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0),
1653 /* CR1 */
1654 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4),
1655 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8),
1656 /* CR2-4 */
1657 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0),
1658 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0),
1659 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0),
1660 /* CRD */
1661 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64),
1662 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8),
1663 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16),
1664 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8),
1665 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),
1666 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256),
1667
1668 DEFINE_PROP_LINK("memory", PL330State, mem_mr,
1669 TYPE_MEMORY_REGION, MemoryRegion *),
1670 };
1671
1672 static void pl330_class_init(ObjectClass *klass, const void *data)
1673 {
1674 DeviceClass *dc = DEVICE_CLASS(klass);
1675
1676 dc->realize = pl330_realize;
1677 device_class_set_legacy_reset(dc, pl330_reset);
1678 device_class_set_props(dc, pl330_properties);
1679 dc->vmsd = &vmstate_pl330;
1680 }
1681
1682 static const TypeInfo pl330_type_info = {
1683 .name = TYPE_PL330,
1684 .parent = TYPE_SYS_BUS_DEVICE,
1685 .instance_size = sizeof(PL330State),
1686 .class_init = pl330_class_init,
1687 };
1688
1689 static void pl330_register_types(void)
1690 {
1691 type_register_static(&pl330_type_info);
1692 }
1693
1694 type_init(pl330_register_types)