| 1 | /* |
| 2 | * TI OMAP processors GPIO emulation. |
| 3 | * |
| 4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 or |
| 10 | * (at your option) version 3 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/log.h" |
| 23 | #include "hw/core/irq.h" |
| 24 | #include "hw/core/qdev-properties.h" |
| 25 | #include "hw/arm/omap.h" |
| 26 | #include "hw/core/sysbus.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "qapi/error.h" |
| 30 | |
| 31 | struct omap_gpio_s { |
| 32 | qemu_irq irq; |
| 33 | qemu_irq handler[16]; |
| 34 | |
| 35 | uint16_t inputs; |
| 36 | uint16_t outputs; |
| 37 | uint16_t dir; |
| 38 | uint16_t edge; |
| 39 | uint16_t mask; |
| 40 | uint16_t ints; |
| 41 | uint16_t pins; |
| 42 | }; |
| 43 | |
| 44 | struct Omap1GpioState { |
| 45 | SysBusDevice parent_obj; |
| 46 | |
| 47 | MemoryRegion iomem; |
| 48 | void *clk; |
| 49 | struct omap_gpio_s omap1; |
| 50 | }; |
| 51 | |
| 52 | /* General-Purpose I/O of OMAP1 */ |
| 53 | static void omap_gpio_set(void *opaque, int line, int level) |
| 54 | { |
| 55 | Omap1GpioState *p = opaque; |
| 56 | struct omap_gpio_s *s = &p->omap1; |
| 57 | uint16_t prev = s->inputs; |
| 58 | |
| 59 | if (level) |
| 60 | s->inputs |= 1 << line; |
| 61 | else |
| 62 | s->inputs &= ~(1 << line); |
| 63 | |
| 64 | if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & |
| 65 | (1 << line) & s->dir & ~s->mask) { |
| 66 | s->ints |= 1 << line; |
| 67 | qemu_irq_raise(s->irq); |
| 68 | } |
| 69 | } |
| 70 | |
| 71 | static uint64_t omap_gpio_read(void *opaque, hwaddr addr, |
| 72 | unsigned size) |
| 73 | { |
| 74 | struct omap_gpio_s *s = opaque; |
| 75 | int offset = addr & OMAP_MPUI_REG_MASK; |
| 76 | |
| 77 | if (size != 2) { |
| 78 | qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx |
| 79 | " with bad width %d\n", __func__, addr, size); |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | switch (offset) { |
| 84 | case 0x00: /* DATA_INPUT */ |
| 85 | return s->inputs & s->pins; |
| 86 | |
| 87 | case 0x04: /* DATA_OUTPUT */ |
| 88 | return s->outputs; |
| 89 | |
| 90 | case 0x08: /* DIRECTION_CONTROL */ |
| 91 | return s->dir; |
| 92 | |
| 93 | case 0x0c: /* INTERRUPT_CONTROL */ |
| 94 | return s->edge; |
| 95 | |
| 96 | case 0x10: /* INTERRUPT_MASK */ |
| 97 | return s->mask; |
| 98 | |
| 99 | case 0x14: /* INTERRUPT_STATUS */ |
| 100 | return s->ints; |
| 101 | |
| 102 | case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
| 103 | OMAP_BAD_REG(addr); |
| 104 | return s->pins; |
| 105 | } |
| 106 | |
| 107 | OMAP_BAD_REG(addr); |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | static void omap_gpio_write(void *opaque, hwaddr addr, |
| 112 | uint64_t value, unsigned size) |
| 113 | { |
| 114 | struct omap_gpio_s *s = opaque; |
| 115 | int offset = addr & OMAP_MPUI_REG_MASK; |
| 116 | uint16_t diff; |
| 117 | int ln; |
| 118 | |
| 119 | if (size != 2) { |
| 120 | qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx |
| 121 | " with bad width %d\n", __func__, addr, size); |
| 122 | return; |
| 123 | } |
| 124 | |
| 125 | switch (offset) { |
| 126 | case 0x00: /* DATA_INPUT */ |
| 127 | OMAP_RO_REG(addr); |
| 128 | return; |
| 129 | |
| 130 | case 0x04: /* DATA_OUTPUT */ |
| 131 | diff = (s->outputs ^ value) & ~s->dir; |
| 132 | s->outputs = value; |
| 133 | while ((ln = ctz32(diff)) != 32) { |
| 134 | if (s->handler[ln]) |
| 135 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
| 136 | diff &= ~(1 << ln); |
| 137 | } |
| 138 | break; |
| 139 | |
| 140 | case 0x08: /* DIRECTION_CONTROL */ |
| 141 | diff = s->outputs & (s->dir ^ value); |
| 142 | s->dir = value; |
| 143 | |
| 144 | value = s->outputs & ~s->dir; |
| 145 | while ((ln = ctz32(diff)) != 32) { |
| 146 | if (s->handler[ln]) |
| 147 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
| 148 | diff &= ~(1 << ln); |
| 149 | } |
| 150 | break; |
| 151 | |
| 152 | case 0x0c: /* INTERRUPT_CONTROL */ |
| 153 | s->edge = value; |
| 154 | break; |
| 155 | |
| 156 | case 0x10: /* INTERRUPT_MASK */ |
| 157 | s->mask = value; |
| 158 | break; |
| 159 | |
| 160 | case 0x14: /* INTERRUPT_STATUS */ |
| 161 | s->ints &= ~value; |
| 162 | if (!s->ints) |
| 163 | qemu_irq_lower(s->irq); |
| 164 | break; |
| 165 | |
| 166 | case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
| 167 | OMAP_BAD_REG(addr); |
| 168 | s->pins = value; |
| 169 | break; |
| 170 | |
| 171 | default: |
| 172 | OMAP_BAD_REG(addr); |
| 173 | return; |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | /* *Some* sources say the memory region is 32-bit. */ |
| 178 | static const MemoryRegionOps omap_gpio_ops = { |
| 179 | .read = omap_gpio_read, |
| 180 | .write = omap_gpio_write, |
| 181 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 182 | }; |
| 183 | |
| 184 | static void omap_gpio_reset(struct omap_gpio_s *s) |
| 185 | { |
| 186 | s->inputs = 0; |
| 187 | s->outputs = ~0; |
| 188 | s->dir = ~0; |
| 189 | s->edge = ~0; |
| 190 | s->mask = ~0; |
| 191 | s->ints = 0; |
| 192 | s->pins = ~0; |
| 193 | } |
| 194 | |
| 195 | static void omap_gpif_reset(DeviceState *dev) |
| 196 | { |
| 197 | Omap1GpioState *s = OMAP1_GPIO(dev); |
| 198 | |
| 199 | omap_gpio_reset(&s->omap1); |
| 200 | } |
| 201 | |
| 202 | static void omap_gpio_init(Object *obj) |
| 203 | { |
| 204 | DeviceState *dev = DEVICE(obj); |
| 205 | Omap1GpioState *s = OMAP1_GPIO(obj); |
| 206 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 207 | |
| 208 | qdev_init_gpio_in(dev, omap_gpio_set, 16); |
| 209 | qdev_init_gpio_out(dev, s->omap1.handler, 16); |
| 210 | sysbus_init_irq(sbd, &s->omap1.irq); |
| 211 | memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1, |
| 212 | "omap.gpio", 0x1000); |
| 213 | sysbus_init_mmio(sbd, &s->iomem); |
| 214 | } |
| 215 | |
| 216 | static void omap_gpio_realize(DeviceState *dev, Error **errp) |
| 217 | { |
| 218 | Omap1GpioState *s = OMAP1_GPIO(dev); |
| 219 | |
| 220 | if (!s->clk) { |
| 221 | error_setg(errp, "omap-gpio: clk not connected"); |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) |
| 226 | { |
| 227 | gpio->clk = clk; |
| 228 | } |
| 229 | |
| 230 | static void omap_gpio_class_init(ObjectClass *klass, const void *data) |
| 231 | { |
| 232 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 233 | |
| 234 | dc->realize = omap_gpio_realize; |
| 235 | device_class_set_legacy_reset(dc, omap_gpif_reset); |
| 236 | /* Reason: pointer property "clk" */ |
| 237 | dc->user_creatable = false; |
| 238 | } |
| 239 | |
| 240 | static const TypeInfo omap_gpio_info = { |
| 241 | .name = TYPE_OMAP1_GPIO, |
| 242 | .parent = TYPE_SYS_BUS_DEVICE, |
| 243 | .instance_size = sizeof(Omap1GpioState), |
| 244 | .instance_init = omap_gpio_init, |
| 245 | .class_init = omap_gpio_class_init, |
| 246 | }; |
| 247 | |
| 248 | static void omap_gpio_register_types(void) |
| 249 | { |
| 250 | type_register_static(&omap_gpio_info); |
| 251 | } |
| 252 | |
| 253 | type_init(omap_gpio_register_types) |