| 1 | /* |
| 2 | * PCA9554 I/O port |
| 3 | * |
| 4 | * Copyright (c) 2023, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "qemu/log.h" |
| 11 | #include "qemu/module.h" |
| 12 | #include "qemu/bitops.h" |
| 13 | #include "hw/core/qdev-properties.h" |
| 14 | #include "hw/gpio/pca9554.h" |
| 15 | #include "hw/gpio/pca9554_regs.h" |
| 16 | #include "hw/core/irq.h" |
| 17 | #include "migration/vmstate.h" |
| 18 | #include "qapi/error.h" |
| 19 | #include "qapi/visitor.h" |
| 20 | #include "trace.h" |
| 21 | #include "qom/object.h" |
| 22 | |
| 23 | struct PCA9554Class { |
| 24 | /*< private >*/ |
| 25 | I2CSlaveClass parent_class; |
| 26 | /*< public >*/ |
| 27 | |
| 28 | uint8_t pin_count; |
| 29 | }; |
| 30 | typedef struct PCA9554Class PCA9554Class; |
| 31 | |
| 32 | DECLARE_CLASS_CHECKERS(PCA9554Class, PCA9554, |
| 33 | TYPE_PCA9554) |
| 34 | |
| 35 | #define PCA9554_PIN_LOW 0x0 |
| 36 | #define PCA9554_PIN_HIZ 0x1 |
| 37 | |
| 38 | static const char *pin_state[] = {"low", "high"}; |
| 39 | |
| 40 | static void pca9554_update_pin_input(PCA9554State *s) |
| 41 | { |
| 42 | PCA9554Class *pc = PCA9554_GET_CLASS(s); |
| 43 | int i; |
| 44 | uint8_t config = s->regs[PCA9554_CONFIG]; |
| 45 | uint8_t output = s->regs[PCA9554_OUTPUT]; |
| 46 | |
| 47 | for (i = 0; i < pc->pin_count; i++) { |
| 48 | uint8_t bit_mask = 1 << i; |
| 49 | uint8_t old_value = s->regs[PCA9554_INPUT] & bit_mask; |
| 50 | uint8_t new_value; |
| 51 | |
| 52 | if (config & bit_mask) { |
| 53 | /* |
| 54 | * Input: the pin is Hi-Z with a pull-up, so it reads high |
| 55 | * unless an external device drives it low. |
| 56 | */ |
| 57 | if (s->ext_state[i] == PCA9554_PIN_LOW) { |
| 58 | s->regs[PCA9554_INPUT] &= ~bit_mask; |
| 59 | } else { |
| 60 | s->regs[PCA9554_INPUT] |= bit_mask; |
| 61 | } |
| 62 | } else { |
| 63 | /* Output: the push-pull stage drives the output register level. */ |
| 64 | s->regs[PCA9554_INPUT] = (s->regs[PCA9554_INPUT] & ~bit_mask) | |
| 65 | (output & bit_mask); |
| 66 | } |
| 67 | |
| 68 | /* drive the per-pin GPIO output only if the pin level changed */ |
| 69 | new_value = s->regs[PCA9554_INPUT] & bit_mask; |
| 70 | if (new_value != old_value) { |
| 71 | qemu_set_irq(s->gpio_out[i], !!new_value); |
| 72 | } |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | static uint8_t pca9554_read(PCA9554State *s, uint8_t reg) |
| 77 | { |
| 78 | switch (reg) { |
| 79 | case PCA9554_INPUT: |
| 80 | return s->regs[PCA9554_INPUT] ^ s->regs[PCA9554_POLARITY]; |
| 81 | case PCA9554_OUTPUT: |
| 82 | case PCA9554_POLARITY: |
| 83 | case PCA9554_CONFIG: |
| 84 | return s->regs[reg]; |
| 85 | default: |
| 86 | qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read to register %d\n", |
| 87 | __func__, reg); |
| 88 | return 0xFF; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | static void pca9554_write(PCA9554State *s, uint8_t reg, uint8_t data) |
| 93 | { |
| 94 | PCA9554Class *pc = PCA9554_GET_CLASS(s); |
| 95 | uint8_t pin_mask = (1 << pc->pin_count) - 1; |
| 96 | |
| 97 | /* Variants narrower than 8 bits ignore the unimplemented upper pins. */ |
| 98 | data &= pin_mask; |
| 99 | |
| 100 | switch (reg) { |
| 101 | case PCA9554_OUTPUT: |
| 102 | case PCA9554_CONFIG: |
| 103 | s->regs[reg] = data; |
| 104 | pca9554_update_pin_input(s); |
| 105 | break; |
| 106 | case PCA9554_POLARITY: |
| 107 | s->regs[reg] = data; |
| 108 | break; |
| 109 | case PCA9554_INPUT: |
| 110 | default: |
| 111 | qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %d\n", |
| 112 | __func__, reg); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static uint8_t pca9554_recv(I2CSlave *i2c) |
| 117 | { |
| 118 | PCA9554State *s = PCA9554(i2c); |
| 119 | |
| 120 | return pca9554_read(s, s->pointer & 0x3); |
| 121 | } |
| 122 | |
| 123 | static int pca9554_send(I2CSlave *i2c, uint8_t data) |
| 124 | { |
| 125 | PCA9554State *s = PCA9554(i2c); |
| 126 | |
| 127 | /* First byte sent by is the register address */ |
| 128 | if (s->len == 0) { |
| 129 | s->pointer = data; |
| 130 | s->len++; |
| 131 | } else { |
| 132 | pca9554_write(s, s->pointer & 0x3, data); |
| 133 | } |
| 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | static int pca9554_event(I2CSlave *i2c, enum i2c_event event) |
| 139 | { |
| 140 | PCA9554State *s = PCA9554(i2c); |
| 141 | |
| 142 | s->len = 0; |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static void pca9554_set_ext_state(PCA9554State *s, int pin, int level) |
| 147 | { |
| 148 | if (s->ext_state[pin] != level) { |
| 149 | s->ext_state[pin] = level; |
| 150 | pca9554_update_pin_input(s); |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | static void pca9554_get_pin(Object *obj, Visitor *v, const char *name, |
| 155 | void *opaque, Error **errp) |
| 156 | { |
| 157 | PCA9554State *s = PCA9554(obj); |
| 158 | int pin, rc; |
| 159 | uint8_t state; |
| 160 | |
| 161 | rc = sscanf(name, "pin%2d", &pin); |
| 162 | if (rc != 1) { |
| 163 | error_setg(errp, "%s: error reading %s", __func__, name); |
| 164 | return; |
| 165 | } |
| 166 | if (pin < 0 || pin >= PCA9554_GET_CLASS(s)->pin_count) { |
| 167 | error_setg(errp, "%s invalid pin %s", __func__, name); |
| 168 | return; |
| 169 | } |
| 170 | |
| 171 | /* |
| 172 | * Report the physical pin level. The input register is kept in sync by |
| 173 | * pca9554_update_pin_input(): output pins mirror the OUTPUT register and |
| 174 | * input pins reflect the externally driven (or pulled-up) level, so it |
| 175 | * holds the wire level regardless of the configured direction. |
| 176 | */ |
| 177 | state = (s->regs[PCA9554_INPUT] >> pin) & 0x1; |
| 178 | visit_type_str(v, name, (char **)&pin_state[state], errp); |
| 179 | } |
| 180 | |
| 181 | static void pca9554_set_pin(Object *obj, Visitor *v, const char *name, |
| 182 | void *opaque, Error **errp) |
| 183 | { |
| 184 | PCA9554State *s = PCA9554(obj); |
| 185 | int pin, rc, val; |
| 186 | uint8_t state, mask; |
| 187 | g_autofree char *state_str = NULL; |
| 188 | |
| 189 | if (!visit_type_str(v, name, &state_str, errp)) { |
| 190 | return; |
| 191 | } |
| 192 | rc = sscanf(name, "pin%2d", &pin); |
| 193 | if (rc != 1) { |
| 194 | error_setg(errp, "%s: error reading %s", __func__, name); |
| 195 | return; |
| 196 | } |
| 197 | if (pin < 0 || pin >= PCA9554_GET_CLASS(s)->pin_count) { |
| 198 | error_setg(errp, "%s invalid pin %s", __func__, name); |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | for (state = 0; state < ARRAY_SIZE(pin_state); state++) { |
| 203 | if (!strcmp(state_str, pin_state[state])) { |
| 204 | break; |
| 205 | } |
| 206 | } |
| 207 | if (state >= ARRAY_SIZE(pin_state)) { |
| 208 | error_setg(errp, "%s invalid pin state %s", __func__, state_str); |
| 209 | return; |
| 210 | } |
| 211 | |
| 212 | if (s->hw_dir) { |
| 213 | /* Warn and ignore if the guest has configured this pin as output */ |
| 214 | if (!((s->regs[PCA9554_CONFIG] >> pin) & 0x1)) { |
| 215 | qemu_log_mask(LOG_UNIMP, |
| 216 | "%s: pin %d is configured as output, " |
| 217 | "ignoring external set\n", |
| 218 | s->description, pin); |
| 219 | return; |
| 220 | } |
| 221 | /* Drive the external input level */ |
| 222 | pca9554_set_ext_state(s, pin, state != PCA9554_PIN_LOW); |
| 223 | } else { |
| 224 | /* Legacy behavior: force output mode and drive */ |
| 225 | /* First, modify the output register bit */ |
| 226 | val = pca9554_read(s, PCA9554_OUTPUT); |
| 227 | mask = 0x1 << pin; |
| 228 | if (state == PCA9554_PIN_LOW) { |
| 229 | val &= ~(mask); |
| 230 | } else { |
| 231 | val |= mask; |
| 232 | } |
| 233 | pca9554_write(s, PCA9554_OUTPUT, val); |
| 234 | |
| 235 | /* Then, clear the config register bit for output mode */ |
| 236 | val = pca9554_read(s, PCA9554_CONFIG); |
| 237 | val &= ~mask; |
| 238 | pca9554_write(s, PCA9554_CONFIG, val); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | static const VMStateDescription pca9554_vmstate = { |
| 243 | .name = "PCA9554", |
| 244 | .version_id = 0, |
| 245 | .minimum_version_id = 0, |
| 246 | .fields = (VMStateField[]) { |
| 247 | VMSTATE_UINT8(len, PCA9554State), |
| 248 | VMSTATE_UINT8(pointer, PCA9554State), |
| 249 | VMSTATE_UINT8_ARRAY(regs, PCA9554State, PCA9554_NR_REGS), |
| 250 | VMSTATE_UINT8_ARRAY(ext_state, PCA9554State, PCA9554_PIN_COUNT), |
| 251 | VMSTATE_I2C_SLAVE(i2c, PCA9554State), |
| 252 | VMSTATE_END_OF_LIST() |
| 253 | } |
| 254 | }; |
| 255 | |
| 256 | static void pca9554_reset(DeviceState *dev) |
| 257 | { |
| 258 | PCA9554State *s = PCA9554(dev); |
| 259 | PCA9554Class *pc = PCA9554_GET_CLASS(s); |
| 260 | uint8_t pin_mask = (1 << pc->pin_count) - 1; |
| 261 | |
| 262 | s->regs[PCA9554_INPUT] = pin_mask; |
| 263 | s->regs[PCA9554_OUTPUT] = pin_mask; |
| 264 | s->regs[PCA9554_POLARITY] = 0x0; /* No pins are inverted */ |
| 265 | s->regs[PCA9554_CONFIG] = pin_mask; /* All pins are inputs */ |
| 266 | |
| 267 | memset(s->ext_state, PCA9554_PIN_HIZ, pc->pin_count); |
| 268 | pca9554_update_pin_input(s); |
| 269 | |
| 270 | s->pointer = 0x0; |
| 271 | s->len = 0; |
| 272 | } |
| 273 | |
| 274 | static void pca9554_initfn(Object *obj) |
| 275 | { |
| 276 | PCA9554Class *pc = PCA9554_GET_CLASS(obj); |
| 277 | int pin; |
| 278 | |
| 279 | for (pin = 0; pin < pc->pin_count; pin++) { |
| 280 | char *name; |
| 281 | |
| 282 | name = g_strdup_printf("pin%d", pin); |
| 283 | object_property_add(obj, name, "str", pca9554_get_pin, pca9554_set_pin, |
| 284 | NULL, NULL); |
| 285 | g_free(name); |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | static void pca9554_gpio_in_handler(void *opaque, int pin, int level) |
| 290 | { |
| 291 | PCA9554State *s = PCA9554(opaque); |
| 292 | PCA9554Class *pc = PCA9554_GET_CLASS(s); |
| 293 | |
| 294 | assert((pin >= 0) && (pin < pc->pin_count)); |
| 295 | pca9554_set_ext_state(s, pin, level); |
| 296 | } |
| 297 | |
| 298 | static void pca9554_realize(DeviceState *dev, Error **errp) |
| 299 | { |
| 300 | PCA9554State *s = PCA9554(dev); |
| 301 | PCA9554Class *pc = PCA9554_GET_CLASS(s); |
| 302 | |
| 303 | if (!s->description) { |
| 304 | s->description = g_strdup(object_get_typename(OBJECT(dev))); |
| 305 | } |
| 306 | |
| 307 | qdev_init_gpio_out(dev, s->gpio_out, pc->pin_count); |
| 308 | qdev_init_gpio_in(dev, pca9554_gpio_in_handler, pc->pin_count); |
| 309 | } |
| 310 | |
| 311 | static const Property pca9554_properties[] = { |
| 312 | DEFINE_PROP_STRING("description", PCA9554State, description), |
| 313 | DEFINE_PROP_BOOL("hw-dir", PCA9554State, hw_dir, false), |
| 314 | }; |
| 315 | |
| 316 | static void pca9554_class_init(ObjectClass *klass, const void *data) |
| 317 | { |
| 318 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 319 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); |
| 320 | PCA9554Class *pc = PCA9554_CLASS(klass); |
| 321 | |
| 322 | k->event = pca9554_event; |
| 323 | k->recv = pca9554_recv; |
| 324 | k->send = pca9554_send; |
| 325 | dc->realize = pca9554_realize; |
| 326 | device_class_set_legacy_reset(dc, pca9554_reset); |
| 327 | dc->vmsd = &pca9554_vmstate; |
| 328 | device_class_set_props(dc, pca9554_properties); |
| 329 | |
| 330 | pc->pin_count = PCA9554_PIN_COUNT; |
| 331 | } |
| 332 | |
| 333 | static void pca9536_class_init(ObjectClass *klass, const void *data) |
| 334 | { |
| 335 | PCA9554Class *pc = PCA9554_CLASS(klass); |
| 336 | |
| 337 | pc->pin_count = PCA9536_PIN_COUNT; |
| 338 | } |
| 339 | |
| 340 | static const TypeInfo pca9554_types[] = { |
| 341 | { |
| 342 | .name = TYPE_PCA9554, |
| 343 | .parent = TYPE_I2C_SLAVE, |
| 344 | .instance_init = pca9554_initfn, |
| 345 | .instance_size = sizeof(PCA9554State), |
| 346 | .class_init = pca9554_class_init, |
| 347 | .class_size = sizeof(PCA9554Class), |
| 348 | .abstract = false, |
| 349 | }, |
| 350 | { |
| 351 | .name = TYPE_PCA9536, |
| 352 | .parent = TYPE_PCA9554, |
| 353 | .class_init = pca9536_class_init, |
| 354 | } |
| 355 | }; |
| 356 | |
| 357 | DEFINE_TYPES(pca9554_types); |