| 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 2 | |
| 3 | # imx_gpio.c |
| 4 | imx_gpio_read(const char *id, const char *reg, uint32_t value) "%s:[%s] -> 0x%" PRIx32 |
| 5 | imx_gpio_write(const char *id, const char *reg, uint32_t value) "%s:[%s] <- 0x%" PRIx32 |
| 6 | imx_gpio_set(const char *id, int line, int level) "%s:[%d] <- %d" |
| 7 | |
| 8 | # npcm7xx_gpio.c |
| 9 | npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| 10 | npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| 11 | npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32 |
| 12 | npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32 |
| 13 | npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32 |
| 14 | |
| 15 | # nrf51_gpio.c |
| 16 | nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 17 | nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 18 | nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |
| 19 | nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |
| 20 | |
| 21 | # pca9552.c |
| 22 | pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" |
| 23 | pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" |
| 24 | |
| 25 | # pl061.c |
| 26 | pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x" |
| 27 | pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d" |
| 28 | pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d" |
| 29 | pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" |
| 30 | pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 31 | pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 32 | pl061_reset(const char *id) "%s reset" |
| 33 | |
| 34 | # sifive_gpio.c |
| 35 | sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 36 | sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 37 | sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |
| 38 | sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |
| 39 | |
| 40 | # aspeed_gpio.c |
| 41 | aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 |
| 42 | aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 |
| 43 | |
| 44 | # stm32l4x5_gpio.c |
| 45 | stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " " |
| 46 | stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 47 | stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x" |
| 48 | stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x" |
| 49 | |
| 50 | # cadence_gpio.c |
| 51 | cdns_gpio_read(const char *path, uint64_t offset, uint32_t value) "%s:reg[0x%04" PRIx64 "] -> 0x%" PRIx32 |
| 52 | cdns_gpio_write(const char *path, uint64_t offset, uint64_t value) "%s:reg[0x%04" PRIx64 "] <- 0x%04" PRIx64 |
| 53 | cdns_gpio_set(const char *path, int line, int level) "%s:[%d] <- %d" |