| 1 | /* |
| 2 | * Copyright (c) 2006-2008 Openedhand Ltd. |
| 3 | * Written by Andrzej Zaborowski <balrog@zabor.org> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 or |
| 8 | * (at your option) version 3 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "hw/core/irq.h" |
| 21 | #include "hw/core/sysbus.h" |
| 22 | #include "migration/vmstate.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "qemu/log.h" |
| 25 | #include "qom/object.h" |
| 26 | |
| 27 | /* SCOOP devices */ |
| 28 | |
| 29 | #define TYPE_SCOOP "scoop" |
| 30 | OBJECT_DECLARE_SIMPLE_TYPE(ScoopInfo, SCOOP) |
| 31 | |
| 32 | struct ScoopInfo { |
| 33 | SysBusDevice parent_obj; |
| 34 | |
| 35 | qemu_irq handler[16]; |
| 36 | MemoryRegion iomem; |
| 37 | uint16_t status; |
| 38 | uint16_t power; |
| 39 | uint32_t gpio_level; |
| 40 | uint32_t gpio_dir; |
| 41 | uint32_t prev_level; |
| 42 | |
| 43 | uint16_t mcr; |
| 44 | uint16_t cdr; |
| 45 | uint16_t ccr; |
| 46 | uint16_t irr; |
| 47 | uint16_t imr; |
| 48 | uint16_t isr; |
| 49 | }; |
| 50 | |
| 51 | #define SCOOP_MCR 0x00 |
| 52 | #define SCOOP_CDR 0x04 |
| 53 | #define SCOOP_CSR 0x08 |
| 54 | #define SCOOP_CPR 0x0c |
| 55 | #define SCOOP_CCR 0x10 |
| 56 | #define SCOOP_IRR_IRM 0x14 |
| 57 | #define SCOOP_IMR 0x18 |
| 58 | #define SCOOP_ISR 0x1c |
| 59 | #define SCOOP_GPCR 0x20 |
| 60 | #define SCOOP_GPWR 0x24 |
| 61 | #define SCOOP_GPRR 0x28 |
| 62 | |
| 63 | static inline void scoop_gpio_handler_update(ScoopInfo *s) |
| 64 | { |
| 65 | uint32_t level, diff; |
| 66 | int bit; |
| 67 | level = s->gpio_level & s->gpio_dir; |
| 68 | |
| 69 | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
| 70 | bit = ctz32(diff); |
| 71 | qemu_set_irq(s->handler[bit], (level >> bit) & 1); |
| 72 | } |
| 73 | |
| 74 | s->prev_level = level; |
| 75 | } |
| 76 | |
| 77 | static uint64_t scoop_read(void *opaque, hwaddr addr, |
| 78 | unsigned size) |
| 79 | { |
| 80 | ScoopInfo *s = (ScoopInfo *) opaque; |
| 81 | |
| 82 | switch (addr & 0x3f) { |
| 83 | case SCOOP_MCR: |
| 84 | return s->mcr; |
| 85 | case SCOOP_CDR: |
| 86 | return s->cdr; |
| 87 | case SCOOP_CSR: |
| 88 | return s->status; |
| 89 | case SCOOP_CPR: |
| 90 | return s->power; |
| 91 | case SCOOP_CCR: |
| 92 | return s->ccr; |
| 93 | case SCOOP_IRR_IRM: |
| 94 | return s->irr; |
| 95 | case SCOOP_IMR: |
| 96 | return s->imr; |
| 97 | case SCOOP_ISR: |
| 98 | return s->isr; |
| 99 | case SCOOP_GPCR: |
| 100 | return s->gpio_dir; |
| 101 | case SCOOP_GPWR: |
| 102 | case SCOOP_GPRR: |
| 103 | return s->gpio_level; |
| 104 | default: |
| 105 | qemu_log_mask(LOG_GUEST_ERROR, |
| 106 | "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n", |
| 107 | addr); |
| 108 | } |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | static void scoop_write(void *opaque, hwaddr addr, |
| 114 | uint64_t value, unsigned size) |
| 115 | { |
| 116 | ScoopInfo *s = (ScoopInfo *) opaque; |
| 117 | value &= 0xffff; |
| 118 | |
| 119 | switch (addr & 0x3f) { |
| 120 | case SCOOP_MCR: |
| 121 | s->mcr = value; |
| 122 | break; |
| 123 | case SCOOP_CDR: |
| 124 | s->cdr = value; |
| 125 | break; |
| 126 | case SCOOP_CPR: |
| 127 | s->power = value; |
| 128 | if (value & 0x80) { |
| 129 | s->power |= 0x8040; |
| 130 | } |
| 131 | break; |
| 132 | case SCOOP_CCR: |
| 133 | s->ccr = value; |
| 134 | break; |
| 135 | case SCOOP_IRR_IRM: |
| 136 | s->irr = value; |
| 137 | break; |
| 138 | case SCOOP_IMR: |
| 139 | s->imr = value; |
| 140 | break; |
| 141 | case SCOOP_ISR: |
| 142 | s->isr = value; |
| 143 | break; |
| 144 | case SCOOP_GPCR: |
| 145 | s->gpio_dir = value; |
| 146 | scoop_gpio_handler_update(s); |
| 147 | break; |
| 148 | case SCOOP_GPWR: |
| 149 | case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ |
| 150 | s->gpio_level = value & s->gpio_dir; |
| 151 | scoop_gpio_handler_update(s); |
| 152 | break; |
| 153 | default: |
| 154 | qemu_log_mask(LOG_GUEST_ERROR, |
| 155 | "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n", |
| 156 | addr); |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | static const MemoryRegionOps scoop_ops = { |
| 161 | .read = scoop_read, |
| 162 | .write = scoop_write, |
| 163 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 164 | }; |
| 165 | |
| 166 | static void scoop_gpio_set(void *opaque, int line, int level) |
| 167 | { |
| 168 | ScoopInfo *s = (ScoopInfo *) opaque; |
| 169 | |
| 170 | if (level) { |
| 171 | s->gpio_level |= (1 << line); |
| 172 | } else { |
| 173 | s->gpio_level &= ~(1 << line); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | static void scoop_init(Object *obj) |
| 178 | { |
| 179 | DeviceState *dev = DEVICE(obj); |
| 180 | ScoopInfo *s = SCOOP(obj); |
| 181 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 182 | |
| 183 | s->status = 0x02; |
| 184 | qdev_init_gpio_out(dev, s->handler, 16); |
| 185 | qdev_init_gpio_in(dev, scoop_gpio_set, 16); |
| 186 | memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000); |
| 187 | |
| 188 | sysbus_init_mmio(sbd, &s->iomem); |
| 189 | } |
| 190 | |
| 191 | static int scoop_post_load(void *opaque, int version_id) |
| 192 | { |
| 193 | ScoopInfo *s = (ScoopInfo *) opaque; |
| 194 | int i; |
| 195 | uint32_t level; |
| 196 | |
| 197 | level = s->gpio_level & s->gpio_dir; |
| 198 | |
| 199 | for (i = 0; i < 16; i++) { |
| 200 | qemu_set_irq(s->handler[i], (level >> i) & 1); |
| 201 | } |
| 202 | |
| 203 | s->prev_level = level; |
| 204 | |
| 205 | return 0; |
| 206 | } |
| 207 | |
| 208 | static bool is_version_0(void *opaque, int version_id) |
| 209 | { |
| 210 | return version_id == 0; |
| 211 | } |
| 212 | |
| 213 | static bool vmstate_scoop_validate(void *opaque, int version_id) |
| 214 | { |
| 215 | ScoopInfo *s = opaque; |
| 216 | |
| 217 | return !(s->prev_level & 0xffff0000) && |
| 218 | !(s->gpio_level & 0xffff0000) && |
| 219 | !(s->gpio_dir & 0xffff0000); |
| 220 | } |
| 221 | |
| 222 | static const VMStateDescription vmstate_scoop_regs = { |
| 223 | .name = "scoop", |
| 224 | .version_id = 1, |
| 225 | .minimum_version_id = 0, |
| 226 | .post_load = scoop_post_load, |
| 227 | .fields = (const VMStateField[]) { |
| 228 | VMSTATE_UINT16(status, ScoopInfo), |
| 229 | VMSTATE_UINT16(power, ScoopInfo), |
| 230 | VMSTATE_UINT32(gpio_level, ScoopInfo), |
| 231 | VMSTATE_UINT32(gpio_dir, ScoopInfo), |
| 232 | VMSTATE_UINT32(prev_level, ScoopInfo), |
| 233 | VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate), |
| 234 | VMSTATE_UINT16(mcr, ScoopInfo), |
| 235 | VMSTATE_UINT16(cdr, ScoopInfo), |
| 236 | VMSTATE_UINT16(ccr, ScoopInfo), |
| 237 | VMSTATE_UINT16(irr, ScoopInfo), |
| 238 | VMSTATE_UINT16(imr, ScoopInfo), |
| 239 | VMSTATE_UINT16(isr, ScoopInfo), |
| 240 | VMSTATE_UNUSED_TEST(is_version_0, 2), |
| 241 | VMSTATE_END_OF_LIST(), |
| 242 | }, |
| 243 | }; |
| 244 | |
| 245 | static void scoop_sysbus_class_init(ObjectClass *klass, const void *data) |
| 246 | { |
| 247 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 248 | |
| 249 | dc->desc = "Scoop2 Sharp custom ASIC"; |
| 250 | dc->vmsd = &vmstate_scoop_regs; |
| 251 | } |
| 252 | |
| 253 | static const TypeInfo scoop_sysbus_info = { |
| 254 | .name = TYPE_SCOOP, |
| 255 | .parent = TYPE_SYS_BUS_DEVICE, |
| 256 | .instance_size = sizeof(ScoopInfo), |
| 257 | .instance_init = scoop_init, |
| 258 | .class_init = scoop_sysbus_class_init, |
| 259 | }; |
| 260 | |
| 261 | static void scoop_register_types(void) |
| 262 | { |
| 263 | type_register_static(&scoop_sysbus_info); |
| 264 | } |
| 265 | |
| 266 | type_init(scoop_register_types) |