| 1 | /* HPPA cores and system support chips. */ |
| 2 | /* Be aware: QEMU and seabios-hppa repositories share this file as-is. */ |
| 3 | |
| 4 | #ifndef HW_HPPA_HPPA_HARDWARE_H |
| 5 | #define HW_HPPA_HPPA_HARDWARE_H |
| 6 | |
| 7 | #define FIRMWARE_START 0xf0000000 |
| 8 | #define FIRMWARE_END 0xf0100000 |
| 9 | #define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ |
| 10 | |
| 11 | #define RAM_MAP_HIGH1 0x0100000000 /* memory above 4 GB */ |
| 12 | #define RAM_MAP_HIGH2 0x4040000000 /* memory between 1 G and 3.75 GB */ |
| 13 | |
| 14 | #define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ |
| 15 | |
| 16 | #define DEVICE_HPA_LEN 0x00100000 |
| 17 | |
| 18 | #define GSC_HPA 0xffc00000 |
| 19 | #define DINO_HPA 0xfff80000 |
| 20 | #define DINO_UART_HPA 0xfff83000 |
| 21 | #define DINO_UART_BASE 0xfff83800 |
| 22 | #define DINO_SCSI_HPA 0xfff8c000 |
| 23 | #define LASI_HPA_715 0xf0100000 |
| 24 | #define LASI_HPA 0xffd00000 |
| 25 | #define LASI_GFX_HPA 0xf8000000 |
| 26 | #define ARTIST_FB_ADDR 0xf9000000 |
| 27 | #define CPU_HPA 0xfffb0000 |
| 28 | #define MEMORY_HPA 0xfffff000 |
| 29 | |
| 30 | #define IDE_HPA 0xf9000000 /* Boot disc controller */ |
| 31 | #define ASTRO_HPA 0xfed00000 |
| 32 | #define ELROY0_HPA 0xfed30000 |
| 33 | #define ELROY2_HPA 0xfed32000 |
| 34 | #define ELROY8_HPA 0xfed38000 |
| 35 | #define ELROYc_HPA 0xfed3c000 |
| 36 | #define ASTRO_MEMORY_HPA 0xfed10200 |
| 37 | |
| 38 | #define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ |
| 39 | |
| 40 | #define HPA_DISABLED_DEVICE 1 /* add to HPA to disable */ |
| 41 | |
| 42 | /* offsets to DINO HPA: */ |
| 43 | #define DINO_PCI_ADDR 0x064 |
| 44 | #define DINO_CONFIG_DATA 0x068 |
| 45 | #define DINO_IO_DATA 0x06c |
| 46 | |
| 47 | #define PORT_PCI_CMD hppa_port_pci_cmd |
| 48 | #define PORT_PCI_DATA hppa_port_pci_data |
| 49 | |
| 50 | #define FW_CFG_IO_BASE 0xfffa0000 |
| 51 | |
| 52 | #define PORT_SERIAL1 (LASI_UART_HPA + 0x800) |
| 53 | #define PORT_SERIAL2 (DINO_UART_HPA + 0x800) |
| 54 | |
| 55 | #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ |
| 56 | #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ |
| 57 | |
| 58 | #define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ |
| 59 | #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ |
| 60 | #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ |
| 61 | |
| 62 | #define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ |
| 63 | |
| 64 | /* ASTRO Memory and I/O regions */ |
| 65 | #define ASTRO_BASE_HPA 0xffffed00000 |
| 66 | #define ELROY0_BASE_HPA 0xffffed30000 /* ELROY0_HPA */ |
| 67 | |
| 68 | #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ |
| 69 | |
| 70 | #define LMMIO_DIRECT0_BASE 0x300 |
| 71 | #define LMMIO_DIRECT0_MASK 0x308 |
| 72 | #define LMMIO_DIRECT0_ROUTE 0x310 |
| 73 | |
| 74 | /* space register hashing */ |
| 75 | #define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ |
| 76 | #define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ |
| 77 | |
| 78 | #endif |