| 1 | /* |
| 2 | * ARM Aspeed I2C controller |
| 3 | * |
| 4 | * Copyright (C) 2016 IBM Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "hw/core/sysbus.h" |
| 23 | #include "migration/vmstate.h" |
| 24 | #include "qemu/cutils.h" |
| 25 | #include "qemu/log.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "hw/i2c/aspeed_i2c.h" |
| 30 | #include "hw/core/irq.h" |
| 31 | #include "hw/core/qdev-properties.h" |
| 32 | #include "hw/core/registerfields.h" |
| 33 | #include "trace.h" |
| 34 | |
| 35 | /* Enable SLAVE_ADDR_RX_MATCH always */ |
| 36 | #define R_I2CD_INTR_STS_ALWAYS_ENABLE R_I2CD_INTR_STS_SLAVE_ADDR_RX_MATCH_MASK |
| 37 | |
| 38 | static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) |
| 39 | { |
| 40 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 41 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 42 | uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); |
| 43 | uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | |
| 44 | R_I2CD_INTR_STS_ALWAYS_ENABLE; |
| 45 | bool raise_irq; |
| 46 | |
| 47 | if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) { |
| 48 | g_autofree char *buf = g_strdup_printf("%s%s%s%s%s%s%s", |
| 49 | aspeed_i2c_bus_pkt_mode_en(bus) && |
| 50 | ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? |
| 51 | "pktdone|" : "", |
| 52 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? |
| 53 | "nak|" : "", |
| 54 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? |
| 55 | "ack|" : "", |
| 56 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? |
| 57 | "done|" : "", |
| 58 | ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? |
| 59 | "slave-match|" : "", |
| 60 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? |
| 61 | "stop|" : "", |
| 62 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? |
| 63 | "abnormal" : ""); |
| 64 | |
| 65 | trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf); |
| 66 | } |
| 67 | |
| 68 | raise_irq = bus->regs[reg_intr_sts] & intr_ctrl_mask ; |
| 69 | |
| 70 | /* In packet mode we don't mask off INTR_STS */ |
| 71 | if (!aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 72 | bus->regs[reg_intr_sts] &= intr_ctrl_mask; |
| 73 | } |
| 74 | |
| 75 | if (raise_irq) { |
| 76 | bus->controller->intr_status |= 1 << bus->id; |
| 77 | qemu_irq_raise(aic->bus_get_irq(bus)); |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | static inline void aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus *bus) |
| 82 | { |
| 83 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 84 | |
| 85 | if (!bus->regs[R_I2CS_INTR_STS]) { |
| 86 | return; |
| 87 | } |
| 88 | |
| 89 | bus->controller->intr_status |= 1 << bus->id; |
| 90 | qemu_irq_raise(aic->bus_get_irq(bus)); |
| 91 | } |
| 92 | |
| 93 | static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, |
| 94 | unsigned size) |
| 95 | { |
| 96 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 97 | uint64_t value = -1; |
| 98 | |
| 99 | switch (offset) { |
| 100 | case A_I2CD_FUN_CTRL: |
| 101 | case A_I2CD_AC_TIMING1: |
| 102 | case A_I2CD_AC_TIMING2: |
| 103 | case A_I2CD_INTR_CTRL: |
| 104 | case A_I2CD_INTR_STS: |
| 105 | case A_I2CD_DEV_ADDR: |
| 106 | case A_I2CD_POOL_CTRL: |
| 107 | case A_I2CD_BYTE_BUF: |
| 108 | value = bus->regs[offset / sizeof(*bus->regs)]; |
| 109 | break; |
| 110 | case A_I2CD_CMD: |
| 111 | value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); |
| 112 | break; |
| 113 | case A_I2CD_DMA_ADDR: |
| 114 | if (!aic->has_dma) { |
| 115 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 116 | break; |
| 117 | } |
| 118 | value = bus->regs[offset / sizeof(*bus->regs)]; |
| 119 | break; |
| 120 | case A_I2CD_DMA_LEN: |
| 121 | if (!aic->has_dma) { |
| 122 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 123 | break; |
| 124 | } |
| 125 | value = bus->regs[offset / sizeof(*bus->regs)]; |
| 126 | break; |
| 127 | default: |
| 128 | qemu_log_mask(LOG_GUEST_ERROR, |
| 129 | "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); |
| 130 | break; |
| 131 | } |
| 132 | |
| 133 | trace_aspeed_i2c_bus_read(bus->id, offset, size, value); |
| 134 | return value; |
| 135 | } |
| 136 | |
| 137 | static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, |
| 138 | unsigned size) |
| 139 | { |
| 140 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 141 | uint64_t value = -1; |
| 142 | |
| 143 | switch (offset) { |
| 144 | case A_I2CC_FUN_CTRL: |
| 145 | case A_I2CC_AC_TIMING: |
| 146 | case A_I2CC_POOL_CTRL: |
| 147 | case A_I2CM_INTR_CTRL: |
| 148 | case A_I2CM_INTR_STS: |
| 149 | case A_I2CC_MS_TXRX_BYTE_BUF: |
| 150 | case A_I2CM_DMA_LEN: |
| 151 | case A_I2CM_DMA_TX_ADDR: |
| 152 | case A_I2CM_DMA_RX_ADDR: |
| 153 | case A_I2CM_DMA_LEN_STS: |
| 154 | case A_I2CC_DMA_LEN: |
| 155 | case A_I2CS_DEV_ADDR: |
| 156 | case A_I2CS_DMA_RX_ADDR: |
| 157 | case A_I2CS_DMA_LEN: |
| 158 | case A_I2CS_CMD: |
| 159 | case A_I2CS_INTR_CTRL: |
| 160 | case A_I2CS_DMA_LEN_STS: |
| 161 | case A_I2CS_INTR_STS: |
| 162 | case A_I2CC_VERSION_CTRL: |
| 163 | value = bus->regs[offset / sizeof(*bus->regs)]; |
| 164 | break; |
| 165 | case A_I2CC_DMA_ADDR: |
| 166 | value = extract64(bus->dma_dram_offset, 0, 32); |
| 167 | break; |
| 168 | case A_I2CM_CMD: |
| 169 | value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); |
| 170 | break; |
| 171 | case A_I2CM_DMA_TX_ADDR_HI: |
| 172 | case A_I2CM_DMA_RX_ADDR_HI: |
| 173 | case A_I2CS_DMA_TX_ADDR_HI: |
| 174 | case A_I2CS_DMA_RX_ADDR_HI: |
| 175 | if (!aic->has_dma64) { |
| 176 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", |
| 177 | __func__); |
| 178 | break; |
| 179 | } |
| 180 | value = bus->regs[offset / sizeof(*bus->regs)]; |
| 181 | break; |
| 182 | default: |
| 183 | qemu_log_mask(LOG_GUEST_ERROR, |
| 184 | "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); |
| 185 | break; |
| 186 | } |
| 187 | |
| 188 | trace_aspeed_i2c_bus_read(bus->id, offset, size, value); |
| 189 | return value; |
| 190 | } |
| 191 | |
| 192 | static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, |
| 193 | unsigned size) |
| 194 | { |
| 195 | AspeedI2CBus *bus = opaque; |
| 196 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 197 | return aspeed_i2c_bus_new_read(bus, offset, size); |
| 198 | } |
| 199 | return aspeed_i2c_bus_old_read(bus, offset, size); |
| 200 | } |
| 201 | |
| 202 | static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) |
| 203 | { |
| 204 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 205 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, |
| 206 | state); |
| 207 | } else { |
| 208 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) |
| 213 | { |
| 214 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 215 | return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, |
| 216 | TX_STATE); |
| 217 | } |
| 218 | return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * The AST2700 support the maximum DRAM size is 8 GB. |
| 223 | * The DRAM offset range is from 0x0_0000_0000 to |
| 224 | * 0x1_FFFF_FFFF and it is enough to use bits [33:0] |
| 225 | * saving the dram offset. |
| 226 | * Therefore, save the high part physical address bit[1:0] |
| 227 | * of Tx/Rx buffer address as dma_dram_offset bit[33:32]. |
| 228 | */ |
| 229 | static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus) |
| 230 | { |
| 231 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 232 | uint32_t value; |
| 233 | |
| 234 | assert(aic->has_dma); |
| 235 | |
| 236 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 237 | value = bus->regs[R_I2CM_DMA_TX_ADDR]; |
| 238 | bus->dma_dram_offset = |
| 239 | deposit64(bus->dma_dram_offset, 0, 32, |
| 240 | value & aic->dma_addr_lo_mask); |
| 241 | if (aic->has_dma64) { |
| 242 | value = bus->regs[R_I2CM_DMA_TX_ADDR_HI]; |
| 243 | bus->dma_dram_offset = |
| 244 | deposit64(bus->dma_dram_offset, 32, 32, |
| 245 | extract32(value, 0, 2)); |
| 246 | } |
| 247 | } else { |
| 248 | value = bus->regs[R_I2CD_DMA_ADDR]; |
| 249 | bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, |
| 250 | value & aic->dma_addr_lo_mask); |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus) |
| 255 | { |
| 256 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 257 | uint32_t value; |
| 258 | |
| 259 | assert(aic->has_dma); |
| 260 | |
| 261 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 262 | value = bus->regs[R_I2CM_DMA_RX_ADDR]; |
| 263 | bus->dma_dram_offset = |
| 264 | deposit64(bus->dma_dram_offset, 0, 32, |
| 265 | value & aic->dma_addr_lo_mask); |
| 266 | if (aic->has_dma64) { |
| 267 | value = bus->regs[R_I2CM_DMA_RX_ADDR_HI]; |
| 268 | bus->dma_dram_offset = |
| 269 | deposit64(bus->dma_dram_offset, 32, 32, |
| 270 | extract32(value, 0, 2)); |
| 271 | } |
| 272 | } else { |
| 273 | value = bus->regs[R_I2CD_DMA_ADDR]; |
| 274 | bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, |
| 275 | value & aic->dma_addr_lo_mask); |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) |
| 280 | { |
| 281 | MemTxResult result; |
| 282 | AspeedI2CState *s = bus->controller; |
| 283 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 284 | |
| 285 | result = address_space_read(&s->dram_as, bus->dma_dram_offset, |
| 286 | MEMTXATTRS_UNSPECIFIED, data, 1); |
| 287 | if (result != MEMTX_OK) { |
| 288 | qemu_log_mask(LOG_GUEST_ERROR, |
| 289 | "%s: DRAM read failed @%" PRIx64 "\n", |
| 290 | __func__, bus->dma_dram_offset); |
| 291 | return -1; |
| 292 | } |
| 293 | |
| 294 | bus->dma_dram_offset++; |
| 295 | bus->regs[reg_dma_len]--; |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | /* |
| 300 | * In AST2700 buffer mode the master DMA command bits (TX/RX_DMA_EN) and the |
| 301 | * DMA length registers are reused, but data is moved through the controller |
| 302 | * internal SRAM pool at the offset programmed in I2CM_DMA_TX/RX_ADDR instead |
| 303 | * of DRAM. FUNC_CFG_DMA_EN selects between the two (set = DRAM). |
| 304 | */ |
| 305 | static bool aspeed_i2c_bus_dma_to_pool(AspeedI2CBus *bus) |
| 306 | { |
| 307 | return aspeed_i2c_is_new_mode(bus->controller) && |
| 308 | !ARRAY_FIELD_EX32(bus->regs, I2CC_VERSION_CTRL, FUNC_CFG_DMA_EN); |
| 309 | } |
| 310 | |
| 311 | static int aspeed_i2c_bus_send_dma_pool(AspeedI2CBus *bus) |
| 312 | { |
| 313 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 314 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 315 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 316 | uint32_t offset = bus->regs[R_I2CM_DMA_TX_ADDR]; |
| 317 | uint8_t *pool_base = aic->bus_pool_base(bus); |
| 318 | int ret = -1; |
| 319 | int i; |
| 320 | |
| 321 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); |
| 322 | for (i = 0; bus->regs[reg_dma_len] && |
| 323 | offset + i < ASPEED_I2C_BUS_POOL_SIZE; i++) { |
| 324 | trace_aspeed_i2c_bus_send("BUFF", i + 1, bus->regs[reg_dma_len], |
| 325 | pool_base[offset + i]); |
| 326 | ret = i2c_send(bus->bus, pool_base[offset + i]); |
| 327 | bus->regs[reg_dma_len]--; |
| 328 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, i + 1); |
| 329 | if (ret) { |
| 330 | break; |
| 331 | } |
| 332 | } |
| 333 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); |
| 334 | return ret; |
| 335 | } |
| 336 | |
| 337 | static void aspeed_i2c_bus_recv_dma_pool(AspeedI2CBus *bus) |
| 338 | { |
| 339 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 340 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 341 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 342 | uint32_t offset = bus->regs[R_I2CM_DMA_RX_ADDR]; |
| 343 | uint8_t *pool_base = aic->bus_pool_base(bus); |
| 344 | int i; |
| 345 | |
| 346 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); |
| 347 | for (i = 0; bus->regs[reg_dma_len] && |
| 348 | offset + i < ASPEED_I2C_BUS_POOL_SIZE; i++) { |
| 349 | pool_base[offset + i] = i2c_recv(bus->bus); |
| 350 | trace_aspeed_i2c_bus_recv("BUFF", i + 1, bus->regs[reg_dma_len], |
| 351 | pool_base[offset + i]); |
| 352 | bus->regs[reg_dma_len]--; |
| 353 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, i + 1); |
| 354 | } |
| 355 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); |
| 356 | } |
| 357 | |
| 358 | static int aspeed_i2c_bus_send(AspeedI2CBus *bus) |
| 359 | { |
| 360 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 361 | int ret = -1; |
| 362 | int i; |
| 363 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 364 | uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); |
| 365 | uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); |
| 366 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 367 | int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, |
| 368 | TX_COUNT) + 1; |
| 369 | |
| 370 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { |
| 371 | for (i = 0; i < pool_tx_count; i++) { |
| 372 | uint8_t *pool_base = aic->bus_pool_base(bus); |
| 373 | |
| 374 | trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, |
| 375 | pool_base[i]); |
| 376 | ret = i2c_send(bus->bus, pool_base[i]); |
| 377 | if (ret) { |
| 378 | break; |
| 379 | } |
| 380 | } |
| 381 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); |
| 382 | } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { |
| 383 | /* In buffer mode the DMA moves data through the pool, not DRAM */ |
| 384 | if (aspeed_i2c_bus_dma_to_pool(bus)) { |
| 385 | return aspeed_i2c_bus_send_dma_pool(bus); |
| 386 | } |
| 387 | /* In new mode, clear how many bytes we TXed */ |
| 388 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 389 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); |
| 390 | } |
| 391 | aspeed_i2c_set_tx_dma_dram_offset(bus); |
| 392 | while (bus->regs[reg_dma_len]) { |
| 393 | uint8_t data; |
| 394 | ret = aspeed_i2c_dma_read(bus, &data); |
| 395 | /* Check that we were able to read the DMA */ |
| 396 | if (ret) { |
| 397 | break; |
| 398 | } |
| 399 | trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], |
| 400 | bus->regs[reg_dma_len], data); |
| 401 | ret = i2c_send(bus->bus, data); |
| 402 | if (ret) { |
| 403 | break; |
| 404 | } |
| 405 | /* In new mode, keep track of how many bytes we TXed */ |
| 406 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 407 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, |
| 408 | ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, |
| 409 | TX_LEN) + 1); |
| 410 | } |
| 411 | } |
| 412 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); |
| 413 | } else { |
| 414 | trace_aspeed_i2c_bus_send("BYTE", 0, 1, |
| 415 | bus->regs[reg_byte_buf]); |
| 416 | ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); |
| 417 | } |
| 418 | |
| 419 | return ret; |
| 420 | } |
| 421 | |
| 422 | static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) |
| 423 | { |
| 424 | AspeedI2CState *s = bus->controller; |
| 425 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); |
| 426 | uint8_t data; |
| 427 | int i; |
| 428 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 429 | uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); |
| 430 | uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); |
| 431 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 432 | int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, |
| 433 | RX_SIZE) + 1; |
| 434 | |
| 435 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { |
| 436 | uint8_t *pool_base = aic->bus_pool_base(bus); |
| 437 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, |
| 438 | BUF_ORGANIZATION)) { |
| 439 | pool_base += 16; |
| 440 | } |
| 441 | |
| 442 | for (i = 0; i < pool_rx_count; i++) { |
| 443 | pool_base[i] = i2c_recv(bus->bus); |
| 444 | trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count, |
| 445 | pool_base[i]); |
| 446 | } |
| 447 | |
| 448 | /* Update RX count */ |
| 449 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); |
| 450 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); |
| 451 | } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { |
| 452 | /* In buffer mode the DMA moves data through the pool, not DRAM */ |
| 453 | if (aspeed_i2c_bus_dma_to_pool(bus)) { |
| 454 | aspeed_i2c_bus_recv_dma_pool(bus); |
| 455 | return; |
| 456 | } |
| 457 | /* In new mode, clear how many bytes we RXed */ |
| 458 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 459 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); |
| 460 | } |
| 461 | |
| 462 | aspeed_i2c_set_rx_dma_dram_offset(bus); |
| 463 | while (bus->regs[reg_dma_len]) { |
| 464 | MemTxResult result; |
| 465 | |
| 466 | data = i2c_recv(bus->bus); |
| 467 | trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], |
| 468 | bus->regs[reg_dma_len], data); |
| 469 | |
| 470 | result = address_space_write(&s->dram_as, bus->dma_dram_offset, |
| 471 | MEMTXATTRS_UNSPECIFIED, &data, 1); |
| 472 | if (result != MEMTX_OK) { |
| 473 | qemu_log_mask(LOG_GUEST_ERROR, |
| 474 | "%s: DRAM write failed @%" PRIx64 "\n", |
| 475 | __func__, bus->dma_dram_offset); |
| 476 | return; |
| 477 | } |
| 478 | |
| 479 | bus->dma_dram_offset++; |
| 480 | bus->regs[reg_dma_len]--; |
| 481 | /* In new mode, keep track of how many bytes we RXed */ |
| 482 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 483 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, |
| 484 | ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, |
| 485 | RX_LEN) + 1); |
| 486 | } |
| 487 | } |
| 488 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); |
| 489 | } else { |
| 490 | data = i2c_recv(bus->bus); |
| 491 | trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); |
| 492 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) |
| 497 | { |
| 498 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 499 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 500 | |
| 501 | aspeed_i2c_set_state(bus, I2CD_MRXD); |
| 502 | aspeed_i2c_bus_recv(bus); |
| 503 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); |
| 504 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { |
| 505 | i2c_nack(bus->bus); |
| 506 | } |
| 507 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); |
| 508 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); |
| 509 | aspeed_i2c_set_state(bus, I2CD_MACTIVE); |
| 510 | } |
| 511 | |
| 512 | static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) |
| 513 | { |
| 514 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 515 | uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); |
| 516 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 517 | |
| 518 | if (aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 519 | return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | |
| 520 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); |
| 521 | } |
| 522 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { |
| 523 | uint8_t *pool_base = aic->bus_pool_base(bus); |
| 524 | |
| 525 | return pool_base[0]; |
| 526 | } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { |
| 527 | uint8_t data; |
| 528 | |
| 529 | aspeed_i2c_set_tx_dma_dram_offset(bus); |
| 530 | aspeed_i2c_dma_read(bus, &data); |
| 531 | return data; |
| 532 | } else { |
| 533 | return bus->regs[reg_byte_buf]; |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) |
| 538 | { |
| 539 | AspeedI2CState *s = bus->controller; |
| 540 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); |
| 541 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 542 | bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || |
| 543 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || |
| 544 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || |
| 545 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); |
| 546 | if (!aic->check_sram) { |
| 547 | return true; |
| 548 | } |
| 549 | |
| 550 | /* |
| 551 | * AST2500: SRAM must be enabled before using the Buffer Pool or |
| 552 | * DMA mode. |
| 553 | */ |
| 554 | if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { |
| 555 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); |
| 556 | return false; |
| 557 | } |
| 558 | |
| 559 | return true; |
| 560 | } |
| 561 | |
| 562 | static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) |
| 563 | { |
| 564 | g_autofree char *cmd_flags = NULL; |
| 565 | uint32_t count; |
| 566 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 567 | uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); |
| 568 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 569 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 570 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { |
| 571 | count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 1; |
| 572 | } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { |
| 573 | count = bus->regs[reg_dma_len]; |
| 574 | } else { /* BYTE mode */ |
| 575 | count = 1; |
| 576 | } |
| 577 | |
| 578 | cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", |
| 579 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", |
| 580 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", |
| 581 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", |
| 582 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", |
| 583 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", |
| 584 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", |
| 585 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", |
| 586 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", |
| 587 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); |
| 588 | |
| 589 | trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, |
| 590 | bus->regs[reg_intr_sts]); |
| 591 | } |
| 592 | |
| 593 | /* |
| 594 | * The state machine needs some refinement. It is only used to track |
| 595 | * invalid STOP commands for the moment. |
| 596 | */ |
| 597 | static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) |
| 598 | { |
| 599 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 600 | uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); |
| 601 | uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); |
| 602 | |
| 603 | if (!aspeed_i2c_check_sram(bus)) { |
| 604 | return; |
| 605 | } |
| 606 | |
| 607 | if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { |
| 608 | aspeed_i2c_bus_cmd_dump(bus); |
| 609 | } |
| 610 | |
| 611 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { |
| 612 | uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? |
| 613 | I2CD_MSTARTR : I2CD_MSTART; |
| 614 | uint8_t addr; |
| 615 | |
| 616 | aspeed_i2c_set_state(bus, state); |
| 617 | |
| 618 | addr = aspeed_i2c_get_addr(bus); |
| 619 | if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), |
| 620 | extract32(addr, 0, 1))) { |
| 621 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); |
| 622 | if (aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 623 | ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); |
| 624 | } |
| 625 | } else { |
| 626 | /* START doesn't set TX_ACK in packet mode */ |
| 627 | if (!aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 628 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); |
| 633 | |
| 634 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { |
| 635 | if (bus->regs[reg_dma_len] == 0) { |
| 636 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); |
| 637 | } |
| 638 | } else if (!SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { |
| 639 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); |
| 640 | } |
| 641 | |
| 642 | /* No slave found */ |
| 643 | if (!i2c_bus_busy(bus->bus)) { |
| 644 | if (aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 645 | ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); |
| 646 | ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); |
| 647 | } |
| 648 | return; |
| 649 | } |
| 650 | aspeed_i2c_set_state(bus, I2CD_MACTIVE); |
| 651 | } |
| 652 | |
| 653 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { |
| 654 | aspeed_i2c_set_state(bus, I2CD_MTXD); |
| 655 | if (aspeed_i2c_bus_send(bus)) { |
| 656 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); |
| 657 | i2c_end_transfer(bus->bus); |
| 658 | } else { |
| 659 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); |
| 660 | } |
| 661 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); |
| 662 | aspeed_i2c_set_state(bus, I2CD_MACTIVE); |
| 663 | } |
| 664 | |
| 665 | if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || |
| 666 | SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && |
| 667 | !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { |
| 668 | aspeed_i2c_handle_rx_cmd(bus); |
| 669 | } |
| 670 | |
| 671 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { |
| 672 | if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { |
| 673 | qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); |
| 674 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); |
| 675 | if (aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 676 | ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); |
| 677 | } |
| 678 | } else { |
| 679 | aspeed_i2c_set_state(bus, I2CD_MSTOP); |
| 680 | i2c_end_transfer(bus->bus); |
| 681 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); |
| 682 | } |
| 683 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); |
| 684 | aspeed_i2c_set_state(bus, I2CD_IDLE); |
| 685 | |
| 686 | i2c_schedule_pending_master(bus->bus); |
| 687 | } |
| 688 | |
| 689 | if (aspeed_i2c_bus_pkt_mode_en(bus)) { |
| 690 | ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, |
| 695 | uint64_t value, unsigned size) |
| 696 | { |
| 697 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 698 | bool handle_rx; |
| 699 | bool w1t; |
| 700 | uint32_t old_intr; |
| 701 | uint32_t cmd_intr; |
| 702 | |
| 703 | trace_aspeed_i2c_bus_write(bus->id, offset, size, value); |
| 704 | |
| 705 | switch (offset) { |
| 706 | case A_I2CC_FUN_CTRL: |
| 707 | bus->regs[R_I2CC_FUN_CTRL] = value; |
| 708 | break; |
| 709 | case A_I2CC_AC_TIMING: |
| 710 | bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; |
| 711 | break; |
| 712 | case A_I2CC_MS_TXRX_BYTE_BUF: |
| 713 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, |
| 714 | value); |
| 715 | break; |
| 716 | case A_I2CC_POOL_CTRL: |
| 717 | bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; |
| 718 | bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); |
| 719 | break; |
| 720 | case A_I2CM_INTR_CTRL: |
| 721 | bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; |
| 722 | break; |
| 723 | case A_I2CM_INTR_STS: |
| 724 | handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) |
| 725 | && SHARED_FIELD_EX32(value, RX_DONE); |
| 726 | |
| 727 | /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */ |
| 728 | if (aspeed_i2c_bus_pkt_mode_en(bus) && |
| 729 | FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { |
| 730 | bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; |
| 731 | if (!bus->regs[R_I2CM_INTR_STS]) { |
| 732 | bus->controller->intr_status &= ~(1 << bus->id); |
| 733 | qemu_irq_lower(aic->bus_get_irq(bus)); |
| 734 | } |
| 735 | aspeed_i2c_bus_raise_slave_interrupt(bus); |
| 736 | break; |
| 737 | } |
| 738 | bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); |
| 739 | /* |
| 740 | * Re-apply interrupts lost due to synchronous command completion. |
| 741 | * When a command completes instantly during an MMIO write, the new |
| 742 | * interrupt status bits collide with already-pending bits. After |
| 743 | * the ISR clears them, re-apply the saved bits so the ISR can |
| 744 | * process the new completion. |
| 745 | */ |
| 746 | if (bus->pending_intr_sts) { |
| 747 | bus->regs[R_I2CM_INTR_STS] |= bus->pending_intr_sts; |
| 748 | bus->pending_intr_sts = 0; |
| 749 | } |
| 750 | if (!bus->regs[R_I2CM_INTR_STS]) { |
| 751 | bus->controller->intr_status &= ~(1 << bus->id); |
| 752 | qemu_irq_lower(aic->bus_get_irq(bus)); |
| 753 | } |
| 754 | if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, |
| 755 | M_RX_CMD) || |
| 756 | SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, |
| 757 | M_S_RX_CMD_LAST))) { |
| 758 | aspeed_i2c_handle_rx_cmd(bus); |
| 759 | aspeed_i2c_bus_raise_interrupt(bus); |
| 760 | } |
| 761 | break; |
| 762 | case A_I2CM_CMD: |
| 763 | if (!aspeed_i2c_bus_is_enabled(bus)) { |
| 764 | break; |
| 765 | } |
| 766 | |
| 767 | if (!aspeed_i2c_bus_is_master(bus)) { |
| 768 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n", |
| 769 | __func__); |
| 770 | break; |
| 771 | } |
| 772 | |
| 773 | if (!aic->has_dma && |
| 774 | (SHARED_FIELD_EX32(value, RX_DMA_EN) || |
| 775 | SHARED_FIELD_EX32(value, TX_DMA_EN))) { |
| 776 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 777 | break; |
| 778 | } |
| 779 | |
| 780 | if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { |
| 781 | qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n", |
| 782 | __func__); |
| 783 | break; |
| 784 | } |
| 785 | |
| 786 | value &= 0xff0ffbfb; |
| 787 | if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { |
| 788 | bus->regs[R_I2CM_CMD] |= value; |
| 789 | } else { |
| 790 | bus->regs[R_I2CM_CMD] = value; |
| 791 | } |
| 792 | |
| 793 | old_intr = bus->regs[R_I2CM_INTR_STS]; |
| 794 | bus->regs[R_I2CM_INTR_STS] = 0; |
| 795 | aspeed_i2c_bus_handle_cmd(bus, value); |
| 796 | /* |
| 797 | * cmd_intr has only the bits handle_cmd freshly set. |
| 798 | * Overlap with old_intr means the same bit was re-fired |
| 799 | * and would be lost when the ISR W1C-clears the old one. |
| 800 | */ |
| 801 | cmd_intr = bus->regs[R_I2CM_INTR_STS]; |
| 802 | bus->regs[R_I2CM_INTR_STS] = cmd_intr | old_intr; |
| 803 | bus->pending_intr_sts |= old_intr & cmd_intr; |
| 804 | aspeed_i2c_bus_raise_interrupt(bus); |
| 805 | break; |
| 806 | case A_I2CM_DMA_TX_ADDR: |
| 807 | bus->regs[R_I2CM_DMA_TX_ADDR] = value & aic->dma_addr_lo_mask; |
| 808 | break; |
| 809 | case A_I2CM_DMA_RX_ADDR: |
| 810 | bus->regs[R_I2CM_DMA_RX_ADDR] = value & aic->dma_addr_lo_mask; |
| 811 | break; |
| 812 | case A_I2CM_DMA_LEN: |
| 813 | w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || |
| 814 | FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T); |
| 815 | /* If none of the w1t bits are set, just write to the reg as normal. */ |
| 816 | if (!w1t) { |
| 817 | bus->regs[R_I2CM_DMA_LEN] = value; |
| 818 | break; |
| 819 | } |
| 820 | if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { |
| 821 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, |
| 822 | FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); |
| 823 | bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, |
| 824 | I2CM_DMA_LEN, |
| 825 | RX_BUF_LEN) + 1; |
| 826 | } |
| 827 | if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { |
| 828 | ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, |
| 829 | FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); |
| 830 | bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, |
| 831 | I2CM_DMA_LEN, |
| 832 | TX_BUF_LEN) + 1; |
| 833 | } |
| 834 | break; |
| 835 | case A_I2CM_DMA_LEN_STS: |
| 836 | /* Writes clear to 0 */ |
| 837 | bus->regs[R_I2CM_DMA_LEN_STS] = 0; |
| 838 | break; |
| 839 | case A_I2CC_DMA_ADDR: |
| 840 | case A_I2CC_DMA_LEN: |
| 841 | /* RO */ |
| 842 | break; |
| 843 | case A_I2CS_DEV_ADDR: |
| 844 | bus->regs[R_I2CS_DEV_ADDR] = value; |
| 845 | break; |
| 846 | case A_I2CS_DMA_RX_ADDR: |
| 847 | bus->regs[R_I2CS_DMA_RX_ADDR] = value & aic->dma_addr_lo_mask; |
| 848 | break; |
| 849 | case A_I2CS_DMA_LEN: |
| 850 | if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) { |
| 851 | ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN, |
| 852 | FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN)); |
| 853 | } else { |
| 854 | bus->regs[R_I2CS_DMA_LEN] = value; |
| 855 | } |
| 856 | break; |
| 857 | case A_I2CS_CMD: |
| 858 | if (FIELD_EX32(value, I2CS_CMD, W1_CTRL)) { |
| 859 | bus->regs[R_I2CS_CMD] |= value; |
| 860 | } else { |
| 861 | bus->regs[R_I2CS_CMD] = value; |
| 862 | } |
| 863 | i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]); |
| 864 | break; |
| 865 | case A_I2CS_INTR_CTRL: |
| 866 | bus->regs[R_I2CS_INTR_CTRL] = value; |
| 867 | break; |
| 868 | |
| 869 | case A_I2CS_INTR_STS: |
| 870 | if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) { |
| 871 | if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) && |
| 872 | FIELD_EX32(value, I2CS_INTR_STS, PKT_CMD_DONE)) { |
| 873 | bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000; |
| 874 | } |
| 875 | } else { |
| 876 | bus->regs[R_I2CS_INTR_STS] &= ~value; |
| 877 | } |
| 878 | if (!bus->regs[R_I2CS_INTR_STS]) { |
| 879 | bus->controller->intr_status &= ~(1 << bus->id); |
| 880 | qemu_irq_lower(aic->bus_get_irq(bus)); |
| 881 | } |
| 882 | aspeed_i2c_bus_raise_interrupt(bus); |
| 883 | break; |
| 884 | case A_I2CS_DMA_LEN_STS: |
| 885 | bus->regs[R_I2CS_DMA_LEN_STS] = 0; |
| 886 | break; |
| 887 | case A_I2CS_DMA_TX_ADDR: |
| 888 | qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n", |
| 889 | __func__); |
| 890 | break; |
| 891 | case A_I2CM_DMA_TX_ADDR_HI: |
| 892 | if (!aic->has_dma64) { |
| 893 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", |
| 894 | __func__); |
| 895 | break; |
| 896 | } |
| 897 | bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value, |
| 898 | I2CM_DMA_TX_ADDR_HI, |
| 899 | ADDR_HI); |
| 900 | break; |
| 901 | case A_I2CM_DMA_RX_ADDR_HI: |
| 902 | if (!aic->has_dma64) { |
| 903 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", |
| 904 | __func__); |
| 905 | break; |
| 906 | } |
| 907 | bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value, |
| 908 | I2CM_DMA_RX_ADDR_HI, |
| 909 | ADDR_HI); |
| 910 | break; |
| 911 | case A_I2CS_DMA_TX_ADDR_HI: |
| 912 | qemu_log_mask(LOG_UNIMP, |
| 913 | "%s: Slave mode DMA TX Addr high is not implemented\n", |
| 914 | __func__); |
| 915 | break; |
| 916 | case A_I2CS_DMA_RX_ADDR_HI: |
| 917 | if (!aic->has_dma64) { |
| 918 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", |
| 919 | __func__); |
| 920 | break; |
| 921 | } |
| 922 | bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value, |
| 923 | I2CS_DMA_RX_ADDR_HI, |
| 924 | ADDR_HI); |
| 925 | break; |
| 926 | case A_I2CC_VERSION_CTRL: |
| 927 | bus->regs[R_I2CC_VERSION_CTRL] = value; |
| 928 | break; |
| 929 | default: |
| 930 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", |
| 931 | __func__, offset); |
| 932 | } |
| 933 | } |
| 934 | |
| 935 | static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, |
| 936 | uint64_t value, unsigned size) |
| 937 | { |
| 938 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 939 | bool handle_rx; |
| 940 | uint32_t old_intr; |
| 941 | uint32_t cmd_intr; |
| 942 | |
| 943 | trace_aspeed_i2c_bus_write(bus->id, offset, size, value); |
| 944 | |
| 945 | switch (offset) { |
| 946 | case A_I2CD_FUN_CTRL: |
| 947 | if (SHARED_FIELD_EX32(value, SLAVE_EN)) { |
| 948 | i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]); |
| 949 | } |
| 950 | bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; |
| 951 | break; |
| 952 | case A_I2CD_AC_TIMING1: |
| 953 | bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; |
| 954 | break; |
| 955 | case A_I2CD_AC_TIMING2: |
| 956 | bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; |
| 957 | break; |
| 958 | case A_I2CD_INTR_CTRL: |
| 959 | bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; |
| 960 | break; |
| 961 | case A_I2CD_INTR_STS: |
| 962 | handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) |
| 963 | && SHARED_FIELD_EX32(value, RX_DONE); |
| 964 | bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); |
| 965 | /* |
| 966 | * Re-apply interrupts lost due to synchronous command completion. |
| 967 | * When a command completes instantly during an MMIO write, the new |
| 968 | * interrupt status bits collide with already-pending bits. After |
| 969 | * the ISR clears them, re-apply the saved bits so the ISR can |
| 970 | * process the new completion. |
| 971 | */ |
| 972 | if (bus->pending_intr_sts) { |
| 973 | bus->regs[R_I2CD_INTR_STS] |= bus->pending_intr_sts; |
| 974 | bus->pending_intr_sts = 0; |
| 975 | } |
| 976 | if (!bus->regs[R_I2CD_INTR_STS]) { |
| 977 | bus->controller->intr_status &= ~(1 << bus->id); |
| 978 | qemu_irq_lower(aic->bus_get_irq(bus)); |
| 979 | } |
| 980 | if (handle_rx) { |
| 981 | if (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, M_RX_CMD) || |
| 982 | SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, |
| 983 | M_S_RX_CMD_LAST)) { |
| 984 | aspeed_i2c_handle_rx_cmd(bus); |
| 985 | aspeed_i2c_bus_raise_interrupt(bus); |
| 986 | } else if (aspeed_i2c_get_state(bus) == I2CD_STXD) { |
| 987 | i2c_ack(bus->bus); |
| 988 | } |
| 989 | } |
| 990 | break; |
| 991 | case A_I2CD_DEV_ADDR: |
| 992 | bus->regs[R_I2CD_DEV_ADDR] = value; |
| 993 | break; |
| 994 | case A_I2CD_POOL_CTRL: |
| 995 | bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; |
| 996 | bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); |
| 997 | break; |
| 998 | |
| 999 | case A_I2CD_BYTE_BUF: |
| 1000 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); |
| 1001 | break; |
| 1002 | case A_I2CD_CMD: |
| 1003 | if (!aspeed_i2c_bus_is_enabled(bus)) { |
| 1004 | break; |
| 1005 | } |
| 1006 | |
| 1007 | if (!aspeed_i2c_bus_is_master(bus)) { |
| 1008 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n", |
| 1009 | __func__); |
| 1010 | break; |
| 1011 | } |
| 1012 | |
| 1013 | if (!aic->has_dma && |
| 1014 | (SHARED_FIELD_EX32(value, RX_DMA_EN) || |
| 1015 | SHARED_FIELD_EX32(value, TX_DMA_EN))) { |
| 1016 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 1017 | break; |
| 1018 | } |
| 1019 | |
| 1020 | bus->regs[R_I2CD_CMD] &= ~0xFFFF; |
| 1021 | bus->regs[R_I2CD_CMD] |= value & 0xFFFF; |
| 1022 | |
| 1023 | old_intr = bus->regs[R_I2CD_INTR_STS]; |
| 1024 | bus->regs[R_I2CD_INTR_STS] = 0; |
| 1025 | aspeed_i2c_bus_handle_cmd(bus, value); |
| 1026 | /* |
| 1027 | * cmd_intr has only the bits handle_cmd freshly set. |
| 1028 | * Overlap with old_intr means the same bit was re-fired |
| 1029 | * and would be lost when the ISR W1C-clears the old one. |
| 1030 | */ |
| 1031 | cmd_intr = bus->regs[R_I2CD_INTR_STS]; |
| 1032 | bus->regs[R_I2CD_INTR_STS] = cmd_intr | old_intr; |
| 1033 | bus->pending_intr_sts |= old_intr & cmd_intr; |
| 1034 | aspeed_i2c_bus_raise_interrupt(bus); |
| 1035 | break; |
| 1036 | case A_I2CD_DMA_ADDR: |
| 1037 | if (!aic->has_dma) { |
| 1038 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 1039 | break; |
| 1040 | } |
| 1041 | break; |
| 1042 | |
| 1043 | case A_I2CD_DMA_LEN: |
| 1044 | if (!aic->has_dma) { |
| 1045 | qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); |
| 1046 | break; |
| 1047 | } |
| 1048 | |
| 1049 | bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; |
| 1050 | if (!bus->regs[R_I2CD_DMA_LEN]) { |
| 1051 | qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); |
| 1052 | } |
| 1053 | break; |
| 1054 | |
| 1055 | default: |
| 1056 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", |
| 1057 | __func__, offset); |
| 1058 | } |
| 1059 | } |
| 1060 | |
| 1061 | static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, |
| 1062 | uint64_t value, unsigned size) |
| 1063 | { |
| 1064 | AspeedI2CBus *bus = opaque; |
| 1065 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 1066 | aspeed_i2c_bus_new_write(bus, offset, value, size); |
| 1067 | } else { |
| 1068 | aspeed_i2c_bus_old_write(bus, offset, value, size); |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, |
| 1073 | unsigned size) |
| 1074 | { |
| 1075 | AspeedI2CState *s = opaque; |
| 1076 | |
| 1077 | switch (offset) { |
| 1078 | case A_I2C_CTRL_STATUS: |
| 1079 | return s->intr_status; |
| 1080 | case A_I2C_CTRL_GLOBAL: |
| 1081 | return s->ctrl_global; |
| 1082 | case A_I2C_CTRL_NEW_CLK_DIVIDER: |
| 1083 | if (aspeed_i2c_is_new_mode(s)) { |
| 1084 | return s->new_clk_divider; |
| 1085 | } |
| 1086 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", |
| 1087 | __func__, offset); |
| 1088 | break; |
| 1089 | default: |
| 1090 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", |
| 1091 | __func__, offset); |
| 1092 | break; |
| 1093 | } |
| 1094 | |
| 1095 | return -1; |
| 1096 | } |
| 1097 | |
| 1098 | static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, |
| 1099 | uint64_t value, unsigned size) |
| 1100 | { |
| 1101 | AspeedI2CState *s = opaque; |
| 1102 | |
| 1103 | switch (offset) { |
| 1104 | case A_I2C_CTRL_GLOBAL: |
| 1105 | s->ctrl_global = value; |
| 1106 | break; |
| 1107 | case A_I2C_CTRL_NEW_CLK_DIVIDER: |
| 1108 | if (aspeed_i2c_is_new_mode(s)) { |
| 1109 | s->new_clk_divider = value; |
| 1110 | } else { |
| 1111 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx |
| 1112 | "\n", __func__, offset); |
| 1113 | } |
| 1114 | break; |
| 1115 | case A_I2C_CTRL_STATUS: |
| 1116 | default: |
| 1117 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", |
| 1118 | __func__, offset); |
| 1119 | break; |
| 1120 | } |
| 1121 | } |
| 1122 | |
| 1123 | static const MemoryRegionOps aspeed_i2c_bus_ops = { |
| 1124 | .read = aspeed_i2c_bus_read, |
| 1125 | .write = aspeed_i2c_bus_write, |
| 1126 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1127 | }; |
| 1128 | |
| 1129 | static const MemoryRegionOps aspeed_i2c_ctrl_ops = { |
| 1130 | .read = aspeed_i2c_ctrl_read, |
| 1131 | .write = aspeed_i2c_ctrl_write, |
| 1132 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1133 | }; |
| 1134 | |
| 1135 | static uint64_t aspeed_i2c_share_pool_read(void *opaque, hwaddr offset, |
| 1136 | unsigned size) |
| 1137 | { |
| 1138 | AspeedI2CState *s = opaque; |
| 1139 | uint64_t ret = 0; |
| 1140 | int i; |
| 1141 | |
| 1142 | for (i = 0; i < size; i++) { |
| 1143 | ret |= (uint64_t) s->share_pool[offset + i] << (8 * i); |
| 1144 | } |
| 1145 | |
| 1146 | return ret; |
| 1147 | } |
| 1148 | |
| 1149 | static void aspeed_i2c_share_pool_write(void *opaque, hwaddr offset, |
| 1150 | uint64_t value, unsigned size) |
| 1151 | { |
| 1152 | AspeedI2CState *s = opaque; |
| 1153 | int i; |
| 1154 | |
| 1155 | for (i = 0; i < size; i++) { |
| 1156 | s->share_pool[offset + i] = (value >> (8 * i)) & 0xFF; |
| 1157 | } |
| 1158 | } |
| 1159 | |
| 1160 | static const MemoryRegionOps aspeed_i2c_share_pool_ops = { |
| 1161 | .read = aspeed_i2c_share_pool_read, |
| 1162 | .write = aspeed_i2c_share_pool_write, |
| 1163 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1164 | .valid = { |
| 1165 | .min_access_size = 1, |
| 1166 | .max_access_size = 4, |
| 1167 | }, |
| 1168 | }; |
| 1169 | |
| 1170 | static uint64_t aspeed_i2c_bus_pool_read(void *opaque, hwaddr offset, |
| 1171 | unsigned size) |
| 1172 | { |
| 1173 | AspeedI2CBus *s = opaque; |
| 1174 | uint64_t ret = 0; |
| 1175 | int i; |
| 1176 | |
| 1177 | for (i = 0; i < size; i++) { |
| 1178 | ret |= (uint64_t) s->pool[offset + i] << (8 * i); |
| 1179 | } |
| 1180 | |
| 1181 | return ret; |
| 1182 | } |
| 1183 | |
| 1184 | static void aspeed_i2c_bus_pool_write(void *opaque, hwaddr offset, |
| 1185 | uint64_t value, unsigned size) |
| 1186 | { |
| 1187 | AspeedI2CBus *s = opaque; |
| 1188 | int i; |
| 1189 | |
| 1190 | for (i = 0; i < size; i++) { |
| 1191 | s->pool[offset + i] = (value >> (8 * i)) & 0xFF; |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | static const MemoryRegionOps aspeed_i2c_bus_pool_ops = { |
| 1196 | .read = aspeed_i2c_bus_pool_read, |
| 1197 | .write = aspeed_i2c_bus_pool_write, |
| 1198 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1199 | .valid = { |
| 1200 | .min_access_size = 1, |
| 1201 | .max_access_size = 4, |
| 1202 | }, |
| 1203 | }; |
| 1204 | |
| 1205 | static const VMStateDescription aspeed_i2c_bus_vmstate = { |
| 1206 | .name = TYPE_ASPEED_I2C, |
| 1207 | .version_id = 8, |
| 1208 | .minimum_version_id = 8, |
| 1209 | .fields = (const VMStateField[]) { |
| 1210 | VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG), |
| 1211 | VMSTATE_UINT32_V(pending_intr_sts, AspeedI2CBus, 7), |
| 1212 | VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus, ASPEED_I2C_BUS_POOL_SIZE), |
| 1213 | VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus), |
| 1214 | VMSTATE_END_OF_LIST() |
| 1215 | } |
| 1216 | }; |
| 1217 | |
| 1218 | static const VMStateDescription aspeed_i2c_vmstate = { |
| 1219 | .name = TYPE_ASPEED_I2C, |
| 1220 | .version_id = 4, |
| 1221 | .minimum_version_id = 4, |
| 1222 | .fields = (const VMStateField[]) { |
| 1223 | VMSTATE_UINT32(intr_status, AspeedI2CState), |
| 1224 | VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, |
| 1225 | ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, |
| 1226 | AspeedI2CBus), |
| 1227 | VMSTATE_UINT8_ARRAY(share_pool, AspeedI2CState, |
| 1228 | ASPEED_I2C_SHARE_POOL_SIZE), |
| 1229 | VMSTATE_END_OF_LIST() |
| 1230 | } |
| 1231 | }; |
| 1232 | |
| 1233 | static void aspeed_i2c_reset_hold(Object *obj, ResetType type) |
| 1234 | { |
| 1235 | AspeedI2CState *s = ASPEED_I2C(obj); |
| 1236 | |
| 1237 | s->intr_status = 0; |
| 1238 | } |
| 1239 | |
| 1240 | static void aspeed_i2c_instance_init(Object *obj) |
| 1241 | { |
| 1242 | AspeedI2CState *s = ASPEED_I2C(obj); |
| 1243 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); |
| 1244 | int i; |
| 1245 | |
| 1246 | for (i = 0; i < aic->num_busses; i++) { |
| 1247 | object_initialize_child(obj, "bus[*]", &s->busses[i], |
| 1248 | TYPE_ASPEED_I2C_BUS); |
| 1249 | } |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * Address Definitions (AST2400 and AST2500) |
| 1254 | * |
| 1255 | * 0x000 ... 0x03F: Global Register |
| 1256 | * 0x040 ... 0x07F: Device 1 |
| 1257 | * 0x080 ... 0x0BF: Device 2 |
| 1258 | * 0x0C0 ... 0x0FF: Device 3 |
| 1259 | * 0x100 ... 0x13F: Device 4 |
| 1260 | * 0x140 ... 0x17F: Device 5 |
| 1261 | * 0x180 ... 0x1BF: Device 6 |
| 1262 | * 0x1C0 ... 0x1FF: Device 7 |
| 1263 | * 0x200 ... 0x20F: Device 1 buffer (AST2500 unused in linux driver) |
| 1264 | * 0x210 ... 0x21F: Device 2 buffer |
| 1265 | * 0x220 ... 0x22F: Device 3 buffer |
| 1266 | * 0x230 ... 0x23F: Device 4 buffer |
| 1267 | * 0x240 ... 0x24F: Device 5 buffer |
| 1268 | * 0x250 ... 0x25F: Device 6 buffer |
| 1269 | * 0x260 ... 0x26F: Device 7 buffer |
| 1270 | * 0x270 ... 0x27F: Device 8 buffer |
| 1271 | * 0x280 ... 0x28F: Device 9 buffer |
| 1272 | * 0x290 ... 0x29F: Device 10 buffer |
| 1273 | * 0x2A0 ... 0x2AF: Device 11 buffer |
| 1274 | * 0x2B0 ... 0x2BF: Device 12 buffer |
| 1275 | * 0x2C0 ... 0x2CF: Device 13 buffer |
| 1276 | * 0x2D0 ... 0x2DF: Device 14 buffer |
| 1277 | * 0x2E0 ... 0x2FF: Reserved |
| 1278 | * 0x300 ... 0x33F: Device 8 |
| 1279 | * 0x340 ... 0x37F: Device 9 |
| 1280 | * 0x380 ... 0x3BF: Device 10 |
| 1281 | * 0x3C0 ... 0x3FF: Device 11 |
| 1282 | * 0x400 ... 0x43F: Device 12 |
| 1283 | * 0x440 ... 0x47F: Device 13 |
| 1284 | * 0x480 ... 0x4BF: Device 14 |
| 1285 | * 0x800 ... 0xFFF: Buffer Pool (AST2400 unused in linux driver) |
| 1286 | * |
| 1287 | * Address Definitions (AST2600 and AST1030) |
| 1288 | * 0x000 ... 0x07F: Global Register |
| 1289 | * 0x080 ... 0x0FF: Device 1 |
| 1290 | * 0x100 ... 0x17F: Device 2 |
| 1291 | * 0x180 ... 0x1FF: Device 3 |
| 1292 | * 0x200 ... 0x27F: Device 4 |
| 1293 | * 0x280 ... 0x2FF: Device 5 |
| 1294 | * 0x300 ... 0x37F: Device 6 |
| 1295 | * 0x380 ... 0x3FF: Device 7 |
| 1296 | * 0x400 ... 0x47F: Device 8 |
| 1297 | * 0x480 ... 0x4FF: Device 9 |
| 1298 | * 0x500 ... 0x57F: Device 10 |
| 1299 | * 0x580 ... 0x5FF: Device 11 |
| 1300 | * 0x600 ... 0x67F: Device 12 |
| 1301 | * 0x680 ... 0x6FF: Device 13 |
| 1302 | * 0x700 ... 0x77F: Device 14 |
| 1303 | * 0x780 ... 0x7FF: Device 15 (15 and 16 unused in AST1030) |
| 1304 | * 0x800 ... 0x87F: Device 16 |
| 1305 | * 0xC00 ... 0xC1F: Device 1 buffer |
| 1306 | * 0xC20 ... 0xC3F: Device 2 buffer |
| 1307 | * 0xC40 ... 0xC5F: Device 3 buffer |
| 1308 | * 0xC60 ... 0xC7F: Device 4 buffer |
| 1309 | * 0xC80 ... 0xC9F: Device 5 buffer |
| 1310 | * 0xCA0 ... 0xCBF: Device 6 buffer |
| 1311 | * 0xCC0 ... 0xCDF: Device 7 buffer |
| 1312 | * 0xCE0 ... 0xCFF: Device 8 buffer |
| 1313 | * 0xD00 ... 0xD1F: Device 9 buffer |
| 1314 | * 0xD20 ... 0xD3F: Device 10 buffer |
| 1315 | * 0xD40 ... 0xD5F: Device 11 buffer |
| 1316 | * 0xD60 ... 0xD7F: Device 12 buffer |
| 1317 | * 0xD80 ... 0xD9F: Device 13 buffer |
| 1318 | * 0xDA0 ... 0xDBF: Device 14 buffer |
| 1319 | * 0xDC0 ... 0xDDF: Device 15 buffer (15 and 16 unused in AST1030) |
| 1320 | * 0xDE0 ... 0xDFF: Device 16 buffer |
| 1321 | * |
| 1322 | * Address Definitions (AST2700) |
| 1323 | * 0x000 ... 0x0FF: Global Register |
| 1324 | * 0x100 ... 0x19F: Device 0 |
| 1325 | * 0x1C0 ... 0x1FF: Device 0 buffer |
| 1326 | * 0x200 ... 0x29F: Device 1 |
| 1327 | * 0x2C0 ... 0x2FF: Device 1 buffer |
| 1328 | * 0x300 ... 0x39F: Device 2 |
| 1329 | * 0x3C0 ... 0x3FF: Device 2 buffer |
| 1330 | * 0x400 ... 0x49F: Device 3 |
| 1331 | * 0x4C0 ... 0x4FF: Device 3 buffer |
| 1332 | * 0x500 ... 0x59F: Device 4 |
| 1333 | * 0x5C0 ... 0x5FF: Device 4 buffer |
| 1334 | * 0x600 ... 0x69F: Device 5 |
| 1335 | * 0x6C0 ... 0x6FF: Device 5 buffer |
| 1336 | * 0x700 ... 0x79F: Device 6 |
| 1337 | * 0x7C0 ... 0x7FF: Device 6 buffer |
| 1338 | * 0x800 ... 0x89F: Device 7 |
| 1339 | * 0x8C0 ... 0x8FF: Device 7 buffer |
| 1340 | * 0x900 ... 0x99F: Device 8 |
| 1341 | * 0x9C0 ... 0x9FF: Device 8 buffer |
| 1342 | * 0xA00 ... 0xA9F: Device 9 |
| 1343 | * 0xAC0 ... 0xAFF: Device 9 buffer |
| 1344 | * 0xB00 ... 0xB9F: Device 10 |
| 1345 | * 0xBC0 ... 0xBFF: Device 10 buffer |
| 1346 | * 0xC00 ... 0xC9F: Device 11 |
| 1347 | * 0xCC0 ... 0xCFF: Device 11 buffer |
| 1348 | * 0xD00 ... 0xD9F: Device 12 |
| 1349 | * 0xDC0 ... 0xDFF: Device 12 buffer |
| 1350 | * 0xE00 ... 0xE9F: Device 13 |
| 1351 | * 0xEC0 ... 0xEFF: Device 13 buffer |
| 1352 | * 0xF00 ... 0xF9F: Device 14 |
| 1353 | * 0xFC0 ... 0xFFF: Device 14 buffer |
| 1354 | * 0x1000 ... 0x109F: Device 15 |
| 1355 | * 0x10C0 ... 0x10BF: Device 15 buffer |
| 1356 | */ |
| 1357 | static void aspeed_i2c_realize(DeviceState *dev, Error **errp) |
| 1358 | { |
| 1359 | int i; |
| 1360 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 1361 | AspeedI2CState *s = ASPEED_I2C(dev); |
| 1362 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); |
| 1363 | uint32_t reg_offset = aic->reg_size + aic->reg_gap_size; |
| 1364 | uint32_t pool_offset = aic->pool_size + aic->pool_gap_size; |
| 1365 | |
| 1366 | sysbus_init_irq(sbd, &s->irq); |
| 1367 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, |
| 1368 | "aspeed.i2c", aic->mem_size); |
| 1369 | sysbus_init_mmio(sbd, &s->iomem); |
| 1370 | |
| 1371 | /* default value */ |
| 1372 | if (!s->bus_label) { |
| 1373 | s->bus_label = g_strdup(TYPE_ASPEED_I2C_BUS); |
| 1374 | } |
| 1375 | |
| 1376 | for (i = 0; i < aic->num_busses; i++) { |
| 1377 | Object *bus = OBJECT(&s->busses[i]); |
| 1378 | int offset = i < aic->gap ? 1 : 5; |
| 1379 | g_autofree char *name = g_strdup_printf("%s.%d", |
| 1380 | s->bus_label, i); |
| 1381 | |
| 1382 | if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { |
| 1383 | return; |
| 1384 | } |
| 1385 | |
| 1386 | if (!object_property_set_uint(bus, "bus-id", i, errp)) { |
| 1387 | return; |
| 1388 | } |
| 1389 | |
| 1390 | if (!object_property_set_str(bus, "bus-name", name, errp)) { |
| 1391 | return; |
| 1392 | } |
| 1393 | |
| 1394 | if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { |
| 1395 | return; |
| 1396 | } |
| 1397 | |
| 1398 | memory_region_add_subregion(&s->iomem, reg_offset * (i + offset), |
| 1399 | &s->busses[i].mr); |
| 1400 | } |
| 1401 | |
| 1402 | if (aic->has_share_pool) { |
| 1403 | memory_region_init_io(&s->pool_iomem, OBJECT(s), |
| 1404 | &aspeed_i2c_share_pool_ops, s, |
| 1405 | "aspeed.i2c-share-pool", aic->pool_size); |
| 1406 | memory_region_add_subregion(&s->iomem, aic->pool_base, |
| 1407 | &s->pool_iomem); |
| 1408 | } else { |
| 1409 | for (i = 0; i < aic->num_busses; i++) { |
| 1410 | memory_region_add_subregion(&s->iomem, |
| 1411 | aic->pool_base + (pool_offset * i), |
| 1412 | &s->busses[i].mr_pool); |
| 1413 | } |
| 1414 | } |
| 1415 | |
| 1416 | if (aic->has_dma) { |
| 1417 | if (!s->dram_mr) { |
| 1418 | error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); |
| 1419 | return; |
| 1420 | } |
| 1421 | |
| 1422 | address_space_init(&s->dram_as, s->dram_mr, |
| 1423 | TYPE_ASPEED_I2C "-dma-dram"); |
| 1424 | } |
| 1425 | } |
| 1426 | |
| 1427 | static const Property aspeed_i2c_properties[] = { |
| 1428 | DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, |
| 1429 | TYPE_MEMORY_REGION, MemoryRegion *), |
| 1430 | DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label), |
| 1431 | }; |
| 1432 | |
| 1433 | static void aspeed_i2c_class_init(ObjectClass *klass, const void *data) |
| 1434 | { |
| 1435 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1436 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 1437 | |
| 1438 | dc->vmsd = &aspeed_i2c_vmstate; |
| 1439 | rc->phases.hold = aspeed_i2c_reset_hold; |
| 1440 | device_class_set_props(dc, aspeed_i2c_properties); |
| 1441 | dc->realize = aspeed_i2c_realize; |
| 1442 | dc->desc = "Aspeed I2C Controller"; |
| 1443 | } |
| 1444 | |
| 1445 | static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus, |
| 1446 | enum i2c_event event) |
| 1447 | { |
| 1448 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); |
| 1449 | |
| 1450 | switch (event) { |
| 1451 | case I2C_START_SEND_ASYNC: |
| 1452 | if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) { |
| 1453 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1454 | "%s: Slave mode RX DMA is not enabled\n", __func__); |
| 1455 | return -1; |
| 1456 | } |
| 1457 | ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); |
| 1458 | bus->dma_dram_offset = |
| 1459 | deposit64(bus->dma_dram_offset, 0, 32, |
| 1460 | bus->regs[R_I2CS_DMA_RX_ADDR] & aic->dma_addr_lo_mask); |
| 1461 | bus->regs[R_I2CC_DMA_LEN] = |
| 1462 | ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1; |
| 1463 | i2c_ack(bus->bus); |
| 1464 | break; |
| 1465 | case I2C_FINISH: |
| 1466 | ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1); |
| 1467 | ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); |
| 1468 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, NORMAL_STOP, 1); |
| 1469 | SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, RX_DONE, 1); |
| 1470 | aspeed_i2c_bus_raise_slave_interrupt(bus); |
| 1471 | break; |
| 1472 | default: |
| 1473 | qemu_log_mask(LOG_UNIMP, "%s: i2c event %d unimplemented\n", |
| 1474 | __func__, event); |
| 1475 | return -1; |
| 1476 | } |
| 1477 | |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
| 1481 | static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event) |
| 1482 | { |
| 1483 | BusState *qbus = qdev_get_parent_bus(DEVICE(slave)); |
| 1484 | AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); |
| 1485 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 1486 | uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); |
| 1487 | uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus); |
| 1488 | uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr, |
| 1489 | SLAVE_DEV_ADDR1); |
| 1490 | |
| 1491 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 1492 | return aspeed_i2c_bus_new_slave_event(bus, event); |
| 1493 | } |
| 1494 | |
| 1495 | switch (event) { |
| 1496 | case I2C_START_SEND_ASYNC: |
| 1497 | /* Bit[0] == 0 indicates "send". */ |
| 1498 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1); |
| 1499 | |
| 1500 | ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); |
| 1501 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); |
| 1502 | |
| 1503 | aspeed_i2c_set_state(bus, I2CD_STXD); |
| 1504 | |
| 1505 | break; |
| 1506 | |
| 1507 | case I2C_FINISH: |
| 1508 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); |
| 1509 | |
| 1510 | aspeed_i2c_set_state(bus, I2CD_IDLE); |
| 1511 | |
| 1512 | break; |
| 1513 | |
| 1514 | default: |
| 1515 | return -1; |
| 1516 | } |
| 1517 | |
| 1518 | aspeed_i2c_bus_raise_interrupt(bus); |
| 1519 | |
| 1520 | return 0; |
| 1521 | } |
| 1522 | |
| 1523 | static void aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus *bus, uint8_t data) |
| 1524 | { |
| 1525 | assert(address_space_write(&bus->controller->dram_as, |
| 1526 | bus->dma_dram_offset, |
| 1527 | MEMTXATTRS_UNSPECIFIED, &data, 1) == MEMTX_OK); |
| 1528 | |
| 1529 | bus->dma_dram_offset++; |
| 1530 | bus->regs[R_I2CC_DMA_LEN]--; |
| 1531 | ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, |
| 1532 | ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN) + 1); |
| 1533 | i2c_ack(bus->bus); |
| 1534 | } |
| 1535 | |
| 1536 | static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data) |
| 1537 | { |
| 1538 | BusState *qbus = qdev_get_parent_bus(DEVICE(slave)); |
| 1539 | AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); |
| 1540 | uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); |
| 1541 | uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); |
| 1542 | |
| 1543 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 1544 | return aspeed_i2c_bus_new_slave_send_async(bus, data); |
| 1545 | } |
| 1546 | |
| 1547 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); |
| 1548 | SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); |
| 1549 | |
| 1550 | aspeed_i2c_bus_raise_interrupt(bus); |
| 1551 | } |
| 1552 | |
| 1553 | static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass, |
| 1554 | const void *data) |
| 1555 | { |
| 1556 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1557 | I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass); |
| 1558 | |
| 1559 | dc->desc = "Aspeed I2C Bus Slave"; |
| 1560 | |
| 1561 | sc->event = aspeed_i2c_bus_slave_event; |
| 1562 | sc->send_async = aspeed_i2c_bus_slave_send_async; |
| 1563 | } |
| 1564 | |
| 1565 | static void aspeed_i2c_bus_reset_hold(Object *obj, ResetType type) |
| 1566 | { |
| 1567 | AspeedI2CBus *s = ASPEED_I2C_BUS(obj); |
| 1568 | |
| 1569 | memset(s->regs, 0, sizeof(s->regs)); |
| 1570 | s->pending_intr_sts = 0; |
| 1571 | i2c_end_transfer(s->bus); |
| 1572 | /* |
| 1573 | * I2CC_VERSION_CTRL resets to all-ones. FUNC_CFG_DMA_EN is therefore set, |
| 1574 | * so master DMA targets DRAM unless the guest clears it to select buffer |
| 1575 | * mode. Guests unaware of buffer mode never touch this register and keep |
| 1576 | * doing DRAM DMA. |
| 1577 | */ |
| 1578 | s->regs[R_I2CC_VERSION_CTRL] = 0xffffffff; |
| 1579 | } |
| 1580 | |
| 1581 | static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) |
| 1582 | { |
| 1583 | AspeedI2CBus *s = ASPEED_I2C_BUS(dev); |
| 1584 | AspeedI2CClass *aic; |
| 1585 | g_autofree char *pool_name = NULL; |
| 1586 | |
| 1587 | if (!s->controller || !s->name) { |
| 1588 | error_setg(errp, TYPE_ASPEED_I2C_BUS |
| 1589 | ": 'controller' or 'bus-name' not set"); |
| 1590 | return; |
| 1591 | } |
| 1592 | |
| 1593 | pool_name = g_strdup_printf("%s.pool", s->name); |
| 1594 | |
| 1595 | aic = ASPEED_I2C_GET_CLASS(s->controller); |
| 1596 | |
| 1597 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); |
| 1598 | |
| 1599 | s->bus = i2c_init_bus(dev, s->name); |
| 1600 | s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, |
| 1601 | 0xff); |
| 1602 | |
| 1603 | memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, |
| 1604 | s, s->name, aic->reg_size); |
| 1605 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); |
| 1606 | |
| 1607 | memory_region_init_io(&s->mr_pool, OBJECT(s), &aspeed_i2c_bus_pool_ops, |
| 1608 | s, pool_name, aic->pool_size); |
| 1609 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool); |
| 1610 | } |
| 1611 | |
| 1612 | static const Property aspeed_i2c_bus_properties[] = { |
| 1613 | DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), |
| 1614 | DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, |
| 1615 | AspeedI2CState *), |
| 1616 | DEFINE_PROP_STRING("bus-name", AspeedI2CBus, name), |
| 1617 | }; |
| 1618 | |
| 1619 | static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data) |
| 1620 | { |
| 1621 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1622 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 1623 | |
| 1624 | dc->desc = "Aspeed I2C Bus"; |
| 1625 | dc->realize = aspeed_i2c_bus_realize; |
| 1626 | rc->phases.hold = aspeed_i2c_bus_reset_hold; |
| 1627 | device_class_set_props(dc, aspeed_i2c_bus_properties); |
| 1628 | } |
| 1629 | |
| 1630 | static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) |
| 1631 | { |
| 1632 | return bus->controller->irq; |
| 1633 | } |
| 1634 | |
| 1635 | static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) |
| 1636 | { |
| 1637 | uint8_t *pool_page = |
| 1638 | &bus->controller->share_pool[ARRAY_FIELD_EX32(bus->regs, |
| 1639 | I2CD_FUN_CTRL, |
| 1640 | POOL_PAGE_SEL) * 0x100]; |
| 1641 | |
| 1642 | return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; |
| 1643 | } |
| 1644 | |
| 1645 | static void aspeed_2400_i2c_class_init(ObjectClass *klass, const void *data) |
| 1646 | { |
| 1647 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1648 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1649 | |
| 1650 | dc->desc = "ASPEED 2400 I2C Controller"; |
| 1651 | |
| 1652 | aic->num_busses = 14; |
| 1653 | aic->reg_size = 0x40; |
| 1654 | aic->gap = 7; |
| 1655 | aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; |
| 1656 | aic->has_share_pool = true; |
| 1657 | aic->pool_size = 0x800; |
| 1658 | aic->pool_base = 0x800; |
| 1659 | aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; |
| 1660 | aic->mem_size = 0x1000; |
| 1661 | } |
| 1662 | |
| 1663 | static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) |
| 1664 | { |
| 1665 | return bus->controller->irq; |
| 1666 | } |
| 1667 | |
| 1668 | static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) |
| 1669 | { |
| 1670 | return bus->pool; |
| 1671 | } |
| 1672 | |
| 1673 | static void aspeed_2500_i2c_class_init(ObjectClass *klass, const void *data) |
| 1674 | { |
| 1675 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1676 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1677 | |
| 1678 | dc->desc = "ASPEED 2500 I2C Controller"; |
| 1679 | |
| 1680 | aic->num_busses = 14; |
| 1681 | aic->reg_size = 0x40; |
| 1682 | aic->gap = 7; |
| 1683 | aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; |
| 1684 | aic->pool_size = 0x10; |
| 1685 | aic->pool_base = 0x200; |
| 1686 | aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; |
| 1687 | aic->check_sram = true; |
| 1688 | aic->has_dma = true; |
| 1689 | aic->mem_size = 0x1000; |
| 1690 | aic->dma_addr_lo_mask = 0x3ffffffc; |
| 1691 | } |
| 1692 | |
| 1693 | static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) |
| 1694 | { |
| 1695 | return bus->irq; |
| 1696 | } |
| 1697 | |
| 1698 | static void aspeed_2600_i2c_class_init(ObjectClass *klass, const void *data) |
| 1699 | { |
| 1700 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1701 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1702 | |
| 1703 | dc->desc = "ASPEED 2600 I2C Controller"; |
| 1704 | |
| 1705 | aic->num_busses = 16; |
| 1706 | aic->reg_size = 0x80; |
| 1707 | aic->gap = -1; /* no gap */ |
| 1708 | aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; |
| 1709 | aic->pool_size = 0x20; |
| 1710 | aic->pool_base = 0xC00; |
| 1711 | aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; |
| 1712 | aic->has_dma = true; |
| 1713 | aic->mem_size = 0x1000; |
| 1714 | aic->dma_addr_lo_mask = 0x7fffffff; |
| 1715 | } |
| 1716 | |
| 1717 | static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *data) |
| 1718 | { |
| 1719 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1720 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1721 | |
| 1722 | dc->desc = "ASPEED 1030 I2C Controller"; |
| 1723 | |
| 1724 | aic->num_busses = 14; |
| 1725 | aic->reg_size = 0x80; |
| 1726 | aic->gap = -1; /* no gap */ |
| 1727 | aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; |
| 1728 | aic->pool_size = 0x20; |
| 1729 | aic->pool_base = 0xC00; |
| 1730 | aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; |
| 1731 | aic->has_dma = true; |
| 1732 | aic->mem_size = 0x10000; |
| 1733 | aic->dma_addr_lo_mask = 0x7fffffff; |
| 1734 | } |
| 1735 | |
| 1736 | static void aspeed_1040_i2c_class_init(ObjectClass *klass, const void *data) |
| 1737 | { |
| 1738 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1739 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1740 | |
| 1741 | dc->desc = "ASPEED 1040 I2C Controller"; |
| 1742 | |
| 1743 | /* |
| 1744 | * AST1040 reuses the AST2700 I2C controller implementation since |
| 1745 | * the AST1040 is compatible with AST2700. AST1040 has 14 I2C buses, |
| 1746 | * and its HyperRAM is limited to 16 MiB, so the DMA low address |
| 1747 | * mask is restricted accordingly. |
| 1748 | */ |
| 1749 | aic->num_busses = 14; |
| 1750 | aic->reg_size = 0xa0; |
| 1751 | aic->reg_gap_size = 0x60; |
| 1752 | aic->gap = -1; /* no gap */ |
| 1753 | aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; |
| 1754 | aic->pool_size = 0x40; |
| 1755 | aic->pool_gap_size = 0xc0; |
| 1756 | aic->pool_base = 0x1c0; |
| 1757 | aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; |
| 1758 | aic->has_dma = true; |
| 1759 | aic->mem_size = 0x2000; |
| 1760 | aic->has_dma64 = true; |
| 1761 | aic->dma_addr_lo_mask = 0x00ffffff; |
| 1762 | } |
| 1763 | |
| 1764 | static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data) |
| 1765 | { |
| 1766 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1767 | AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); |
| 1768 | |
| 1769 | dc->desc = "ASPEED 2700 I2C Controller"; |
| 1770 | |
| 1771 | aic->num_busses = 16; |
| 1772 | aic->reg_size = 0xa0; |
| 1773 | aic->reg_gap_size = 0x60; |
| 1774 | aic->gap = -1; /* no gap */ |
| 1775 | aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; |
| 1776 | aic->pool_size = 0x40; |
| 1777 | aic->pool_gap_size = 0xc0; |
| 1778 | aic->pool_base = 0x1c0; |
| 1779 | aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; |
| 1780 | aic->has_dma = true; |
| 1781 | aic->mem_size = 0x2000; |
| 1782 | aic->has_dma64 = true; |
| 1783 | aic->dma_addr_lo_mask = 0xffffffff; |
| 1784 | } |
| 1785 | |
| 1786 | static const TypeInfo aspeed_i2c_types[] = { |
| 1787 | { |
| 1788 | .name = TYPE_ASPEED_I2C_BUS, |
| 1789 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1790 | .instance_size = sizeof(AspeedI2CBus), |
| 1791 | .class_init = aspeed_i2c_bus_class_init, |
| 1792 | }, |
| 1793 | { |
| 1794 | .name = TYPE_ASPEED_I2C_BUS_SLAVE, |
| 1795 | .parent = TYPE_I2C_SLAVE, |
| 1796 | .instance_size = sizeof(AspeedI2CBusSlave), |
| 1797 | .class_init = aspeed_i2c_bus_slave_class_init, |
| 1798 | }, |
| 1799 | { |
| 1800 | .name = TYPE_ASPEED_I2C, |
| 1801 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1802 | .instance_init = aspeed_i2c_instance_init, |
| 1803 | .instance_size = sizeof(AspeedI2CState), |
| 1804 | .class_init = aspeed_i2c_class_init, |
| 1805 | .class_size = sizeof(AspeedI2CClass), |
| 1806 | .abstract = true, |
| 1807 | }, |
| 1808 | { |
| 1809 | .name = TYPE_ASPEED_1030_I2C, |
| 1810 | .parent = TYPE_ASPEED_I2C, |
| 1811 | .class_init = aspeed_1030_i2c_class_init, |
| 1812 | }, |
| 1813 | { |
| 1814 | .name = TYPE_ASPEED_1040_I2C, |
| 1815 | .parent = TYPE_ASPEED_I2C, |
| 1816 | .class_init = aspeed_1040_i2c_class_init, |
| 1817 | }, |
| 1818 | { |
| 1819 | .name = TYPE_ASPEED_2400_I2C, |
| 1820 | .parent = TYPE_ASPEED_I2C, |
| 1821 | .class_init = aspeed_2400_i2c_class_init, |
| 1822 | }, |
| 1823 | { |
| 1824 | .name = TYPE_ASPEED_2500_I2C, |
| 1825 | .parent = TYPE_ASPEED_I2C, |
| 1826 | .class_init = aspeed_2500_i2c_class_init, |
| 1827 | }, |
| 1828 | { |
| 1829 | .name = TYPE_ASPEED_2600_I2C, |
| 1830 | .parent = TYPE_ASPEED_I2C, |
| 1831 | .class_init = aspeed_2600_i2c_class_init, |
| 1832 | }, |
| 1833 | { |
| 1834 | .name = TYPE_ASPEED_2700_I2C, |
| 1835 | .parent = TYPE_ASPEED_I2C, |
| 1836 | .class_init = aspeed_2700_i2c_class_init, |
| 1837 | } |
| 1838 | }; |
| 1839 | |
| 1840 | DEFINE_TYPES(aspeed_i2c_types) |
| 1841 | |
| 1842 | |
| 1843 | I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) |
| 1844 | { |
| 1845 | AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); |
| 1846 | I2CBus *bus = NULL; |
| 1847 | |
| 1848 | if (busnr >= 0 && busnr < aic->num_busses) { |
| 1849 | bus = s->busses[busnr].bus; |
| 1850 | } |
| 1851 | |
| 1852 | return bus; |
| 1853 | } |