@samitouri / QOSamiQemu
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1 /*
2 * Microbit stub for Nordic Semiconductor nRF51 SoC Two-Wire Interface
3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
4 *
5 * This is a microbit-specific stub for the TWI controller on the nRF51 SoC.
6 * We don't emulate I2C devices but the firmware probes the
7 * accelerometer/magnetometer on startup and panics if they are not found.
8 * Therefore we stub out the probing.
9 *
10 * In the future this file could evolve into a full nRF51 TWI controller
11 * device.
12 *
13 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
14 * Copyright 2019 Red Hat, Inc.
15 *
16 * This code is licensed under the GPL version 2 or later. See
17 * the COPYING file in the top-level directory.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "hw/i2c/microbit_i2c.h"
24 #include "migration/vmstate.h"
25
26 static const uint32_t twi_read_sequence[] = {0x5A, 0x5A, 0x40};
27
28 static uint64_t microbit_i2c_read(void *opaque, hwaddr addr, unsigned int size)
29 {
30 MicrobitI2CState *s = opaque;
31 uint64_t data = 0x00;
32
33 switch (addr) {
34 case NRF51_TWI_EVENT_STOPPED:
35 data = 0x01;
36 break;
37 case NRF51_TWI_EVENT_RXDREADY:
38 data = 0x01;
39 break;
40 case NRF51_TWI_EVENT_TXDSENT:
41 data = 0x01;
42 break;
43 case NRF51_TWI_REG_RXD:
44 /*
45 * Return the next byte from our fake data sequence. If
46 * the guest keeps reading the register after that, keep
47 * returning the same last byte value.
48 */
49 data = twi_read_sequence[s->read_idx];
50 if (s->read_idx + 1 < G_N_ELEMENTS(twi_read_sequence)) {
51 s->read_idx++;
52 }
53 break;
54 default:
55 data = s->regs[addr / sizeof(s->regs[0])];
56 break;
57 }
58
59 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u] = %" PRIx32 "\n",
60 __func__, addr, size, (uint32_t)data);
61
62
63 return data;
64 }
65
66 static void microbit_i2c_write(void *opaque, hwaddr addr, uint64_t data,
67 unsigned int size)
68 {
69 MicrobitI2CState *s = opaque;
70
71 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
72 __func__, addr, data, size);
73 s->regs[addr / sizeof(s->regs[0])] = data;
74 }
75
76 static const MemoryRegionOps microbit_i2c_ops = {
77 .read = microbit_i2c_read,
78 .write = microbit_i2c_write,
79 .endianness = DEVICE_LITTLE_ENDIAN,
80 .impl.min_access_size = 4,
81 .impl.max_access_size = 4,
82 };
83
84 static const VMStateDescription microbit_i2c_vmstate = {
85 .name = TYPE_MICROBIT_I2C,
86 .version_id = 1,
87 .minimum_version_id = 1,
88 .fields = (const VMStateField[]) {
89 VMSTATE_UINT32_ARRAY(regs, MicrobitI2CState, MICROBIT_I2C_NREGS),
90 VMSTATE_UINT32(read_idx, MicrobitI2CState),
91 VMSTATE_END_OF_LIST()
92 },
93 };
94
95 static void microbit_i2c_reset(DeviceState *dev)
96 {
97 MicrobitI2CState *s = MICROBIT_I2C(dev);
98
99 memset(s->regs, 0, sizeof(s->regs));
100 s->read_idx = 0;
101 }
102
103 static void microbit_i2c_realize(DeviceState *dev, Error **errp)
104 {
105 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
106 MicrobitI2CState *s = MICROBIT_I2C(dev);
107
108 memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
109 "microbit.twi", NRF51_PERIPHERAL_SIZE);
110 sysbus_init_mmio(sbd, &s->iomem);
111 }
112
113 static void microbit_i2c_class_init(ObjectClass *klass, const void *data)
114 {
115 DeviceClass *dc = DEVICE_CLASS(klass);
116
117 dc->vmsd = &microbit_i2c_vmstate;
118 device_class_set_legacy_reset(dc, microbit_i2c_reset);
119 dc->realize = microbit_i2c_realize;
120 dc->desc = "Microbit I2C controller";
121 }
122
123 static const TypeInfo microbit_i2c_info = {
124 .name = TYPE_MICROBIT_I2C,
125 .parent = TYPE_SYS_BUS_DEVICE,
126 .instance_size = sizeof(MicrobitI2CState),
127 .class_init = microbit_i2c_class_init,
128 };
129
130 static void microbit_i2c_register_types(void)
131 {
132 type_register_static(&microbit_i2c_info);
133 }
134
135 type_init(microbit_i2c_register_types)