@samitouri / QOSamiQemu
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1 /*
2 * QEMU SMBus EEPROM device
3 *
4 * Copyright (c) 2007 Arastra, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "hw/core/boards.h"
29 #include "hw/i2c/i2c.h"
30 #include "hw/i2c/smbus_slave.h"
31 #include "hw/core/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "hw/i2c/smbus_eeprom.h"
34 #include "qom/object.h"
35
36 //#define DEBUG
37
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
39
40 OBJECT_DECLARE_SIMPLE_TYPE(SMBusEEPROMDevice, SMBUS_EEPROM)
41
42 #define SMBUS_EEPROM_SIZE 256
43
44 struct SMBusEEPROMDevice {
45 SMBusDevice smbusdev;
46 uint8_t data[SMBUS_EEPROM_SIZE];
47 uint8_t *init_data;
48 uint8_t offset;
49 bool accessed;
50 };
51
52 static uint8_t eeprom_receive_byte(SMBusDevice *dev)
53 {
54 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
55 uint8_t *data = eeprom->data;
56 uint8_t val = data[eeprom->offset++];
57
58 eeprom->accessed = true;
59 #ifdef DEBUG
60 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n",
61 dev->i2c.address, val);
62 #endif
63 return val;
64 }
65
66 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len)
67 {
68 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
69 uint8_t *data = eeprom->data;
70
71 eeprom->accessed = true;
72 #ifdef DEBUG
73 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n",
74 dev->i2c.address, buf[0], buf[1]);
75 #endif
76 /* len is guaranteed to be > 0 */
77 eeprom->offset = buf[0];
78 buf++;
79 len--;
80
81 for (; len > 0; len--) {
82 data[eeprom->offset] = *buf++;
83 eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;
84 }
85
86 return 0;
87 }
88
89 static bool smbus_eeprom_vmstate_needed(void *opaque)
90 {
91 SMBusEEPROMDevice *eeprom = opaque;
92
93 return eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev);
94 }
95
96 static const VMStateDescription vmstate_smbus_eeprom = {
97 .name = "smbus-eeprom",
98 .version_id = 1,
99 .minimum_version_id = 1,
100 .needed = smbus_eeprom_vmstate_needed,
101 .fields = (const VMStateField[]) {
102 VMSTATE_SMBUS_DEVICE(smbusdev, SMBusEEPROMDevice),
103 VMSTATE_UINT8_ARRAY(data, SMBusEEPROMDevice, SMBUS_EEPROM_SIZE),
104 VMSTATE_UINT8(offset, SMBusEEPROMDevice),
105 VMSTATE_BOOL(accessed, SMBusEEPROMDevice),
106 VMSTATE_END_OF_LIST()
107 }
108 };
109
110 /*
111 * Reset the EEPROM contents to the initial state on a reset. This
112 * isn't really how an EEPROM works, of course, but the general
113 * principle of QEMU is to restore function on reset to what it would
114 * be if QEMU was stopped and started.
115 *
116 * The proper thing to do would be to have a backing blockdev to hold
117 * the contents and restore that on startup, and not do this on reset.
118 * But until that time, act as if we had been stopped and restarted.
119 */
120 static void smbus_eeprom_reset(DeviceState *dev)
121 {
122 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
123
124 memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE);
125 eeprom->offset = 0;
126 }
127
128 static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
129 {
130 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
131
132 smbus_eeprom_reset(dev);
133 if (eeprom->init_data == NULL) {
134 error_setg(errp, "init_data cannot be NULL");
135 }
136 }
137
138 static void smbus_eeprom_class_initfn(ObjectClass *klass, const void *data)
139 {
140 DeviceClass *dc = DEVICE_CLASS(klass);
141 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass);
142
143 dc->realize = smbus_eeprom_realize;
144 device_class_set_legacy_reset(dc, smbus_eeprom_reset);
145 sc->receive_byte = eeprom_receive_byte;
146 sc->write_data = eeprom_write_data;
147 dc->vmsd = &vmstate_smbus_eeprom;
148 /* Reason: init_data */
149 dc->user_creatable = false;
150 }
151
152 static const TypeInfo smbus_eeprom_types[] = {
153 {
154 .name = TYPE_SMBUS_EEPROM,
155 .parent = TYPE_SMBUS_DEVICE,
156 .instance_size = sizeof(SMBusEEPROMDevice),
157 .class_init = smbus_eeprom_class_initfn,
158 },
159 };
160
161 DEFINE_TYPES(smbus_eeprom_types)
162
163 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
164 {
165 DeviceState *dev;
166
167 dev = qdev_new(TYPE_SMBUS_EEPROM);
168 qdev_prop_set_uint8(dev, "address", address);
169 /* FIXME: use an array of byte or block backend property? */
170 SMBUS_EEPROM(dev)->init_data = eeprom_buf;
171 qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal);
172 }
173
174 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
175 const uint8_t *eeprom_spd, int eeprom_spd_size)
176 {
177 int i;
178 /* XXX: make this persistent */
179
180 assert(nb_eeprom <= 8);
181 uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);
182 if (eeprom_spd_size > 0) {
183 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
184 }
185
186 for (i = 0; i < nb_eeprom; i++) {
187 smbus_eeprom_init_one(smbus, 0x50 + i,
188 eeprom_buf + (i * SMBUS_EEPROM_SIZE));
189 }
190 }
191
192 /* Generate SDRAM SPD EEPROM data describing a module of type and size */
193 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size)
194 {
195 uint8_t *spd;
196 uint8_t nbanks;
197 uint16_t density;
198 uint32_t size;
199 int min_log2, max_log2, sz_log2;
200 int i;
201
202 switch (type) {
203 case SDR:
204 min_log2 = 2;
205 max_log2 = 9;
206 break;
207 case DDR:
208 min_log2 = 5;
209 max_log2 = 12;
210 break;
211 case DDR2:
212 min_log2 = 7;
213 max_log2 = 14;
214 break;
215 default:
216 g_assert_not_reached();
217 }
218 size = ram_size >> 20; /* work in terms of megabytes */
219 sz_log2 = 31 - clz32(size);
220 size = 1U << sz_log2;
221 assert(ram_size == size * MiB);
222 assert(sz_log2 >= min_log2);
223
224 nbanks = 1;
225 while (sz_log2 > max_log2 && nbanks < 8) {
226 sz_log2--;
227 nbanks *= 2;
228 }
229
230 assert(size == (1ULL << sz_log2) * nbanks);
231
232 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */
233 if (nbanks == 1 && sz_log2 > min_log2) {
234 sz_log2--;
235 nbanks++;
236 }
237
238 density = 1ULL << (sz_log2 - 2);
239 switch (type) {
240 case DDR2:
241 density = (density & 0xe0) | (density >> 8 & 0x1f);
242 break;
243 case DDR:
244 density = (density & 0xf8) | (density >> 8 & 0x07);
245 break;
246 case SDR:
247 default:
248 density &= 0xff;
249 break;
250 }
251
252 spd = g_malloc0(256);
253 spd[0] = 128; /* data bytes in EEPROM */
254 spd[1] = 8; /* log2 size of EEPROM */
255 spd[2] = type;
256 spd[3] = 13; /* row address bits */
257 spd[4] = 10; /* column address bits */
258 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks);
259 spd[6] = 64; /* module data width */
260 /* reserved / data width high */
261 spd[8] = 4; /* interface voltage level */
262 spd[9] = 0x25; /* highest CAS latency */
263 spd[10] = 1; /* access time */
264 /* DIMM configuration 0 = non-ECC */
265 spd[12] = 0x82; /* refresh requirements */
266 spd[13] = 8; /* primary SDRAM width */
267 /* ECC SDRAM width */
268 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */
269 spd[16] = 12; /* burst lengths supported */
270 spd[17] = 4; /* banks per SDRAM device */
271 spd[18] = 12; /* ~CAS latencies supported */
272 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */
273 spd[20] = 2; /* DIMM type / ~WE latencies */
274 spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */
275 /* memory chip features */
276 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */
277 /* data access time */
278 /* clock cycle time @ short CAS latency */
279 /* data access time */
280 spd[27] = 20; /* min. row precharge time */
281 spd[28] = 15; /* min. row active row delay */
282 spd[29] = 20; /* min. ~RAS to ~CAS delay */
283 spd[30] = 45; /* min. active to precharge time */
284 spd[31] = density;
285 spd[32] = 20; /* addr/cmd setup time */
286 spd[33] = 8; /* addr/cmd hold time */
287 spd[34] = 20; /* data input setup time */
288 spd[35] = 8; /* data input hold time */
289 spd[36] = (type == DDR2 ? 13 << 2 : 0); /* min. write recovery time */
290
291 /* checksum */
292 for (i = 0; i < 63; i++) {
293 spd[63] += spd[i];
294 }
295 return spd;
296 }