| 1 | /* |
| 2 | * ACPI implementation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> |
| 6 | * VA Linux Systems Japan K.K. |
| 7 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, see <http://www.gnu.org/licenses/> |
| 21 | */ |
| 22 | |
| 23 | #include "qemu/osdep.h" |
| 24 | #include "qemu/range.h" |
| 25 | #include "hw/i2c/pm_smbus.h" |
| 26 | #include "hw/pci/pci.h" |
| 27 | #include "migration/vmstate.h" |
| 28 | #include "qemu/module.h" |
| 29 | |
| 30 | #include "hw/southbridge/ich9.h" |
| 31 | #include "qom/object.h" |
| 32 | #include "hw/acpi/acpi_aml_interface.h" |
| 33 | |
| 34 | OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE) |
| 35 | |
| 36 | struct ICH9SMBState { |
| 37 | PCIDevice dev; |
| 38 | |
| 39 | bool irq_enabled; |
| 40 | |
| 41 | PMSMBus smb; |
| 42 | }; |
| 43 | |
| 44 | static const VMStateDescription vmstate_ich9_smbus = { |
| 45 | .name = "ich9_smb", |
| 46 | .version_id = 1, |
| 47 | .minimum_version_id = 1, |
| 48 | .fields = (const VMStateField[]) { |
| 49 | VMSTATE_PCI_DEVICE(dev, ICH9SMBState), |
| 50 | VMSTATE_BOOL(irq_enabled, ICH9SMBState), |
| 51 | VMSTATE_STRUCT(smb, ICH9SMBState, 1, pmsmb_vmstate, PMSMBus), |
| 52 | VMSTATE_END_OF_LIST() |
| 53 | } |
| 54 | }; |
| 55 | |
| 56 | static void ich9_smbus_write_config(PCIDevice *d, uint32_t address, |
| 57 | uint32_t val, int len) |
| 58 | { |
| 59 | ICH9SMBState *s = ICH9_SMB_DEVICE(d); |
| 60 | |
| 61 | pci_default_write_config(d, address, val, len); |
| 62 | if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) { |
| 63 | uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC]; |
| 64 | if (hostc & ICH9_SMB_HOSTC_HST_EN) { |
| 65 | memory_region_set_enabled(&s->smb.io, true); |
| 66 | } else { |
| 67 | memory_region_set_enabled(&s->smb.io, false); |
| 68 | } |
| 69 | s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0; |
| 70 | if (hostc & ICH9_SMB_HOSTC_SSRESET) { |
| 71 | s->smb.reset(&s->smb); |
| 72 | s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET; |
| 73 | } |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled) |
| 78 | { |
| 79 | ICH9SMBState *s = pmsmb->opaque; |
| 80 | |
| 81 | if (enabled == s->irq_enabled) { |
| 82 | return; |
| 83 | } |
| 84 | |
| 85 | s->irq_enabled = enabled; |
| 86 | pci_set_irq(&s->dev, enabled); |
| 87 | } |
| 88 | |
| 89 | static void ich9_smbus_realize(PCIDevice *d, Error **errp) |
| 90 | { |
| 91 | ICH9SMBState *s = ICH9_SMB_DEVICE(d); |
| 92 | |
| 93 | /* TODO? D31IP.SMIP in chipset configuration space */ |
| 94 | pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */ |
| 95 | |
| 96 | pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); |
| 97 | /* TODO bar0, bar1: 64bit BAR support*/ |
| 98 | |
| 99 | pm_smbus_init(&d->qdev, &s->smb, false); |
| 100 | pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO, |
| 101 | &s->smb.io); |
| 102 | |
| 103 | s->smb.set_irq = ich9_smb_set_irq; |
| 104 | s->smb.opaque = s; |
| 105 | } |
| 106 | |
| 107 | static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope) |
| 108 | { |
| 109 | ICH9SMBState *s = ICH9_SMB_DEVICE(adev); |
| 110 | BusState *bus = BUS(s->smb.smbus); |
| 111 | |
| 112 | qbus_build_aml(bus, scope); |
| 113 | } |
| 114 | |
| 115 | static void ich9_smb_class_init(ObjectClass *klass, const void *data) |
| 116 | { |
| 117 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 118 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 119 | AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); |
| 120 | |
| 121 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 122 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6; |
| 123 | k->revision = ICH9_A2_SMB_REVISION; |
| 124 | k->class_id = PCI_CLASS_SERIAL_SMBUS; |
| 125 | dc->vmsd = &vmstate_ich9_smbus; |
| 126 | dc->desc = "ICH9 SMBUS Bridge"; |
| 127 | k->realize = ich9_smbus_realize; |
| 128 | k->config_write = ich9_smbus_write_config; |
| 129 | /* |
| 130 | * Reason: part of ICH9 southbridge, needs to be wired up by |
| 131 | * pc_q35_init() |
| 132 | */ |
| 133 | dc->user_creatable = false; |
| 134 | adevc->build_dev_aml = build_ich9_smb_aml; |
| 135 | } |
| 136 | |
| 137 | static const TypeInfo ich9_smb_info = { |
| 138 | .name = TYPE_ICH9_SMB_DEVICE, |
| 139 | .parent = TYPE_PCI_DEVICE, |
| 140 | .instance_size = sizeof(ICH9SMBState), |
| 141 | .class_init = ich9_smb_class_init, |
| 142 | .interfaces = (const InterfaceInfo[]) { |
| 143 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 144 | { TYPE_ACPI_DEV_AML_IF }, |
| 145 | { }, |
| 146 | }, |
| 147 | }; |
| 148 | |
| 149 | static void ich9_smb_register(void) |
| 150 | { |
| 151 | type_register_static(&ich9_smb_info); |
| 152 | } |
| 153 | |
| 154 | type_init(ich9_smb_register); |