acpi-build.c · samitouri/QOSamiQemu

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1	/* Support for generating ACPI tables and passing them to Guests
2	*
3	* Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4	* Copyright (C) 2006 Fabrice Bellard
5	* Copyright (C) 2013 Red Hat Inc
6	*
7	* Author: Michael S. Tsirkin <mst@redhat.com>
8	*
9	* This program is free software; you can redistribute it and/or modify
10	* it under the terms of the GNU General Public License as published by
11	* the Free Software Foundation; either version 2 of the License, or
12	* (at your option) any later version.
13
14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.
18
19	* You should have received a copy of the GNU General Public License along
20	* with this program; if not, see <http://www.gnu.org/licenses/>.
21	*/
22
23	#include "qemu/osdep.h"
24	#include "qapi/error.h"
25	#include "qobject/qnum.h"
26	#include "acpi-build.h"
27	#include "acpi-common.h"
28	#include "qemu/bitmap.h"
29	#include "qemu/error-report.h"
30	#include "hw/pci/pci_bridge.h"
31	#include "hw/cxl/cxl.h"
32	#include "hw/core/cpu.h"
33	#include "target/i386/cpu.h"
34	#include "hw/timer/hpet.h"
35	#include "hw/acpi/acpi-defs.h"
36	#include "hw/acpi/acpi.h"
37	#include "hw/acpi/cpu.h"
38	#include "hw/acpi/pc-hotplug.h"
39	#include "hw/nvram/fw_cfg.h"
40	#include "hw/acpi/bios-linker-loader.h"
41	#include "hw/acpi/acpi_aml_interface.h"
42	#include "hw/input/i8042.h"
43	#include "hw/acpi/memory_hotplug.h"
44	#include "system/tpm.h"
45	#include "hw/acpi/tpm.h"
46	#include "hw/acpi/vmgenid.h"
47	#include "hw/acpi/vmclock.h"
48	#include "hw/acpi/erst.h"
49	#include "hw/acpi/piix4.h"
50	#include "system/tpm_backend.h"
51	#include "hw/rtc/mc146818rtc_regs.h"
52	#include "migration/vmstate.h"
53	#include "hw/mem/memory-device.h"
54	#include "hw/mem/nvdimm.h"
55	#include "hw/mem/sp-mem.h"
56	#include "system/numa.h"
57	#include "system/reset.h"
58	#include "hw/hyperv/vmbus-bridge.h"
59
60	/* Supported chipsets: */
61	#include "hw/southbridge/ich9.h"
62	#include "hw/acpi/pcihp.h"
63	#include "hw/i386/fw_cfg.h"
64	#include "hw/i386/pc.h"
65	#include "hw/pci/pci_bus.h"
66	#include "hw/pci-host/i440fx.h"
67	#include "hw/pci-host/q35.h"
68	#include "hw/i386/x86-iommu.h"
69
70	#include "hw/acpi/aml-build.h"
71	#include "hw/acpi/utils.h"
72	#include "hw/acpi/pci.h"
73	#include "hw/acpi/cxl.h"
74
75	#include "qom/qom-qobject.h"
76	#include "hw/i386/amd_iommu.h"
77	#include "hw/i386/intel_iommu.h"
78	#include "hw/virtio/virtio-iommu.h"
79
80	#include "hw/acpi/hmat.h"
81	#include "hw/acpi/viot.h"
82	#include "hw/acpi/wdat-ich9.h"
83
84	#include CONFIG_DEVICES
85
86	/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
87	* -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
88	* a little bit, there should be plenty of free space since the DSDT
89	* shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
90	*/
91	#define ACPI_BUILD_ALIGN_SIZE 0x1000
92
93	#define ACPI_BUILD_TABLE_SIZE 0x20000
94
95	/* #define DEBUG_ACPI_BUILD */
96	#ifdef DEBUG_ACPI_BUILD
97	#define ACPI_BUILD_DPRINTF(fmt, ...) \
98	do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
99	#else
100	#define ACPI_BUILD_DPRINTF(fmt, ...)
101	#endif
102
103	typedef struct AcpiPmInfo {
104	bool s3_disabled;
105	bool s4_disabled;
106	bool pcihp_bridge_en;
107	bool smi_on_cpuhp;
108	bool smi_on_cpu_unplug;
109	bool pcihp_root_en;
110	uint8_t s4_val;
111	AcpiFadtData fadt;
112	uint16_t cpu_hp_io_base;
113	uint16_t pcihp_io_base;
114	uint16_t pcihp_io_len;
115	uint64_t tco_io_base;
116	} AcpiPmInfo;
117
118	typedef struct AcpiMiscInfo {
119	bool has_hpet;
120	#ifdef CONFIG_TPM
121	TPMVersion tpm_version;
122	#endif
123	} AcpiMiscInfo;
124
125	typedef struct FwCfgTPMConfig {
126	uint32_t tpmppi_address;
127	uint8_t tpm_version;
128	uint8_t tpmppi_version;
129	} QEMU_PACKED FwCfgTPMConfig;
130
131	static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
132
133	const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
134	.space_id = AML_AS_SYSTEM_IO,
135	.address = NVDIMM_ACPI_IO_BASE,
136	.bit_width = NVDIMM_ACPI_IO_LEN << 3
137	};
138
139	static void init_common_fadt_data(MachineState ms, Object o,
140	AcpiFadtData *data)
141	{
142	X86MachineState *x86ms = X86_MACHINE(ms);
143	/*
144	* "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
145	* behavior for compatibility irrelevant to smm_enabled, which doesn't
146	* conform to the ACPI spec.
147	*/
148	bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
149	true : x86_machine_is_smm_enabled(x86ms);
150	uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
151	AmlAddressSpace as = AML_AS_SYSTEM_IO;
152	AcpiFadtData fadt = {
153	.rev = 3,
154	.flags =
155	(1 << ACPI_FADT_F_WBINVD) \|
156	(1 << ACPI_FADT_F_PROC_C1) \|
157	(1 << ACPI_FADT_F_SLP_BUTTON) \|
158	(1 << ACPI_FADT_F_RTC_S4) \|
159	(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) \|
160	/* APIC destination mode ("Flat Logical") has an upper limit of 8
161	* CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
162	* used
163	*/
164	((ms->smp.max_cpus > 8) ?
165	(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
166	.int_model = 1 /* Multiple APIC */,
167	.rtc_century = RTC_CENTURY,
168	.plvl2_lat = 0xfff /* C2 state not supported */,
169	.plvl3_lat = 0xfff /* C3 state not supported */,
170	.smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
171	.sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
172	.acpi_enable_cmd =
173	smm_enabled ?
174	object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
175	0,
176	.acpi_disable_cmd =
177	smm_enabled ?
178	object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
179	0,
180	.pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
181	.pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
182	.address = io + 0x04 },
183	.pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
184	.gpe0_blk = { .space_id = as, .bit_width =
185	object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
186	.address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
187	},
188	};
189
190	/*
191	* ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
192	* Flags, bit offset 1 - 8042.
193	*/
194	fadt.iapc_boot_arch = iapc_boot_arch_8042();
195
196	*data = fadt;
197	}
198
199	static void acpi_get_pm_info(MachineState machine, AcpiPmInfo pm)
200	{
201	Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
202	Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
203	Object *obj = piix ? piix : lpc;
204	QObject *o;
205	pm->cpu_hp_io_base = 0;
206	pm->pcihp_io_base = 0;
207	pm->pcihp_io_len = 0;
208	pm->smi_on_cpuhp = false;
209	pm->smi_on_cpu_unplug = false;
210	pm->tco_io_base = 0;
211
212	assert(obj);
213	init_common_fadt_data(machine, obj, &pm->fadt);
214	if (piix) {
215	/* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
216	pm->fadt.rev = 1;
217	pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
218	}
219	if (lpc) {
220	uint64_t smi_features = object_property_get_uint(lpc,
221	ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
222	struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
223	.bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
224	pm->fadt.reset_reg = r;
225	pm->fadt.reset_val = 0xf;
226	pm->fadt.flags \|= 1 << ACPI_FADT_F_RESET_REG_SUP;
227	pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
228	pm->smi_on_cpuhp =
229	!!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
230	pm->smi_on_cpu_unplug =
231	!!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
232	pm->tco_io_base = object_property_get_uint(obj, ACPI_PM_PROP_PM_IO_BASE,
233	NULL) + ICH9_PMIO_TCO_RLD;
234	}
235	pm->pcihp_io_base =
236	object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
237	pm->pcihp_io_len =
238	object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
239
240	/* Fill in optional s3/s4 related properties */
241	o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
242	if (o) {
243	pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
244	} else {
245	pm->s3_disabled = false;
246	}
247	qobject_unref(o);
248	o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
249	if (o) {
250	pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
251	} else {
252	pm->s4_disabled = false;
253	}
254	qobject_unref(o);
255	o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
256	if (o) {
257	pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
258	} else {
259	pm->s4_val = false;
260	}
261	qobject_unref(o);
262
263	pm->pcihp_bridge_en =
264	object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
265	NULL);
266	pm->pcihp_root_en =
267	object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
268	NULL);
269	}
270
271	static void acpi_get_misc_info(AcpiMiscInfo *info)
272	{
273	info->has_hpet = hpet_find();
274	#ifdef CONFIG_TPM
275	info->tpm_version = tpm_get_version(tpm_find());
276	#endif
277	}
278
279	/*
280	* Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
281	* On i386 arch we only have two pci hosts, so we can look only for them.
282	*/
283	Object *acpi_get_i386_pci_host(void)
284	{
285	PCIHostState *host;
286
287	host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
288	if (!host) {
289	host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
290	}
291
292	return OBJECT(host);
293	}
294
295	static void acpi_get_pci_holes(Range hole, Range hole64)
296	{
297	Object *pci_host;
298
299	pci_host = acpi_get_i386_pci_host();
300
301	if (!pci_host) {
302	return;
303	}
304
305	range_set_bounds1(hole,
306	object_property_get_uint(pci_host,
307	PCI_HOST_PROP_PCI_HOLE_START,
308	NULL),
309	object_property_get_uint(pci_host,
310	PCI_HOST_PROP_PCI_HOLE_END,
311	NULL));
312	range_set_bounds1(hole64,
313	object_property_get_uint(pci_host,
314	PCI_HOST_PROP_PCI_HOLE64_START,
315	NULL),
316	object_property_get_uint(pci_host,
317	PCI_HOST_PROP_PCI_HOLE64_END,
318	NULL));
319	}
320
321	static void acpi_align_size(GArray *blob, unsigned align)
322	{
323	/* Align size to multiple of given size. This reduces the chance
324	* we need to change size in the future (breaking cross version migration).
325	*/
326	g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
327	}
328
329	/*
330	* ACPI spec 1.0b,
331	* 5.2.6 Firmware ACPI Control Structure
332	*/
333	static void
334	build_facs(GArray *table_data)
335	{
336	const char *sig = "FACS";
337	const uint8_t reserved[40] = {};
338
339	g_array_append_vals(table_data, sig, 4); /* Signature */
340	build_append_int_noprefix(table_data, 64, 4); /* Length */
341	build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
342	build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
343	build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
344	build_append_int_noprefix(table_data, 0, 4); /* Flags */
345	g_array_append_vals(table_data, reserved, 40); /* Reserved */
346	}
347
348	/*
349	* build_prt - Define interrupt routing rules
350	*
351	* Returns an array of 128 routes, one for each device,
352	* based on device location.
353	* The main goal is to equally distribute the interrupts
354	* over the 4 existing ACPI links (works only for i440fx).
355	* The hash function is: (slot + pin) & 3 -> "LNK[D\|A\|B\|C]".
356	*
357	*/
358	static Aml *build_prt(bool is_pci0_prt)
359	{
360	const int nroutes = 128;
361	Aml rt_pkg, method;
362	int pin;
363
364	method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
365	assert(nroutes < 256);
366	rt_pkg = aml_package(nroutes);
367
368	for (pin = 0; pin < nroutes; pin++) {
369	Aml *pkg = aml_package(4);
370	int slot = pin >> 2;
371
372	aml_append(pkg, aml_int((slot << 16) \| 0xFFFF));
373	aml_append(pkg, aml_int(pin & 3));
374	/* device 1 is the power-management device, needs SCI */
375	if (is_pci0_prt && pin == 4) {
376	aml_append(pkg, aml_name("%s", "LNKS"));
377	} else {
378	static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"};
379	int hash = (slot + pin) & 3;
380	aml_append(pkg, aml_name("%s", link_name[hash]));
381	}
382	aml_append(pkg, aml_int(0));
383	aml_append(rt_pkg, pkg);
384	}
385
386	aml_append(method, aml_return(rt_pkg));
387
388	return method;
389	}
390
391	static void build_hpet_aml(Aml *table)
392	{
393	Aml *crs;
394	Aml *field;
395	Aml *method;
396	Aml *if_ctx;
397	Aml *scope = aml_scope("_SB");
398	Aml *dev = aml_device("HPET");
399	Aml *zero = aml_int(0);
400	Aml *id = aml_local(0);
401	Aml *period = aml_local(1);
402
403	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
404	aml_append(dev, aml_name_decl("_UID", zero));
405
406	aml_append(dev,
407	aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
408	HPET_LEN));
409	field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
410	aml_append(field, aml_named_field("VEND", 32));
411	aml_append(field, aml_named_field("PRD", 32));
412	aml_append(dev, field);
413
414	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
415	aml_append(method, aml_store(aml_name("VEND"), id));
416	aml_append(method, aml_store(aml_name("PRD"), period));
417	aml_append(method, aml_shiftright(id, aml_int(16), id));
418	if_ctx = aml_if(aml_lor(aml_equal(id, zero),
419	aml_equal(id, aml_int(0xffff))));
420	{
421	aml_append(if_ctx, aml_return(zero));
422	}
423	aml_append(method, if_ctx);
424
425	if_ctx = aml_if(aml_lor(aml_equal(period, zero),
426	aml_lgreater(period, aml_int(100000000))));
427	{
428	aml_append(if_ctx, aml_return(zero));
429	}
430	aml_append(method, if_ctx);
431
432	aml_append(method, aml_return(aml_int(0x0F)));
433	aml_append(dev, method);
434
435	crs = aml_resource_template();
436	aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
437	aml_append(dev, aml_name_decl("_CRS", crs));
438
439	aml_append(scope, dev);
440	aml_append(table, scope);
441	}
442
443	static Aml build_vmbus_device_aml(VMBusBridge vmbus_bridge)
444	{
445	Aml *dev;
446	Aml *method;
447	Aml *crs;
448
449	dev = aml_device("VMBS");
450	aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
451	aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
452	aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
453	aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
454
455	method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
456	aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
457	aml_name("STA")));
458	aml_append(dev, method);
459
460	method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
461	aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
462	aml_name("STA")));
463	aml_append(dev, method);
464
465	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
466	aml_append(method, aml_return(aml_name("STA")));
467	aml_append(dev, method);
468
469	aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
470
471	crs = aml_resource_template();
472	aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
473	aml_append(dev, aml_name_decl("_CRS", crs));
474
475	return dev;
476	}
477
478	static void build_dbg_aml(Aml *table)
479	{
480	Aml *field;
481	Aml *method;
482	Aml *while_ctx;
483	Aml *scope = aml_scope("\\");
484	Aml *buf = aml_local(0);
485	Aml *len = aml_local(1);
486	Aml *idx = aml_local(2);
487
488	aml_append(scope,
489	aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
490	field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
491	aml_append(field, aml_named_field("DBGB", 8));
492	aml_append(scope, field);
493
494	method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
495
496	aml_append(method, aml_to_hexstring(aml_arg(0), buf));
497	aml_append(method, aml_to_buffer(buf, buf));
498	aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
499	aml_append(method, aml_store(aml_int(0), idx));
500
501	while_ctx = aml_while(aml_lless(idx, len));
502	aml_append(while_ctx,
503	aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
504	aml_append(while_ctx, aml_increment(idx));
505	aml_append(method, while_ctx);
506
507	aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
508	aml_append(scope, method);
509
510	aml_append(table, scope);
511	}
512
513	static Aml build_link_dev(const char name, uint8_t uid, Aml *reg)
514	{
515	Aml *dev;
516	Aml *crs;
517	Aml *method;
518	uint32_t irqs[] = {5, 10, 11};
519
520	dev = aml_device("%s", name);
521	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
522	aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
523
524	crs = aml_resource_template();
525	aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
526	AML_SHARED, irqs, ARRAY_SIZE(irqs)));
527	aml_append(dev, aml_name_decl("_PRS", crs));
528
529	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
530	aml_append(method, aml_return(aml_call1("IQST", reg)));
531	aml_append(dev, method);
532
533	method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
534	aml_append(method, aml_or(reg, aml_int(0x80), reg));
535	aml_append(dev, method);
536
537	method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
538	aml_append(method, aml_return(aml_call1("IQCR", reg)));
539	aml_append(dev, method);
540
541	method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
542	aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
543	aml_append(method, aml_store(aml_name("PRRI"), reg));
544	aml_append(dev, method);
545
546	return dev;
547	}
548
549	static Aml build_gsi_link_dev(const char name, uint8_t uid, uint8_t gsi)
550	{
551	Aml *dev;
552	Aml *crs;
553	Aml *method;
554	uint32_t irqs;
555
556	dev = aml_device("%s", name);
557	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
558	aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
559
560	crs = aml_resource_template();
561	irqs = gsi;
562	aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
563	AML_SHARED, &irqs, 1));
564	aml_append(dev, aml_name_decl("_PRS", crs));
565
566	aml_append(dev, aml_name_decl("_CRS", crs));
567
568	/*
569	* _DIS can be no-op because the interrupt cannot be disabled.
570	*/
571	method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
572	aml_append(dev, method);
573
574	method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
575	aml_append(dev, method);
576
577	return dev;
578	}
579
580	/* _CRS method - get current settings */
581	static Aml *build_iqcr_method(bool is_piix4)
582	{
583	Aml *if_ctx;
584	uint32_t irqs;
585	Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
586	Aml *crs = aml_resource_template();
587
588	irqs = 0;
589	aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
590	AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
591	aml_append(method, aml_name_decl("PRR0", crs));
592
593	aml_append(method,
594	aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
595
596	if (is_piix4) {
597	if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
598	aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
599	aml_append(method, if_ctx);
600	} else {
601	aml_append(method,
602	aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
603	aml_name("PRRI")));
604	}
605
606	aml_append(method, aml_return(aml_name("PRR0")));
607	return method;
608	}
609
610	/* _STA method - get status */
611	static Aml *build_irq_status_method(void)
612	{
613	Aml *if_ctx;
614	Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
615
616	if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
617	aml_append(if_ctx, aml_return(aml_int(0x09)));
618	aml_append(method, if_ctx);
619	aml_append(method, aml_return(aml_int(0x0B)));
620	return method;
621	}
622
623	static void build_piix4_pci0_int(Aml *table)
624	{
625	Aml *dev;
626	Aml *crs;
627	Aml *method;
628	uint32_t irqs;
629	Aml *sb_scope = aml_scope("_SB");
630	Aml *pci0_scope = aml_scope("PCI0");
631
632	aml_append(pci0_scope, build_prt(true));
633	aml_append(sb_scope, pci0_scope);
634
635	aml_append(sb_scope, build_irq_status_method());
636	aml_append(sb_scope, build_iqcr_method(true));
637
638	aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
639	aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
640	aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
641	aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
642
643	dev = aml_device("LNKS");
644	{
645	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
646	aml_append(dev, aml_name_decl("_UID", aml_int(4)));
647
648	crs = aml_resource_template();
649	irqs = 9;
650	aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
651	AML_ACTIVE_HIGH, AML_SHARED,
652	&irqs, 1));
653	aml_append(dev, aml_name_decl("_PRS", crs));
654
655	/* The SCI cannot be disabled and is always attached to GSI 9,
656	* so these are no-ops. We only need this link to override the
657	* polarity to active high and match the content of the MADT.
658	*/
659	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
660	aml_append(method, aml_return(aml_int(0x0b)));
661	aml_append(dev, method);
662
663	method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
664	aml_append(dev, method);
665
666	method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
667	aml_append(method, aml_return(aml_name("_PRS")));
668	aml_append(dev, method);
669
670	method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
671	aml_append(dev, method);
672	}
673	aml_append(sb_scope, dev);
674
675	aml_append(table, sb_scope);
676	}
677
678	static void append_q35_prt_entry(Aml ctx, uint32_t nr, const char name)
679	{
680	int i;
681	int head;
682	Aml *pkg;
683	char base = name[3] < 'E' ? 'A' : 'E';
684	char *s = g_strdup(name);
685	Aml *a_nr = aml_int((nr << 16) \| 0xffff);
686
687	assert(strlen(s) == 4);
688
689	head = name[3] - base;
690	for (i = 0; i < 4; i++) {
691	if (head + i > 3) {
692	head = i * -1;
693	}
694	s[3] = base + head + i;
695	pkg = aml_package(4);
696	aml_append(pkg, a_nr);
697	aml_append(pkg, aml_int(i));
698	aml_append(pkg, aml_name("%s", s));
699	aml_append(pkg, aml_int(0));
700	aml_append(ctx, pkg);
701	}
702	g_free(s);
703	}
704
705	static Aml build_q35_routing_table(const char str)
706	{
707	int i;
708	Aml *pkg;
709	char *name = g_strdup_printf("%s ", str);
710
711	pkg = aml_package(128);
712	for (i = 0; i < 0x18; i++) {
713	name[3] = 'E' + (i & 0x3);
714	append_q35_prt_entry(pkg, i, name);
715	}
716
717	name[3] = 'E';
718	append_q35_prt_entry(pkg, 0x18, name);
719
720	/* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
721	for (i = 0x0019; i < 0x1e; i++) {
722	name[3] = 'A';
723	append_q35_prt_entry(pkg, i, name);
724	}
725
726	/* PCIe->PCI bridge. use PIRQ[E-H] */
727	name[3] = 'E';
728	append_q35_prt_entry(pkg, 0x1e, name);
729	name[3] = 'A';
730	append_q35_prt_entry(pkg, 0x1f, name);
731
732	g_free(name);
733	return pkg;
734	}
735
736	static void build_q35_pci0_int(Aml *table)
737	{
738	Aml *method;
739	Aml *sb_scope = aml_scope("_SB");
740	Aml *pci0_scope = aml_scope("PCI0");
741
742	/* Zero => PIC mode, One => APIC Mode */
743	aml_append(table, aml_name_decl("PICF", aml_int(0)));
744	method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
745	{
746	aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
747	}
748	aml_append(table, method);
749
750	aml_append(pci0_scope,
751	aml_name_decl("PRTP", build_q35_routing_table("LNK")));
752	aml_append(pci0_scope,
753	aml_name_decl("PRTA", build_q35_routing_table("GSI")));
754
755	method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
756	{
757	Aml *if_ctx;
758	Aml *else_ctx;
759
760	/* PCI IRQ routing table, example from ACPI 2.0a specification,
761	section 6.2.8.1 */
762	/* Note: we provide the same info as the PCI routing
763	table of the Bochs BIOS */
764	if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
765	aml_append(if_ctx, aml_return(aml_name("PRTP")));
766	aml_append(method, if_ctx);
767	else_ctx = aml_else();
768	aml_append(else_ctx, aml_return(aml_name("PRTA")));
769	aml_append(method, else_ctx);
770	}
771	aml_append(pci0_scope, method);
772	aml_append(sb_scope, pci0_scope);
773
774	aml_append(sb_scope, build_irq_status_method());
775	aml_append(sb_scope, build_iqcr_method(false));
776
777	aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
778	aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
779	aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
780	aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
781	aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
782	aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
783	aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
784	aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
785
786	aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
787	aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
788	aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
789	aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
790	aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
791	aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
792	aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
793	aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
794
795	aml_append(table, sb_scope);
796	}
797
798	static Aml build_q35_dram_controller(const AcpiMcfgInfo mcfg)
799	{
800	Aml *dev;
801	Aml *resource_template;
802
803	/* DRAM controller */
804	dev = aml_device("DRAC");
805	aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
806
807	resource_template = aml_resource_template();
808	if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
809	aml_append(resource_template,
810	aml_qword_memory(AML_POS_DECODE,
811	AML_MIN_FIXED,
812	AML_MAX_FIXED,
813	AML_NON_CACHEABLE,
814	AML_READ_WRITE,
815	0x0000000000000000,
816	mcfg->base,
817	mcfg->base + mcfg->size - 1,
818	0x0000000000000000,
819	mcfg->size));
820	} else {
821	aml_append(resource_template,
822	aml_dword_memory(AML_POS_DECODE,
823	AML_MIN_FIXED,
824	AML_MAX_FIXED,
825	AML_NON_CACHEABLE,
826	AML_READ_WRITE,
827	0x0000000000000000,
828	mcfg->base,
829	mcfg->base + mcfg->size - 1,
830	0x0000000000000000,
831	mcfg->size));
832	}
833	aml_append(dev, aml_name_decl("_CRS", resource_template));
834
835	return dev;
836	}
837
838	static void build_acpi0017(Aml *table)
839	{
840	Aml dev, scope, *method;
841
842	scope = aml_scope("_SB");
843	dev = aml_device("CXLM");
844	aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
845
846	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
847	aml_append(method, aml_return(aml_int(0x0B)));
848	aml_append(dev, method);
849	build_cxl_dsm_method(dev);
850
851	aml_append(scope, dev);
852	aml_append(table, scope);
853	}
854
855	static void
856	build_dsdt(GArray table_data, BIOSLinker linker,
857	AcpiPmInfo pm, AcpiMiscInfo misc,
858	Range pci_hole, Range pci_hole64, MachineState *machine)
859	{
860	Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
861	NULL);
862	Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
863	CrsRangeEntry *entry;
864	Aml dsdt, sb_scope, scope, dev, method, field, pkg, crs;
865	CrsRangeSet crs_range_set;
866	PCMachineState *pcms = PC_MACHINE(machine);
867	PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
868	X86MachineState *x86ms = X86_MACHINE(machine);
869	AcpiMcfgInfo mcfg;
870	bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
871	uint32_t nr_mem = machine->ram_slots;
872	int root_bus_limit = 0xFF;
873	PCIBus *bus = NULL;
874	#ifdef CONFIG_TPM
875	TPMIf *tpm = tpm_find();
876	#endif
877	bool cxl_present = false;
878	int i;
879	VMBusBridge *vmbus_bridge = vmbus_bridge_find();
880	AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
881	.oem_table_id = x86ms->oem_table_id };
882
883	assert(!!i440fx != !!q35);
884
885	acpi_table_begin(&table, table_data);
886	dsdt = init_aml_allocator();
887
888	build_dbg_aml(dsdt);
889	if (i440fx) {
890	sb_scope = aml_scope("_SB");
891	dev = aml_device("PCI0");
892	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
893	aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
894	aml_append(dev, build_pci_bridge_edsm());
895	aml_append(sb_scope, dev);
896	aml_append(dsdt, sb_scope);
897
898	if (pm->pcihp_bridge_en \|\| pm->pcihp_root_en) {
899	build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
900	}
901	build_piix4_pci0_int(dsdt);
902	} else if (q35) {
903	sb_scope = aml_scope("_SB");
904	dev = aml_device("PCI0");
905	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
906	aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
907	aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
908	aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en));
909	aml_append(dev, build_pci_bridge_edsm());
910	aml_append(sb_scope, dev);
911	if (mcfg_valid) {
912	aml_append(sb_scope, build_q35_dram_controller(&mcfg));
913	}
914
915	if (pm->smi_on_cpuhp) {
916	/* reserve SMI block resources, IO ports 0xB2, 0xB3 */
917	dev = aml_device("PCI0.SMI0");
918	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
919	aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
920	crs = aml_resource_template();
921	aml_append(crs,
922	aml_io(
923	AML_DECODE16,
924	pm->fadt.smi_cmd,
925	pm->fadt.smi_cmd,
926	1,
927	2)
928	);
929	aml_append(dev, aml_name_decl("_CRS", crs));
930	aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
931	aml_int(pm->fadt.smi_cmd), 2));
932	field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
933	AML_WRITE_AS_ZEROS);
934	aml_append(field, aml_named_field("SMIC", 8));
935	aml_append(field, aml_reserved_field(8));
936	aml_append(dev, field);
937	aml_append(sb_scope, dev);
938	}
939
940	aml_append(dsdt, sb_scope);
941
942	if (pm->pcihp_bridge_en) {
943	build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
944	}
945	build_q35_pci0_int(dsdt);
946	}
947
948	if (misc->has_hpet) {
949	build_hpet_aml(dsdt);
950	}
951
952	if (vmbus_bridge) {
953	sb_scope = aml_scope("_SB");
954	aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
955	aml_append(dsdt, sb_scope);
956	}
957
958	scope = aml_scope("_GPE");
959	{
960	aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
961	if (machine->nvdimms_state->is_enabled) {
962	method = aml_method("_E04", 0, AML_NOTSERIALIZED);
963	aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
964	aml_int(0x80)));
965	aml_append(scope, method);
966	}
967	}
968	aml_append(dsdt, scope);
969
970	{
971	CPUHotplugFeatures opts = {
972	.acpi_1_compatible = true,
973	.smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
974	.fw_unplugs_cpu = pm->smi_on_cpu_unplug,
975	};
976	build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
977	pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
978	AML_SYSTEM_IO);
979	}
980
981	if (pcms->memhp_io_base && nr_mem) {
982	build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
983	"\\_GPE._E03", AML_SYSTEM_IO,
984	pcms->memhp_io_base);
985	}
986
987	crs_range_set_init(&crs_range_set);
988	bus = PC_MACHINE(machine)->pcibus;
989	if (bus) {
990	QLIST_FOREACH(bus, &bus->child, sibling) {
991	uint8_t bus_num = pci_bus_num(bus);
992	uint8_t numa_node = pci_bus_numa_node(bus);
993	uint32_t uid;
994
995	/* look only for expander root buses */
996	if (!pci_bus_is_root(bus)) {
997	continue;
998	}
999
1000	if (bus_num < root_bus_limit) {
1001	root_bus_limit = bus_num - 1;
1002	}
1003
1004	uid = object_property_get_uint(OBJECT(bus), "acpi_uid",
1005	&error_fatal);
1006	scope = aml_scope("\\_SB");
1007
1008	if (pci_bus_is_cxl(bus)) {
1009	dev = aml_device("CL%.02X", bus_num);
1010	} else {
1011	dev = aml_device("PC%.02X", bus_num);
1012	}
1013	aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1014	aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1015	if (pci_bus_is_cxl(bus)) {
1016	struct Aml *aml_pkg = aml_package(2);
1017
1018	aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1019	aml_append(aml_pkg, aml_eisaid("PNP0A08"));
1020	aml_append(aml_pkg, aml_eisaid("PNP0A03"));
1021	aml_append(dev, aml_name_decl("_CID", aml_pkg));
1022	build_cxl_osc_method(dev);
1023	} else if (pci_bus_is_express(bus)) {
1024	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1025	aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1026
1027	/* Expander bridges do not have ACPI PCI Hot-plug enabled */
1028	aml_append(dev, build_pci_host_bridge_osc_method(true));
1029	} else {
1030	aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1031	}
1032
1033	if (numa_node != NUMA_NODE_UNASSIGNED) {
1034	aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1035	}
1036
1037	aml_append(dev, build_prt(false));
1038	crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1039	0, 0, 0, 0);
1040	aml_append(dev, aml_name_decl("_CRS", crs));
1041	aml_append(scope, dev);
1042	aml_append(dsdt, scope);
1043
1044	/* Handle the ranges for the PXB expanders */
1045	if (pci_bus_is_cxl(bus)) {
1046	MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1047	uint64_t base = mr->addr;
1048
1049	cxl_present = true;
1050	crs_range_insert(crs_range_set.mem_ranges, base,
1051	base + memory_region_size(mr) - 1);
1052	}
1053	}
1054	}
1055
1056	if (cxl_present) {
1057	build_acpi0017(dsdt);
1058	}
1059
1060	/*
1061	* At this point crs_range_set has all the ranges used by pci
1062	* busses other than PCI0. These ranges will be excluded from
1063	* the PCI0._CRS. Add mmconfig to the set so it will be excluded
1064	* too.
1065	*/
1066	if (mcfg_valid) {
1067	crs_range_insert(crs_range_set.mem_ranges,
1068	mcfg.base, mcfg.base + mcfg.size - 1);
1069	}
1070
1071	scope = aml_scope("\\_SB.PCI0");
1072	/* build PCI0._CRS */
1073	crs = aml_resource_template();
1074	aml_append(crs,
1075	aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1076	0x0000, 0x0, root_bus_limit,
1077	0x0000, root_bus_limit + 1));
1078	aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1079
1080	aml_append(crs,
1081	aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1082	AML_POS_DECODE, AML_ENTIRE_RANGE,
1083	0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1084
1085	crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1086	for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1087	entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1088	aml_append(crs,
1089	aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1090	AML_POS_DECODE, AML_ENTIRE_RANGE,
1091	0x0000, entry->base, entry->limit,
1092	0x0000, entry->limit - entry->base + 1));
1093	}
1094
1095	aml_append(crs,
1096	aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1097	AML_CACHEABLE, AML_READ_WRITE,
1098	0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1099
1100	crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1101	range_lob(pci_hole),
1102	range_upb(pci_hole));
1103	for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1104	entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1105	aml_append(crs,
1106	aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1107	AML_NON_CACHEABLE, AML_READ_WRITE,
1108	0, entry->base, entry->limit,
1109	0, entry->limit - entry->base + 1));
1110	}
1111
1112	if (!range_is_empty(pci_hole64)) {
1113	crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1114	range_lob(pci_hole64),
1115	range_upb(pci_hole64));
1116	for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1117	entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1118	aml_append(crs,
1119	aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1120	AML_MAX_FIXED,
1121	AML_CACHEABLE, AML_READ_WRITE,
1122	0, entry->base, entry->limit,
1123	0, entry->limit - entry->base + 1));
1124	}
1125	}
1126
1127	#ifdef CONFIG_TPM
1128	if (TPM_IS_TIS_ISA(tpm_find())) {
1129	aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1130	TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1131	}
1132	#endif
1133	aml_append(scope, aml_name_decl("_CRS", crs));
1134
1135	/* reserve GPE0 block resources */
1136	dev = aml_device("GPE0");
1137	aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1138	aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1139	/* device present, functioning, decoding, not shown in UI */
1140	aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1141	crs = aml_resource_template();
1142	aml_append(crs,
1143	aml_io(
1144	AML_DECODE16,
1145	pm->fadt.gpe0_blk.address,
1146	pm->fadt.gpe0_blk.address,
1147	1,
1148	pm->fadt.gpe0_blk.bit_width / 8)
1149	);
1150	aml_append(dev, aml_name_decl("_CRS", crs));
1151	aml_append(scope, dev);
1152
1153	crs_range_set_free(&crs_range_set);
1154
1155	/* reserve PCIHP resources */
1156	if (pm->pcihp_io_len && (pm->pcihp_bridge_en \|\| pm->pcihp_root_en)) {
1157	build_append_pcihp_resources(scope,
1158	pm->pcihp_io_base, pm->pcihp_io_len);
1159	}
1160	aml_append(dsdt, scope);
1161
1162	/* create S3_ / S4_ / S5_ packages if necessary */
1163	scope = aml_scope("\\");
1164	if (!pm->s3_disabled) {
1165	pkg = aml_package(4);
1166	aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1167	aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1168	aml_append(pkg, aml_int(0)); /* reserved */
1169	aml_append(pkg, aml_int(0)); /* reserved */
1170	aml_append(scope, aml_name_decl("_S3", pkg));
1171	}
1172
1173	if (!pm->s4_disabled) {
1174	pkg = aml_package(4);
1175	aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1176	/* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1177	aml_append(pkg, aml_int(pm->s4_val));
1178	aml_append(pkg, aml_int(0)); /* reserved */
1179	aml_append(pkg, aml_int(0)); /* reserved */
1180	aml_append(scope, aml_name_decl("_S4", pkg));
1181	}
1182
1183	pkg = aml_package(4);
1184	aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1185	aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1186	aml_append(pkg, aml_int(0)); /* reserved */
1187	aml_append(pkg, aml_int(0)); /* reserved */
1188	aml_append(scope, aml_name_decl("_S5", pkg));
1189	aml_append(dsdt, scope);
1190
1191	/* create fw_cfg node, unconditionally */
1192	{
1193	scope = aml_scope("\\_SB.PCI0");
1194	fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1195	aml_append(dsdt, scope);
1196	}
1197
1198	sb_scope = aml_scope("\\_SB");
1199	{
1200	Object *pci_host = acpi_get_i386_pci_host();
1201	uint32_t bsel;
1202
1203	if (pci_host) {
1204	PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus;
1205	Aml *ascope = aml_scope("PCI0");
1206	/* Scan all PCI buses. Generate tables to support hotplug. */
1207	build_append_pci_bus_devices(ascope, pbus);
1208	bsel = object_property_get_uint(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL,
1209	&error_abort);
1210	if (bsel != UINT32_MAX) {
1211	build_append_pcihp_slots(ascope, pbus);
1212	}
1213	aml_append(sb_scope, ascope);
1214	}
1215	}
1216
1217	#ifdef CONFIG_TPM
1218	if (TPM_IS_CRB(tpm)) {
1219	dev = aml_device("TPM");
1220	aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1221	aml_append(dev, aml_name_decl("_STR",
1222	aml_string("TPM 2.0 Device")));
1223	crs = aml_resource_template();
1224	aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1225	TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1226	aml_append(dev, aml_name_decl("_CRS", crs));
1227
1228	aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1229	aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1230
1231	tpm_build_ppi_acpi(tpm, dev, TPM_PPI_ADDR_BASE);
1232
1233	aml_append(sb_scope, dev);
1234	}
1235	#endif
1236
1237	if (pcms->sgx_epc.size != 0) {
1238	uint64_t epc_base = pcms->sgx_epc.base;
1239	uint64_t epc_size = pcms->sgx_epc.size;
1240
1241	dev = aml_device("EPC");
1242	aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1243	aml_append(dev, aml_name_decl("_STR",
1244	aml_unicode("Enclave Page Cache 1.0")));
1245	crs = aml_resource_template();
1246	aml_append(crs,
1247	aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1248	AML_MAX_FIXED, AML_NON_CACHEABLE,
1249	AML_READ_WRITE, 0, epc_base,
1250	epc_base + epc_size - 1, 0, epc_size));
1251	aml_append(dev, aml_name_decl("_CRS", crs));
1252
1253	method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1254	aml_append(method, aml_return(aml_int(0x0f)));
1255	aml_append(dev, method);
1256
1257	aml_append(sb_scope, dev);
1258	}
1259	aml_append(dsdt, sb_scope);
1260
1261	if (pm->pcihp_bridge_en \|\| pm->pcihp_root_en) {
1262	bool has_pcnt;
1263
1264	Object *pci_host = acpi_get_i386_pci_host();
1265	PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus;
1266
1267	scope = aml_scope("\\_SB.PCI0");
1268	has_pcnt = build_append_notification_callback(scope, b);
1269	if (has_pcnt) {
1270	aml_append(dsdt, scope);
1271	}
1272
1273	scope = aml_scope("_GPE");
1274	{
1275	method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1276	if (has_pcnt) {
1277	aml_append(method,
1278	aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1279	aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1280	aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1281	}
1282	aml_append(scope, method);
1283	}
1284	aml_append(dsdt, scope);
1285	}
1286
1287	/* copy AML table into ACPI tables blob and patch header there */
1288	g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1289	acpi_table_end(linker, &table);
1290	free_aml_allocator();
1291	}
1292
1293	/*
1294	* IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1295	* 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1296	*/
1297	static void
1298	build_hpet(GArray table_data, BIOSLinker linker, const char *oem_id,
1299	const char *oem_table_id)
1300	{
1301	AcpiTable table = { .sig = "HPET", .rev = 1,
1302	.oem_id = oem_id, .oem_table_id = oem_table_id };
1303
1304	acpi_table_begin(&table, table_data);
1305	/* Note timer_block_id value must be kept in sync with value advertised by
1306	* emulated hpet
1307	*/
1308	/* Event Timer Block ID */
1309	build_append_int_noprefix(table_data, 0x8086a201, 4);
1310	/* BASE_ADDRESS */
1311	build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1312	/* HPET Number */
1313	build_append_int_noprefix(table_data, 0, 1);
1314	/* Main Counter Minimum Clock_tick in Periodic Mode */
1315	build_append_int_noprefix(table_data, 0, 2);
1316	/* Page Protection And OEM Attribute */
1317	build_append_int_noprefix(table_data, 0, 1);
1318	acpi_table_end(linker, &table);
1319	}
1320
1321	#ifdef CONFIG_TPM
1322	/*
1323	* TCPA Description Table
1324	*
1325	* Following Level 00, Rev 00.37 of specs:
1326	* http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1327	* 7.1.2 ACPI Table Layout
1328	*/
1329	static void
1330	build_tpm_tcpa(GArray table_data, BIOSLinker linker, GArray *tcpalog,
1331	const char oem_id, const char oem_table_id)
1332	{
1333	unsigned log_addr_offset;
1334	AcpiTable table = { .sig = "TCPA", .rev = 2,
1335	.oem_id = oem_id, .oem_table_id = oem_table_id };
1336
1337	acpi_table_begin(&table, table_data);
1338	/* Platform Class */
1339	build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1340	/* Log Area Minimum Length (LAML) */
1341	build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1342	/* Log Area Start Address (LASA) */
1343	log_addr_offset = table_data->len;
1344	build_append_int_noprefix(table_data, 0, 8);
1345
1346	/* allocate/reserve space for TPM log area */
1347	acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1348	bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1349	false /* high memory */);
1350	/* log area start address to be filled by Guest linker */
1351	bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1352	log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1353
1354	acpi_table_end(linker, &table);
1355	}
1356	#endif
1357
1358	typedef struct {
1359	uint64_t addr;
1360	uint64_t size;
1361	uint32_t node;
1362	} SpMemRange;
1363
1364	static int sp_mem_collect_ranges_cb(Object obj, void opaque)
1365	{
1366	GArray *ranges = opaque;
1367	SpMemDevice *spm;
1368	MemoryDeviceClass *mdc;
1369	SpMemRange r;
1370
1371	if (!object_dynamic_cast(obj, TYPE_SP_MEM)) {
1372	return 0;
1373	}
1374	spm = SP_MEM(obj);
1375	mdc = MEMORY_DEVICE_GET_CLASS(MEMORY_DEVICE(spm));
1376	r.addr = mdc->get_addr(MEMORY_DEVICE(spm));
1377	r.size = memory_region_size(
1378	host_memory_backend_get_memory(spm->hostmem));
1379	r.node = spm->node;
1380	g_array_append_val(ranges, r);
1381	return 0;
1382	}
1383
1384	static gint sp_mem_range_compare(gconstpointer a, gconstpointer b)
1385	{
1386	const SpMemRange *range_a = a;
1387	const SpMemRange *range_b = b;
1388
1389	if (range_a->addr < range_b->addr) {
1390	return -1;
1391	}
1392	if (range_a->addr > range_b->addr) {
1393	return 1;
1394	}
1395	return 0;
1396	}
1397
1398	/*
1399	* Emit SRAT memory-affinity entries covering the device_memory region.
1400	*
1401	* For each plugged TYPE_SP_MEM device, emit an ENABLED entry at the
1402	* device's own proximity_domain. All remaining sub-ranges (gaps
1403	* between sp-mem devices, leading and trailing padding, and ranges
1404	* occupied by other memory devices) are covered by HOTPLUGGABLE \|
1405	* ENABLED placeholder entries at PXM = nb_numa_nodes - 1.
1406	*/
1407	static void build_srat_device_memory(GArray table_data, MachineState ms)
1408	{
1409	g_autoptr(GArray) ranges = g_array_new(FALSE, TRUE, sizeof(SpMemRange));
1410	uint32_t hotplug_pxm = ms->numa_state->num_nodes - 1;
1411	uint64_t region_start, region_end;
1412	guint i;
1413
1414	region_start = ms->device_memory->base;
1415	region_end = region_start + memory_region_size(&ms->device_memory->mr);
1416
1417	object_child_foreach_recursive(qdev_get_machine(),
1418	sp_mem_collect_ranges_cb, ranges);
1419	g_array_sort(ranges, sp_mem_range_compare);
1420
1421	for (i = 0; i < ranges->len; i++) {
1422	SpMemRange *r = &g_array_index(ranges, SpMemRange, i);
1423
1424	if (region_start < r->addr) {
1425	build_srat_memory(table_data, region_start, r->addr - region_start,
1426	hotplug_pxm,
1427	MEM_AFFINITY_HOTPLUGGABLE \|
1428	MEM_AFFINITY_ENABLED);
1429	}
1430	build_srat_memory(table_data, r->addr, r->size, r->node,
1431	MEM_AFFINITY_ENABLED);
1432	region_start = r->addr + r->size;
1433	}
1434
1435	/*
1436	* Cover the rest of the device_memory window that no sp-mem device
1437	* occupies. Keeping it HOTPLUGGABLE preserves the umbrella entry's
1438	* role for future pc-dimm / virtio-mem hot-add into this window.
1439	*/
1440	if (region_start < region_end) {
1441	build_srat_memory(table_data, region_start, region_end - region_start,
1442	hotplug_pxm,
1443	MEM_AFFINITY_HOTPLUGGABLE \|
1444	MEM_AFFINITY_ENABLED);
1445	}
1446	}
1447
1448	#define HOLE_640K_START (640 * KiB)
1449	#define HOLE_640K_END (1 * MiB)
1450
1451	/*
1452	* ACPI spec, Revision 3.0
1453	* 5.2.15 System Resource Affinity Table (SRAT)
1454	*/
1455	static void
1456	build_srat(GArray table_data, BIOSLinker linker, MachineState *machine)
1457	{
1458	int i;
1459	int numa_mem_start, slots;
1460	uint64_t mem_len, mem_base, next_base;
1461	MachineClass *mc = MACHINE_GET_CLASS(machine);
1462	X86MachineState *x86ms = X86_MACHINE(machine);
1463	const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1464	int nb_numa_nodes = machine->numa_state->num_nodes;
1465	NodeInfo *numa_info = machine->numa_state->nodes;
1466	AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1467	.oem_table_id = x86ms->oem_table_id };
1468
1469	acpi_table_begin(&table, table_data);
1470	build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1471	build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1472
1473	for (i = 0; i < apic_ids->len; i++) {
1474	int node_id = apic_ids->cpus[i].props.node_id;
1475	uint32_t apic_id = apic_ids->cpus[i].arch_id;
1476
1477	if (apic_id < 255) {
1478	/* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1479	build_append_int_noprefix(table_data, 0, 1); /* Type */
1480	build_append_int_noprefix(table_data, 16, 1); /* Length */
1481	/* Proximity Domain [7:0] */
1482	build_append_int_noprefix(table_data, node_id, 1);
1483	build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1484	/* Flags, Table 5-36 */
1485	build_append_int_noprefix(table_data, 1, 4);
1486	build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1487	/* Proximity Domain [31:8] */
1488	build_append_int_noprefix(table_data, 0, 3);
1489	build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1490	} else {
1491	/*
1492	* ACPI spec, Revision 4.0
1493	* 5.2.16.3 Processor Local x2APIC Affinity Structure
1494	*/
1495	build_append_int_noprefix(table_data, 2, 1); /* Type */
1496	build_append_int_noprefix(table_data, 24, 1); /* Length */
1497	build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1498	/* Proximity Domain */
1499	build_append_int_noprefix(table_data, node_id, 4);
1500	build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1501	/* Flags, Table 5-39 */
1502	build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1503	build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1504	build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1505	}
1506	}
1507
1508	/* the memory map is a bit tricky, it contains at least one hole
1509	* from 640k-1M and possibly another one from 3.5G-4G.
1510	*/
1511	next_base = 0;
1512	numa_mem_start = table_data->len;
1513
1514	for (i = 1; i < nb_numa_nodes + 1; ++i) {
1515	mem_base = next_base;
1516	mem_len = numa_info[i - 1].node_mem;
1517	next_base = mem_base + mem_len;
1518
1519	/* Cut out the 640K hole */
1520	if (mem_base <= HOLE_640K_START &&
1521	next_base > HOLE_640K_START) {
1522	mem_len -= next_base - HOLE_640K_START;
1523	if (mem_len > 0) {
1524	build_srat_memory(table_data, mem_base, mem_len, i - 1,
1525	MEM_AFFINITY_ENABLED);
1526	}
1527
1528	/* Check for the rare case: 640K < RAM < 1M */
1529	if (next_base <= HOLE_640K_END) {
1530	next_base = HOLE_640K_END;
1531	continue;
1532	}
1533	mem_base = HOLE_640K_END;
1534	mem_len = next_base - HOLE_640K_END;
1535	}
1536
1537	/* Cut out the ACPI_PCI hole */
1538	if (mem_base <= x86ms->below_4g_mem_size &&
1539	next_base > x86ms->below_4g_mem_size) {
1540	mem_len -= next_base - x86ms->below_4g_mem_size;
1541	if (mem_len > 0) {
1542	build_srat_memory(table_data, mem_base, mem_len, i - 1,
1543	MEM_AFFINITY_ENABLED);
1544	}
1545	mem_base = x86ms->above_4g_mem_start;
1546	mem_len = next_base - x86ms->below_4g_mem_size;
1547	next_base = mem_base + mem_len;
1548	}
1549
1550	if (mem_len > 0) {
1551	build_srat_memory(table_data, mem_base, mem_len, i - 1,
1552	MEM_AFFINITY_ENABLED);
1553	}
1554	}
1555
1556	if (machine->nvdimms_state->is_enabled) {
1557	nvdimm_build_srat(table_data);
1558	}
1559
1560	sgx_epc_build_srat(table_data);
1561
1562	/*
1563	* TODO: this part is not in ACPI spec and current linux kernel boots fine
1564	* without these entries. But I recall there were issues the last time I
1565	* tried to remove it with some ancient guest OS, however I can't remember
1566	* what that was so keep this around for now
1567	*/
1568	slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
1569	for (; slots < nb_numa_nodes + 2; slots++) {
1570	build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1571	}
1572
1573	build_srat_generic_affinity_structures(table_data);
1574
1575	/*
1576	* Entry is required for Windows to enable memory hotplug in OS
1577	* and for Linux to enable SWIOTLB when booted with less than
1578	* 4G of RAM. Windows works better if the entry sets proximity
1579	* to the highest NUMA node in the machine.
1580	* Memory devices may override proximity set by this entry,
1581	* providing _PXM method if necessary.
1582	*/
1583	if (machine->device_memory) {
1584	build_srat_device_memory(table_data, machine);
1585	}
1586
1587	acpi_table_end(linker, &table);
1588	}
1589
1590	/*
1591	* Insert DMAR scope for PCI bridges and endpoint devices
1592	*/
1593	static void
1594	insert_scope(PCIBus bus, PCIDevice dev, void *opaque)
1595	{
1596	const size_t device_scope_size = 6 /* device scope structure */ +
1597	2 /* 1 path entry */;
1598	GArray *scope_blob = opaque;
1599
1600	if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1601	/* Dmar Scope Type: 0x02 for PCI Bridge */
1602	build_append_int_noprefix(scope_blob, 0x02, 1);
1603	} else {
1604	/* Dmar Scope Type: 0x01 for PCI Endpoint Device */
1605	build_append_int_noprefix(scope_blob, 0x01, 1);
1606	}
1607
1608	/* length */
1609	build_append_int_noprefix(scope_blob, device_scope_size, 1);
1610	/* reserved */
1611	build_append_int_noprefix(scope_blob, 0, 2);
1612	/* enumeration_id */
1613	build_append_int_noprefix(scope_blob, 0, 1);
1614	/* bus */
1615	build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
1616	/* device */
1617	build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
1618	/* function */
1619	build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
1620	}
1621
1622	/* For a given PCI host bridge, walk and insert DMAR scope */
1623	static int
1624	dmar_host_bridges(Object obj, void opaque)
1625	{
1626	GArray *scope_blob = opaque;
1627
1628	if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1629	PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1630
1631	if (bus && !pci_bus_bypass_iommu(bus)) {
1632	pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
1633	}
1634	}
1635
1636	return 0;
1637	}
1638
1639	/*
1640	* Intel ® Virtualization Technology for Directed I/O
1641	* Architecture Specification. Revision 3.3
1642	* 8.1 DMA Remapping Reporting Structure
1643	*/
1644	static void
1645	build_dmar_q35(GArray table_data, BIOSLinker linker, const char *oem_id,
1646	const char *oem_table_id)
1647	{
1648	uint8_t dmar_flags = 0;
1649	uint8_t rsvd10[10] = {};
1650	/* Root complex IOAPIC uses one path only */
1651	const size_t ioapic_scope_size = 6 /* device scope structure */ +
1652	2 /* 1 path entry */;
1653	X86IOMMUState *iommu = x86_iommu_get_default();
1654	IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1655	GArray *scope_blob = g_array_new(false, true, 1);
1656
1657	AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
1658	.oem_table_id = oem_table_id };
1659
1660	/*
1661	* A PCI bus walk, for each PCI host bridge.
1662	* Insert scope for each PCI bridge and endpoint device which
1663	* is attached to a bus with iommu enabled.
1664	*/
1665	object_child_foreach_recursive(object_get_root(),
1666	dmar_host_bridges, scope_blob);
1667
1668	assert(iommu);
1669	if (x86_iommu_ir_supported(iommu)) {
1670	dmar_flags \|= 0x1; /* Flags: 0x1: INT_REMAP */
1671	}
1672
1673	acpi_table_begin(&table, table_data);
1674	/* Host Address Width */
1675	build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
1676	build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
1677	g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
1678
1679	/* 8.3 DMAR Remapping Hardware Unit Definition structure */
1680	build_append_int_noprefix(table_data, 0, 2); /* Type */
1681	/* Length */
1682	build_append_int_noprefix(table_data,
1683	16 + ioapic_scope_size + scope_blob->len, 2);
1684	/* Flags */
1685	build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
1686	1);
1687	build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
1688	build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
1689	/* Register Base Address */
1690	build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
1691
1692	/* Scope definition for the root-complex IOAPIC. See VT-d spec
1693	* 8.3.1 (version Oct. 2014 or later). */
1694	build_append_int_noprefix(table_data, 0x03 /* IOAPIC /, 1); / Type */
1695	build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
1696	build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1697	/* Enumeration ID */
1698	build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
1699	/* Start Bus Number */
1700	build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
1701	/* Path, {Device, Function} pair */
1702	build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
1703	build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
1704
1705	/* Add scope found above */
1706	g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
1707	g_array_free(scope_blob, true);
1708
1709	if (iommu->dt_supported) {
1710	/* 8.5 Root Port ATS Capability Reporting Structure */
1711	build_append_int_noprefix(table_data, 2, 2); /* Type */
1712	build_append_int_noprefix(table_data, 8, 2); /* Length */
1713	build_append_int_noprefix(table_data, 1 /* ALL_PORTS /, 1); / Flags */
1714	build_append_int_noprefix(table_data, 0, 1); /* Reserved */
1715	build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
1716	}
1717
1718	acpi_table_end(linker, &table);
1719	}
1720
1721	/*
1722	* Windows ACPI Emulated Devices Table
1723	* (Version 1.0 - April 6, 2009)
1724	* Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1725	*
1726	* Helpful to speedup Windows guests and ignored by others.
1727	*/
1728	static void
1729	build_waet(GArray table_data, BIOSLinker linker, const char *oem_id,
1730	const char *oem_table_id)
1731	{
1732	AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
1733	.oem_table_id = oem_table_id };
1734
1735	acpi_table_begin(&table, table_data);
1736	/*
1737	* Set "ACPI PM timer good" flag.
1738	*
1739	* Tells Windows guests that our ACPI PM timer is reliable in the
1740	* sense that guest can read it only once to obtain a reliable value.
1741	* Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1742	*/
1743	build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
1744	acpi_table_end(linker, &table);
1745	}
1746
1747	/*
1748	* IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1749	* accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1750	*/
1751	#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1752
1753	/*
1754	* Insert IVHD entry for device and recurse, insert alias, or insert range as
1755	* necessary for the PCI topology.
1756	*/
1757	static void
1758	insert_ivhd(PCIBus bus, PCIDevice dev, void *opaque)
1759	{
1760	GArray *table_data = opaque;
1761	uint32_t entry;
1762
1763	/* "Select" IVHD entry, type 0x2 */
1764	entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 \| 0x2;
1765	build_append_int_noprefix(table_data, entry, 4);
1766
1767	if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1768	PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1769	uint8_t sec = pci_bus_num(sec_bus);
1770	uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
1771
1772	if (pci_bus_is_express(sec_bus)) {
1773	/*
1774	* Walk the bus if there are subordinates, otherwise use a range
1775	* to cover an entire leaf bus. We could potentially also use a
1776	* range for traversed buses, but we'd need to take care not to
1777	* create both Select and Range entries covering the same device.
1778	* This is easier and potentially more compact.
1779	*
1780	* An example bare metal system seems to use Select entries for
1781	* root ports without a slot (ie. built-ins) and Range entries
1782	* when there is a slot. The same system also only hard-codes
1783	* the alias range for an onboard PCIe-to-PCI bridge, apparently
1784	* making no effort to support nested bridges. We attempt to
1785	* be more thorough here.
1786	*/
1787	if (sec == sub) { /* leaf bus */
1788	/* "Start of Range" IVHD entry, type 0x3 */
1789	entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 \| 0x3;
1790	build_append_int_noprefix(table_data, entry, 4);
1791	/* "End of Range" IVHD entry, type 0x4 */
1792	entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 \| 0x4;
1793	build_append_int_noprefix(table_data, entry, 4);
1794	} else {
1795	pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
1796	}
1797	} else {
1798	/*
1799	* If the secondary bus is conventional, then we need to create an
1800	* Alias range for everything downstream. The range covers the
1801	* first devfn on the secondary bus to the last devfn on the
1802	* subordinate bus. The alias target depends on legacy versus
1803	* express bridges, just as in pci_device_iommu_address_space().
1804	* DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
1805	*/
1806	uint16_t dev_id_a, dev_id_b;
1807
1808	dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
1809
1810	if (pci_is_express(dev) &&
1811	pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
1812	dev_id_b = dev_id_a;
1813	} else {
1814	dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
1815	}
1816
1817	/* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
1818	build_append_int_noprefix(table_data, dev_id_a << 8 \| 0x43, 4);
1819	build_append_int_noprefix(table_data, dev_id_b << 8 \| 0x0, 4);
1820
1821	/* "End of Range" IVHD entry, type 0x4 */
1822	entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 \| 0x4;
1823	build_append_int_noprefix(table_data, entry, 4);
1824	}
1825	}
1826	}
1827
1828	/* For all PCI host bridges, walk and insert IVHD entries */
1829	static int
1830	ivrs_host_bridges(Object obj, void opaque)
1831	{
1832	GArray *ivhd_blob = opaque;
1833
1834	if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1835	PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1836
1837	if (bus && !pci_bus_bypass_iommu(bus)) {
1838	pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
1839	}
1840	}
1841
1842	return 0;
1843	}
1844
1845	static void
1846	build_amd_iommu(GArray table_data, BIOSLinker linker, const char *oem_id,
1847	const char *oem_table_id)
1848	{
1849	AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
1850	GArray *ivhd_blob = g_array_new(false, true, 1);
1851	AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
1852	.oem_table_id = oem_table_id };
1853	uint64_t feature_report;
1854
1855	acpi_table_begin(&table, table_data);
1856	/* IVinfo - IO virtualization information common to all
1857	* IOMMU units in a system
1858	*/
1859	build_append_int_noprefix(table_data,
1860	(1UL << 0) \| /* EFRSup */
1861	(40UL << 8), /* PASize */
1862	4);
1863	/* reserved */
1864	build_append_int_noprefix(table_data, 0, 8);
1865
1866	/*
1867	* A PCI bus walk, for each PCI host bridge, is necessary to create a
1868	* complete set of IVHD entries. Do this into a separate blob so that we
1869	* can calculate the total IVRS table length here and then append the new
1870	* blob further below. Fall back to an entry covering all devices, which
1871	* is sufficient when no aliases are present.
1872	*/
1873	object_child_foreach_recursive(object_get_root(),
1874	ivrs_host_bridges, ivhd_blob);
1875
1876	if (!ivhd_blob->len) {
1877	/*
1878	* Type 1 device entry reporting all devices
1879	* These are 4-byte device entries currently reporting the range of
1880	* Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
1881	*/
1882	build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
1883	}
1884
1885	/*
1886	* When interrupt remapping is supported, we add a special IVHD device
1887	* for type IO-APIC
1888	* Refer to spec - Table 95: IVHD device entry type codes
1889	*
1890	* Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
1891	* See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
1892	*/
1893	if (x86_iommu_ir_supported(x86_iommu_get_default())) {
1894	build_append_int_noprefix(ivhd_blob,
1895	(0x1ull << 56) \| /* type IOAPIC */
1896	(IOAPIC_SB_DEVID << 40) \| /* IOAPIC devid */
1897	0x48, /* special device */
1898	8);
1899	}
1900
1901	/* IVHD definition - type 10h */
1902	build_append_int_noprefix(table_data, 0x10, 1);
1903	/* virtualization flags */
1904	build_append_int_noprefix(table_data,
1905	(1UL << 0) \| /* HtTunEn */
1906	(1UL << 4) \| /* iotblSup */
1907	(1UL << 6) \| /* PrefSup */
1908	(1UL << 7), /* PPRSup */
1909	1);
1910
1911	/* IVHD length */
1912	build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
1913	/* DeviceID */
1914	build_append_int_noprefix(table_data,
1915	object_property_get_int(OBJECT(s->pci), "addr",
1916	&error_abort), 2);
1917	/* Capability offset */
1918	build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
1919	/* IOMMU base address */
1920	build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
1921	/* PCI Segment Group */
1922	build_append_int_noprefix(table_data, 0, 2);
1923	/* IOMMU info */
1924	build_append_int_noprefix(table_data, 0, 2);
1925	/* IOMMU Feature Reporting */
1926	feature_report = (48UL << 30) \| /* HATS */
1927	(48UL << 28) \| /* GATS */
1928	(1UL << 2) \| /* GTSup */
1929	(1UL << 6); /* GASup */
1930	if (s->xtsup) {
1931	feature_report \|= (1UL << 0); /* XTSup */
1932	}
1933	build_append_int_noprefix(table_data, feature_report, 4);
1934
1935	/* IVHD entries as found above */
1936	g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
1937
1938	/* IVHD definition - type 11h */
1939	build_append_int_noprefix(table_data, 0x11, 1);
1940	/* virtualization flags */
1941	build_append_int_noprefix(table_data,
1942	(1UL << 0) \| /* HtTunEn */
1943	(1UL << 4), /* iotblSup */
1944	1);
1945
1946	/* IVHD length */
1947	build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
1948	/* DeviceID */
1949	build_append_int_noprefix(table_data,
1950	object_property_get_int(OBJECT(s->pci), "addr",
1951	&error_abort), 2);
1952	/* Capability offset */
1953	build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
1954	/* IOMMU base address */
1955	build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
1956	/* PCI Segment Group */
1957	build_append_int_noprefix(table_data, 0, 2);
1958	/* IOMMU info */
1959	build_append_int_noprefix(table_data, 0, 2);
1960	/* IOMMU Attributes */
1961	if (!s->iommu.dma_translation) {
1962	build_append_int_noprefix(table_data, (1UL << 0) /* HATDis */, 4);
1963	} else {
1964	build_append_int_noprefix(table_data, 0, 4);
1965	}
1966	/* EFR Register Image */
1967	build_append_int_noprefix(table_data,
1968	amdvi_extended_feature_register(s),
1969	8);
1970	/* EFR Register Image 2 */
1971	build_append_int_noprefix(table_data, 0, 8);
1972
1973	/* IVHD entries as found above */
1974	g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
1975
1976	g_array_free(ivhd_blob, TRUE);
1977	acpi_table_end(linker, &table);
1978	}
1979
1980	typedef
1981	struct AcpiBuildState {
1982	/* Copy of table in RAM (for patching). */
1983	MemoryRegion *table_mr;
1984	/* Is table patched? */
1985	uint8_t patched;
1986	MemoryRegion *rsdp_mr;
1987	MemoryRegion *linker_mr;
1988	} AcpiBuildState;
1989
1990	static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1991	{
1992	Object *pci_host;
1993	QObject *o;
1994
1995	pci_host = acpi_get_i386_pci_host();
1996	if (!pci_host) {
1997	return false;
1998	}
1999
2000	o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2001	if (!o) {
2002	return false;
2003	}
2004	mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2005	qobject_unref(o);
2006	if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2007	return false;
2008	}
2009
2010	o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2011	assert(o);
2012	mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2013	qobject_unref(o);
2014	return true;
2015	}
2016
2017	static
2018	void acpi_build(AcpiBuildTables tables, MachineState machine)
2019	{
2020	PCMachineState *pcms = PC_MACHINE(machine);
2021	X86MachineState *x86ms = X86_MACHINE(machine);
2022	DeviceState *iommu = pcms->iommu;
2023	GArray *table_offsets;
2024	unsigned facs, dsdt, rsdt;
2025	AcpiPmInfo pm;
2026	AcpiMiscInfo misc;
2027	AcpiMcfgInfo mcfg;
2028	Range pci_hole = {}, pci_hole64 = {};
2029	uint8_t *u;
2030	GArray *tables_blob = tables->table_data;
2031	AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2032	Object vmgenid_dev, vmclock_dev;
2033	char *oem_id;
2034	char *oem_table_id;
2035
2036	acpi_get_pm_info(machine, &pm);
2037	acpi_get_misc_info(&misc);
2038	acpi_get_pci_holes(&pci_hole, &pci_hole64);
2039	acpi_get_slic_oem(&slic_oem);
2040
2041	if (slic_oem.id) {
2042	oem_id = slic_oem.id;
2043	} else {
2044	oem_id = x86ms->oem_id;
2045	}
2046
2047	if (slic_oem.table_id) {
2048	oem_table_id = slic_oem.table_id;
2049	} else {
2050	oem_table_id = x86ms->oem_table_id;
2051	}
2052
2053	table_offsets = g_array_new(false, true /* clear */,
2054	sizeof(uint32_t));
2055	ACPI_BUILD_DPRINTF("init ACPI tables\n");
2056
2057	bios_linker_loader_alloc(tables->linker,
2058	ACPI_BUILD_TABLE_FILE, tables_blob,
2059	64 /* Ensure FACS is aligned */,
2060	false /* high memory */);
2061
2062	/*
2063	* FACS is pointed to by FADT.
2064	* We place it first since it's the only table that has alignment
2065	* requirements.
2066	*/
2067	facs = tables_blob->len;
2068	build_facs(tables_blob);
2069
2070	/* DSDT is pointed to by FADT */
2071	dsdt = tables_blob->len;
2072	build_dsdt(tables_blob, tables->linker, &pm, &misc,
2073	&pci_hole, &pci_hole64, machine);
2074
2075	/* ACPI tables pointed to by RSDT */
2076	acpi_add_table(table_offsets, tables_blob);
2077	pm.fadt.facs_tbl_offset = &facs;
2078	pm.fadt.dsdt_tbl_offset = &dsdt;
2079	pm.fadt.xdsdt_tbl_offset = &dsdt;
2080	build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2081
2082	acpi_add_table(table_offsets, tables_blob);
2083	acpi_build_madt(tables_blob, tables->linker, x86ms,
2084	x86ms->oem_id, x86ms->oem_table_id);
2085
2086	#ifdef CONFIG_ACPI_ERST
2087	{
2088	Object *erst_dev;
2089	erst_dev = find_erst_dev();
2090	if (erst_dev) {
2091	acpi_add_table(table_offsets, tables_blob);
2092	build_erst(tables_blob, tables->linker, erst_dev,
2093	x86ms->oem_id, x86ms->oem_table_id);
2094	}
2095	}
2096	#endif
2097
2098	vmgenid_dev = find_vmgenid_dev();
2099	if (vmgenid_dev) {
2100	acpi_add_table(table_offsets, tables_blob);
2101	vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2102	tables->vmgenid, tables->linker, x86ms->oem_id);
2103	}
2104
2105	vmclock_dev = find_vmclock_dev();
2106	if (vmclock_dev) {
2107	acpi_add_table(table_offsets, tables_blob);
2108	vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker,
2109	x86ms->oem_id);
2110	}
2111
2112	if (misc.has_hpet) {
2113	acpi_add_table(table_offsets, tables_blob);
2114	build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2115	x86ms->oem_table_id);
2116	}
2117	#ifdef CONFIG_TPM
2118	if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2119	if (misc.tpm_version == TPM_VERSION_1_2) {
2120	acpi_add_table(table_offsets, tables_blob);
2121	build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2122	x86ms->oem_id, x86ms->oem_table_id);
2123	} else { /* TPM_VERSION_2_0 */
2124	acpi_add_table(table_offsets, tables_blob);
2125	build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2126	x86ms->oem_id, x86ms->oem_table_id);
2127	}
2128	}
2129	#endif
2130	if (machine->numa_state->num_nodes) {
2131	acpi_add_table(table_offsets, tables_blob);
2132	build_srat(tables_blob, tables->linker, machine);
2133	if (machine->numa_state->have_numa_distance) {
2134	acpi_add_table(table_offsets, tables_blob);
2135	build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2136	x86ms->oem_table_id);
2137	}
2138	if (machine->numa_state->hmat_enabled) {
2139	acpi_add_table(table_offsets, tables_blob);
2140	build_hmat(tables_blob, tables->linker, machine->numa_state,
2141	x86ms->oem_id, x86ms->oem_table_id);
2142	}
2143	}
2144	if (acpi_get_mcfg(&mcfg)) {
2145	acpi_add_table(table_offsets, tables_blob);
2146	build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2147	x86ms->oem_table_id);
2148	}
2149	if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2150	acpi_add_table(table_offsets, tables_blob);
2151	build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2152	x86ms->oem_table_id);
2153	} else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2154	acpi_add_table(table_offsets, tables_blob);
2155	build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2156	x86ms->oem_table_id);
2157	} else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2158	PCIDevice *pdev = PCI_DEVICE(iommu);
2159
2160	acpi_add_table(table_offsets, tables_blob);
2161	build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2162	x86ms->oem_id, x86ms->oem_table_id);
2163	}
2164	if (machine->nvdimms_state->is_enabled) {
2165	nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2166	machine->nvdimms_state, machine->ram_slots,
2167	x86ms->oem_id, x86ms->oem_table_id);
2168	}
2169	if (pcms->cxl_devices_state.is_enabled) {
2170	cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2171	x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2172	}
2173
2174	acpi_add_table(table_offsets, tables_blob);
2175	build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2176
2177	if (pcms->wdat_enabled == true) {
2178	g_assert(pm.tco_io_base);
2179	acpi_add_table(table_offsets, tables_blob);
2180	build_ich9_wdat(tables_blob, tables->linker, x86ms->oem_id,
2181	x86ms->oem_table_id, pm.tco_io_base);
2182	}
2183
2184	/* Add tables supplied by user (if any) */
2185	for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2186	unsigned len = acpi_table_len(u);
2187
2188	acpi_add_table(table_offsets, tables_blob);
2189	g_array_append_vals(tables_blob, u, len);
2190	}
2191
2192	/* RSDT is pointed to by RSDP */
2193	rsdt = tables_blob->len;
2194	build_rsdt(tables_blob, tables->linker, table_offsets,
2195	oem_id, oem_table_id);
2196
2197	/* RSDP is in FSEG memory, so allocate it separately */
2198	{
2199	AcpiRsdpData rsdp_data = {
2200	.revision = 0,
2201	.oem_id = x86ms->oem_id,
2202	.xsdt_tbl_offset = NULL,
2203	.rsdt_tbl_offset = &rsdt,
2204	};
2205	build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2206	}
2207
2208	/* We'll expose it all to Guest so we want to reduce
2209	* chance of size changes.
2210	*
2211	* We used to align the tables to 4k, but of course this would
2212	* too simple to be enough. 4k turned out to be too small an
2213	* alignment very soon, and in fact it is almost impossible to
2214	* keep the table size stable for all (max_cpus, max_memory_slots)
2215	* combinations.
2216	*/
2217	acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2218
2219	acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2220
2221	/* Cleanup memory that's no longer used. */
2222	g_array_free(table_offsets, true);
2223	g_free(slic_oem.id);
2224	g_free(slic_oem.table_id);
2225	}
2226
2227	static void acpi_ram_update(MemoryRegion mr, GArray data)
2228	{
2229	uint32_t size = acpi_data_len(data);
2230
2231	/* Make sure RAM size is correct - in case it got changed e.g. by migration */
2232	memory_region_ram_resize(mr, size, &error_abort);
2233
2234	memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2235	memory_region_set_dirty(mr, 0, size);
2236	}
2237
2238	static void acpi_build_update(void *build_opaque)
2239	{
2240	AcpiBuildState *build_state = build_opaque;
2241	AcpiBuildTables tables;
2242
2243	/* No state to update or already patched? Nothing to do. */
2244	if (!build_state \|\| build_state->patched) {
2245	return;
2246	}
2247	build_state->patched = 1;
2248
2249	acpi_build_tables_init(&tables);
2250
2251	acpi_build(&tables, MACHINE(qdev_get_machine()));
2252
2253	acpi_ram_update(build_state->table_mr, tables.table_data);
2254
2255	acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2256
2257	acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2258	acpi_build_tables_cleanup(&tables, true);
2259	}
2260
2261	static void acpi_build_reset(void *build_opaque)
2262	{
2263	AcpiBuildState *build_state = build_opaque;
2264	build_state->patched = 0;
2265	}
2266
2267	static const VMStateDescription vmstate_acpi_build = {
2268	.name = "acpi_build",
2269	.version_id = 1,
2270	.minimum_version_id = 1,
2271	.fields = (const VMStateField[]) {
2272	VMSTATE_UINT8(patched, AcpiBuildState),
2273	VMSTATE_END_OF_LIST()
2274	},
2275	};
2276
2277	void acpi_setup(void)
2278	{
2279	PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2280	X86MachineState *x86ms = X86_MACHINE(pcms);
2281	AcpiBuildTables tables;
2282	AcpiBuildState *build_state;
2283	Object *vmgenid_dev;
2284	#ifdef CONFIG_TPM
2285	TPMIf *tpm;
2286	static FwCfgTPMConfig tpm_config;
2287	#endif
2288
2289	if (!x86ms->fw_cfg) {
2290	ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2291	return;
2292	}
2293
2294	if (!pcms->acpi_build_enabled) {
2295	ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2296	return;
2297	}
2298
2299	if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2300	ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2301	return;
2302	}
2303
2304	build_state = g_malloc0(sizeof *build_state);
2305
2306	acpi_build_tables_init(&tables);
2307	acpi_build(&tables, MACHINE(pcms));
2308
2309	/* Now expose it all to Guest */
2310	build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2311	build_state, tables.table_data,
2312	ACPI_BUILD_TABLE_FILE);
2313	assert(build_state->table_mr != NULL);
2314
2315	build_state->linker_mr =
2316	acpi_add_rom_blob(acpi_build_update, build_state,
2317	tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2318
2319	#ifdef CONFIG_TPM
2320	fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2321	tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2322
2323	tpm = tpm_find();
2324	if (tpm_ppi_enabled(tpm)) {
2325	tpm_config = (FwCfgTPMConfig) {
2326	.tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2327	.tpm_version = tpm_get_version(tpm),
2328	.tpmppi_version = TPM_PPI_VERSION_1_30
2329	};
2330	fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2331	&tpm_config, sizeof tpm_config);
2332	}
2333	#endif
2334
2335	vmgenid_dev = find_vmgenid_dev();
2336	if (vmgenid_dev) {
2337	vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2338	tables.vmgenid);
2339	}
2340
2341	build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2342	build_state, tables.rsdp,
2343	ACPI_BUILD_RSDP_FILE);
2344
2345	qemu_register_reset(acpi_build_reset, build_state);
2346	acpi_build_reset(build_state);
2347	vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2348
2349	/* Cleanup tables but don't free the memory: we track it
2350	* in build_state.
2351	*/
2352	acpi_build_tables_cleanup(&tables, false);
2353	}
2354
2355	GArray acpi_build_madt_standalone(MachineState machine)
2356	{
2357	X86MachineState *x86ms = X86_MACHINE(machine);
2358	GArray *table = g_array_new(false, true, 1);
2359	acpi_build_madt(table, NULL, x86ms, x86ms->oem_id,
2360	x86ms->oem_table_id);
2361	return table;
2362	}