| 1 | /* |
| 2 | * QEMU emulation of an AMD IOMMU (AMD-Vi) |
| 3 | * |
| 4 | * Copyright (C) 2011 Eduard - Gabriel Munteanu |
| 5 | * Copyright (C) 2015, 2016 David Kiarie Kahurani |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef AMD_IOMMU_H |
| 22 | #define AMD_IOMMU_H |
| 23 | |
| 24 | #include "hw/pci/pci.h" |
| 25 | #include "hw/i386/x86-iommu.h" |
| 26 | #include "qom/object.h" |
| 27 | |
| 28 | #define GENMASK64(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) |
| 29 | |
| 30 | /* Capability registers */ |
| 31 | #define AMDVI_CAPAB_BAR_LOW 0x04 |
| 32 | #define AMDVI_CAPAB_BAR_HIGH 0x08 |
| 33 | #define AMDVI_CAPAB_RANGE 0x0C |
| 34 | #define AMDVI_CAPAB_MISC 0x10 |
| 35 | |
| 36 | #define AMDVI_CAPAB_SIZE 0x18 |
| 37 | #define AMDVI_CAPAB_REG_SIZE 0x04 |
| 38 | |
| 39 | /* Capability header data */ |
| 40 | #define AMDVI_CAPAB_ID_SEC 0xf |
| 41 | #define AMDVI_CAPAB_FLAT_EXT (1 << 28) |
| 42 | #define AMDVI_CAPAB_EFR_SUP (1 << 27) |
| 43 | #define AMDVI_CAPAB_FLAG_NPCACHE (1 << 26) |
| 44 | #define AMDVI_CAPAB_FLAG_HTTUNNEL (1 << 25) |
| 45 | #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) |
| 46 | #define AMDVI_CAPAB_INIT_TYPE (3 << 16) |
| 47 | |
| 48 | /* MMIO registers */ |
| 49 | #define AMDVI_MMIO_DEVICE_TABLE 0x0000 |
| 50 | #define AMDVI_MMIO_COMMAND_BASE 0x0008 |
| 51 | #define AMDVI_MMIO_EVENT_BASE 0x0010 |
| 52 | #define AMDVI_MMIO_CONTROL 0x0018 |
| 53 | #define AMDVI_MMIO_EXCL_BASE 0x0020 |
| 54 | #define AMDVI_MMIO_EXCL_LIMIT 0x0028 |
| 55 | #define AMDVI_MMIO_EXT_FEATURES 0x0030 |
| 56 | #define AMDVI_MMIO_XT_GEN_INTR 0x0170 |
| 57 | #define AMDVI_MMIO_COMMAND_HEAD 0x2000 |
| 58 | #define AMDVI_MMIO_COMMAND_TAIL 0x2008 |
| 59 | #define AMDVI_MMIO_EVENT_HEAD 0x2010 |
| 60 | #define AMDVI_MMIO_EVENT_TAIL 0x2018 |
| 61 | #define AMDVI_MMIO_STATUS 0x2020 |
| 62 | #define AMDVI_MMIO_PPR_BASE 0x0038 |
| 63 | #define AMDVI_MMIO_PPR_HEAD 0x2030 |
| 64 | #define AMDVI_MMIO_PPR_TAIL 0x2038 |
| 65 | |
| 66 | #define AMDVI_MMIO_SIZE 0x4000 |
| 67 | |
| 68 | #define AMDVI_MMIO_DEVTAB_SIZE_MASK GENMASK64(8, 0) |
| 69 | #define AMDVI_MMIO_DEVTAB_BASE_MASK GENMASK64(51, 12) |
| 70 | |
| 71 | #define AMDVI_MMIO_DEVTAB_ENTRY_SIZE 32 |
| 72 | #define AMDVI_MMIO_DEVTAB_SIZE_UNIT 4096 |
| 73 | |
| 74 | /* some of this are similar but just for readability */ |
| 75 | #define AMDVI_MMIO_CMDBUF_SIZE_BYTE (AMDVI_MMIO_COMMAND_BASE + 7) |
| 76 | #define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f |
| 77 | #define AMDVI_MMIO_CMDBUF_BASE_MASK GENMASK64(51, 12) |
| 78 | #define AMDVI_MMIO_CMDBUF_HEAD_MASK GENMASK64(18, 4) |
| 79 | #define AMDVI_MMIO_CMDBUF_TAIL_MASK GENMASK64(18, 4) |
| 80 | |
| 81 | #define AMDVI_MMIO_EVTLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7) |
| 82 | #define AMDVI_MMIO_EVTLOG_SIZE_MASK 0x0f |
| 83 | #define AMDVI_MMIO_EVTLOG_BASE_MASK GENMASK64(51, 12) |
| 84 | #define AMDVI_MMIO_EVTLOG_HEAD_MASK GENMASK64(18, 4) |
| 85 | #define AMDVI_MMIO_EVTLOG_TAIL_MASK GENMASK64(18, 4) |
| 86 | |
| 87 | #define AMDVI_MMIO_PPRLOG_SIZE_BYTE (AMDVI_MMIO_PPR_BASE + 7) |
| 88 | #define AMDVI_MMIO_PPRLOG_SIZE_MASK 0x0f |
| 89 | #define AMDVI_MMIO_PPRLOG_BASE_MASK GENMASK64(51, 12) |
| 90 | #define AMDVI_MMIO_PPRLOG_HEAD_MASK GENMASK64(18, 4) |
| 91 | #define AMDVI_MMIO_PPRLOG_TAIL_MASK GENMASK64(18, 4) |
| 92 | |
| 93 | #define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0) |
| 94 | #define AMDVI_MMIO_EXCL_ALLOW_MASK (1ULL << 1) |
| 95 | #define AMDVI_MMIO_EXCL_LIMIT_MASK GENMASK64(51, 12) |
| 96 | #define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff |
| 97 | |
| 98 | /* mmio control register flags */ |
| 99 | #define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0) |
| 100 | #define AMDVI_MMIO_CONTROL_HTTUNEN (1ULL << 1) |
| 101 | #define AMDVI_MMIO_CONTROL_EVENTLOGEN (1ULL << 2) |
| 102 | #define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3) |
| 103 | #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) |
| 104 | #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) |
| 105 | #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) |
| 106 | #define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50) |
| 107 | #define AMDVI_MMIO_CONTROL_INTCAPXTEN (1ULL << 51) |
| 108 | |
| 109 | /* MMIO status register bits */ |
| 110 | #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) |
| 111 | #define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) |
| 112 | #define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) |
| 113 | #define AMDVI_MMIO_STATUS_EVENT_INT (1 << 1) |
| 114 | #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) |
| 115 | |
| 116 | #define AMDVI_CMDBUF_ID_BYTE 0x07 |
| 117 | #define AMDVI_CMDBUF_ID_RSHIFT 4 |
| 118 | |
| 119 | #define AMDVI_CMD_COMPLETION_WAIT 0x01 |
| 120 | #define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02 |
| 121 | #define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03 |
| 122 | #define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04 |
| 123 | #define AMDVI_CMD_INVAL_INTR_TABLE 0x05 |
| 124 | #define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06 |
| 125 | #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 |
| 126 | #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 |
| 127 | |
| 128 | |
| 129 | #define AMDVI_CMD_INVAL_IOMMU_PAGES_S (1ULL << 0) |
| 130 | #define AMDVI_INV_ALL_PAGES (1ULL << 52) |
| 131 | |
| 132 | #define AMDVI_DEVTAB_ENTRY_SIZE 32 |
| 133 | |
| 134 | /* Device table entry bits 0:63 */ |
| 135 | #define AMDVI_DEV_VALID (1ULL << 0) |
| 136 | #define AMDVI_DEV_TRANSLATION_VALID (1ULL << 1) |
| 137 | #define AMDVI_DEV_MODE_MASK 0x7 |
| 138 | #define AMDVI_DEV_MODE_RSHIFT 9 |
| 139 | #define AMDVI_DEV_PT_ROOT_MASK GENMASK64(51, 12) |
| 140 | #define AMDVI_DEV_PT_ROOT_RSHIFT 12 |
| 141 | #define AMDVI_DEV_PERM_SHIFT 61 |
| 142 | #define AMDVI_DEV_PERM_READ (1ULL << 61) |
| 143 | #define AMDVI_DEV_PERM_WRITE (1ULL << 62) |
| 144 | |
| 145 | /* Device table entry bits 64:127 */ |
| 146 | #define AMDVI_DEV_DOMID_ID_MASK GENMASK64(15, 0) |
| 147 | |
| 148 | /* Event codes and flags, as stored in the info field */ |
| 149 | #define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12) |
| 150 | #define AMDVI_EVENT_IOPF (0x2U << 12) |
| 151 | #define AMDVI_EVENT_IOPF_I (1U << 3) |
| 152 | #define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12) |
| 153 | #define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12) |
| 154 | #define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12) |
| 155 | #define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12) |
| 156 | |
| 157 | #define AMDVI_EVENT_LEN 16 |
| 158 | #define AMDVI_PERM_READ (1 << 0) |
| 159 | #define AMDVI_PERM_WRITE (1 << 1) |
| 160 | |
| 161 | #define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */ |
| 162 | #define AMDVI_FEATURE_PPR (1ULL << 1) /* PPR Support */ |
| 163 | #define AMDVI_FEATURE_XT (1ULL << 2) /* x2APIC Support */ |
| 164 | #define AMDVI_FEATURE_GT (1ULL << 4) /* Guest Translation */ |
| 165 | #define AMDVI_FEATURE_IA (1ULL << 6) /* inval all support */ |
| 166 | #define AMDVI_FEATURE_GA (1ULL << 7) /* guest VAPIC support */ |
| 167 | #define AMDVI_FEATURE_HE (1ULL << 8) /* hardware error regs */ |
| 168 | #define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */ |
| 169 | |
| 170 | /* reserved DTE bits */ |
| 171 | #define AMDVI_DTE_QUAD0_RESERVED (GENMASK64(6, 2) | GENMASK64(63, 63)) |
| 172 | #define AMDVI_DTE_QUAD1_RESERVED 0 |
| 173 | #define AMDVI_DTE_QUAD2_RESERVED GENMASK64(53, 52) |
| 174 | #define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48)) |
| 175 | |
| 176 | /* AMDVI paging mode */ |
| 177 | #define AMDVI_GATS_MODE (2ULL << 12) |
| 178 | #define AMDVI_HATS_MODE (2ULL << 10) |
| 179 | #define AMDVI_HATS_MODE_RESERVED (3ULL << 10) |
| 180 | |
| 181 | /* Page Table format */ |
| 182 | |
| 183 | #define AMDVI_PTE_PR (1ULL << 0) |
| 184 | #define AMDVI_PTE_NEXT_LEVEL_MASK GENMASK64(11, 9) |
| 185 | |
| 186 | #define IOMMU_PTE_PRESENT(pte) ((pte) & AMDVI_PTE_PR) |
| 187 | |
| 188 | /* Using level=1 for leaf PTE at 4K page size */ |
| 189 | #define PT_LEVEL_SHIFT(level) (12 + (((level) - 1) * 9)) |
| 190 | |
| 191 | /* Return IOVA bit group used to index the Page Table at specific level */ |
| 192 | #define PT_LEVEL_INDEX(level, iova) (((iova) >> PT_LEVEL_SHIFT(level)) & \ |
| 193 | GENMASK64(8, 0)) |
| 194 | |
| 195 | /* Return the maximum output address for a specified page table level */ |
| 196 | #define PT_LEVEL_MAX_ADDR(level) (((level) > 5) ? (~(0ULL)) : \ |
| 197 | ((1ULL << PT_LEVEL_SHIFT((level) + 1)) - 1)) |
| 198 | |
| 199 | /* Extract the NextLevel field from PTE/PDE */ |
| 200 | #define PTE_NEXT_LEVEL(pte) (((pte) & AMDVI_PTE_NEXT_LEVEL_MASK) >> 9) |
| 201 | |
| 202 | /* Take page table level and return default pagetable size for level */ |
| 203 | #define PTE_LEVEL_PAGE_SIZE(level) (1ULL << (PT_LEVEL_SHIFT(level))) |
| 204 | |
| 205 | /* |
| 206 | * Return address of lower level page table encoded in PTE and specified by |
| 207 | * current level and corresponding IOVA bit group at such level. |
| 208 | */ |
| 209 | #define NEXT_PTE_ADDR(pte, level, iova) (((pte) & AMDVI_DEV_PT_ROOT_MASK) + \ |
| 210 | (PT_LEVEL_INDEX(level, iova) * 8)) |
| 211 | |
| 212 | /* |
| 213 | * Take a PTE value with mode=0x07 and return the page size it encodes. |
| 214 | */ |
| 215 | #define PTE_LARGE_PAGE_SIZE(pte) (1ULL << (1 + cto64(((pte) | 0xfffULL)))) |
| 216 | |
| 217 | /* Return number of PTEs to use for a given page size (expected power of 2) */ |
| 218 | #define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) |
| 219 | |
| 220 | /* IOTLB */ |
| 221 | #define AMDVI_IOTLB_MAX_SIZE 1024 |
| 222 | #define AMDVI_GET_IOTLB_GFN(addr) (addr >> AMDVI_PAGE_SHIFT_4K) |
| 223 | |
| 224 | /* default extended feature */ |
| 225 | #define AMDVI_DEFAULT_EXT_FEATURES \ |
| 226 | (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ |
| 227 | AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ |
| 228 | AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) |
| 229 | |
| 230 | /* capabilities header */ |
| 231 | #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ |
| 232 | AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ |
| 233 | | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \ |
| 234 | AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP) |
| 235 | |
| 236 | /* AMDVI default address */ |
| 237 | #define AMDVI_BASE_ADDR 0xfed80000ULL |
| 238 | |
| 239 | /* page management constants */ |
| 240 | #define AMDVI_PAGE_SHIFT 12 |
| 241 | #define AMDVI_PAGE_SIZE (1ULL << AMDVI_PAGE_SHIFT) |
| 242 | |
| 243 | #define AMDVI_PAGE_SHIFT_4K 12 |
| 244 | #define AMDVI_PAGE_MASK_4K GENMASK64(63, 12) |
| 245 | |
| 246 | #define AMDVI_MAX_GVA_ADDR (2UL << 5) |
| 247 | #define AMDVI_MAX_PH_ADDR (40UL << 8) |
| 248 | #define AMDVI_MAX_VA_ADDR (48UL << 15) |
| 249 | |
| 250 | /* Completion Wait data size */ |
| 251 | #define AMDVI_COMPLETION_DATA_SIZE 8 |
| 252 | |
| 253 | #define AMDVI_COMMAND_SIZE 16 |
| 254 | |
| 255 | #define AMDVI_INT_ADDR_FIRST 0xfee00000 |
| 256 | #define AMDVI_INT_ADDR_LAST 0xfeefffff |
| 257 | #define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1) |
| 258 | |
| 259 | /* SB IOAPIC is always on this device in AMD systems */ |
| 260 | #define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) |
| 261 | |
| 262 | /* Interrupt remapping errors */ |
| 263 | #define AMDVI_IR_ERR 0x1 |
| 264 | #define AMDVI_IR_GET_IRTE 0x2 |
| 265 | #define AMDVI_IR_TARGET_ABORT 0x3 |
| 266 | |
| 267 | /* Interrupt remapping */ |
| 268 | #define AMDVI_IR_REMAP_ENABLE 1ULL |
| 269 | #define AMDVI_IR_INTCTL_SHIFT 60 |
| 270 | #define AMDVI_IR_INTCTL_ABORT 0 |
| 271 | #define AMDVI_IR_INTCTL_PASS 1 |
| 272 | #define AMDVI_IR_INTCTL_REMAP 2 |
| 273 | |
| 274 | #define AMDVI_IR_PHYS_ADDR_MASK GENMASK64(51, 6) |
| 275 | |
| 276 | /* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */ |
| 277 | #define AMDVI_IRTE_OFFSET 0x7ff |
| 278 | |
| 279 | /* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */ |
| 280 | #define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0 |
| 281 | #define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1 |
| 282 | #define AMDVI_IOAPIC_INT_TYPE_SMI 0x2 |
| 283 | #define AMDVI_IOAPIC_INT_TYPE_NMI 0x4 |
| 284 | #define AMDVI_IOAPIC_INT_TYPE_INIT 0x5 |
| 285 | #define AMDVI_IOAPIC_INT_TYPE_EINT 0x7 |
| 286 | |
| 287 | /* Pass through interrupt */ |
| 288 | #define AMDVI_DEV_INT_PASS_MASK (1ULL << 56) |
| 289 | #define AMDVI_DEV_EINT_PASS_MASK (1ULL << 57) |
| 290 | #define AMDVI_DEV_NMI_PASS_MASK (1ULL << 58) |
| 291 | #define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62) |
| 292 | #define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63) |
| 293 | |
| 294 | #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" |
| 295 | OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) |
| 296 | |
| 297 | #define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" |
| 298 | OBJECT_DECLARE_SIMPLE_TYPE(AMDVIPCIState, AMD_IOMMU_PCI) |
| 299 | |
| 300 | #define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region" |
| 301 | |
| 302 | typedef struct AMDVIAddressSpace AMDVIAddressSpace; |
| 303 | |
| 304 | /* functions to steal PCI config space */ |
| 305 | struct AMDVIPCIState { |
| 306 | PCIDevice dev; /* The PCI device itself */ |
| 307 | uint32_t capab_offset; /* capability offset pointer */ |
| 308 | }; |
| 309 | |
| 310 | struct AMDVIState { |
| 311 | X86IOMMUState iommu; /* IOMMU bus device */ |
| 312 | AMDVIPCIState *pci; /* IOMMU PCI device */ |
| 313 | char *pci_id; /* ID of AMDVI-PCI device, if user created */ |
| 314 | |
| 315 | uint32_t version; |
| 316 | |
| 317 | uint64_t mmio_addr; |
| 318 | |
| 319 | bool enabled; /* IOMMU enabled */ |
| 320 | bool cmdbuf_enabled; /* command buffer enabled */ |
| 321 | bool evtlog_enabled; /* event log enabled */ |
| 322 | bool excl_enabled; |
| 323 | |
| 324 | hwaddr devtab; /* base address device table */ |
| 325 | uint64_t devtab_len; /* device table length */ |
| 326 | |
| 327 | hwaddr cmdbuf; /* command buffer base address */ |
| 328 | uint64_t cmdbuf_len; /* command buffer length */ |
| 329 | uint32_t cmdbuf_head; /* current IOMMU read position */ |
| 330 | uint32_t cmdbuf_tail; /* next Software write position */ |
| 331 | bool completion_wait_intr; |
| 332 | |
| 333 | hwaddr evtlog; /* base address event log */ |
| 334 | bool evtlog_intr; |
| 335 | uint32_t evtlog_len; /* event log length */ |
| 336 | uint32_t evtlog_head; /* current IOMMU write position */ |
| 337 | uint32_t evtlog_tail; /* current Software read position */ |
| 338 | |
| 339 | /* unused for now */ |
| 340 | hwaddr excl_base; /* base DVA - IOMMU exclusion range */ |
| 341 | hwaddr excl_limit; /* limit of IOMMU exclusion range */ |
| 342 | bool excl_allow; /* translate accesses to the exclusion range */ |
| 343 | bool excl_enable; /* exclusion range enabled */ |
| 344 | |
| 345 | hwaddr ppr_log; /* base address ppr log */ |
| 346 | uint32_t pprlog_len; /* ppr log len */ |
| 347 | uint32_t pprlog_head; /* ppr log head */ |
| 348 | uint32_t pprlog_tail; /* ppr log tail */ |
| 349 | |
| 350 | MemoryRegion mr_mmio; /* MMIO region */ |
| 351 | MemoryRegion mr_sys; |
| 352 | MemoryRegion mr_nodma; |
| 353 | MemoryRegion mr_ir; |
| 354 | uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */ |
| 355 | uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ |
| 356 | uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */ |
| 357 | bool mmio_enabled; |
| 358 | |
| 359 | /* for each served device */ |
| 360 | GHashTable *address_spaces; |
| 361 | |
| 362 | /* list of address spaces with registered notifiers */ |
| 363 | QLIST_HEAD(, AMDVIAddressSpace) amdvi_as_with_notifiers; |
| 364 | |
| 365 | /* IOTLB */ |
| 366 | GHashTable *iotlb; |
| 367 | |
| 368 | /* Interrupt remapping */ |
| 369 | bool ga_enabled; |
| 370 | bool xtsup; /* xtsup=on command line */ |
| 371 | bool xten; /* guest controlled, x2apic mode enabled */ |
| 372 | bool intcapxten; /* guest controlled, IOMMU x2apic interrupts enabled */ |
| 373 | |
| 374 | /* DMA address translation */ |
| 375 | bool dma_remap; |
| 376 | }; |
| 377 | |
| 378 | uint64_t amdvi_extended_feature_register(AMDVIState *s); |
| 379 | |
| 380 | #endif |