| 1 | /* |
| 2 | * QEMU fw_cfg helpers (X86 specific) |
| 3 | * |
| 4 | * Copyright (c) 2019 Red Hat, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Philippe Mathieu-Daudé |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 10 | * |
| 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 12 | * See the COPYING file in the top-level directory. |
| 13 | */ |
| 14 | |
| 15 | #include "qemu/osdep.h" |
| 16 | #include "system/mshv.h" |
| 17 | #include "system/whpx.h" |
| 18 | #include "system/numa.h" |
| 19 | #include "hw/acpi/acpi.h" |
| 20 | #include "hw/acpi/aml-build.h" |
| 21 | #include "hw/firmware/smbios.h" |
| 22 | #include "hw/i386/fw_cfg.h" |
| 23 | #include "hw/timer/hpet.h" |
| 24 | #include "hw/nvram/fw_cfg.h" |
| 25 | #include "e820_memory_layout.h" |
| 26 | #include "kvm/kvm_i386.h" |
| 27 | #include "qapi/error.h" |
| 28 | #include CONFIG_DEVICES |
| 29 | #include "target/i386/cpu.h" |
| 30 | |
| 31 | #if !defined(CONFIG_HPET) |
| 32 | struct hpet_fw_config hpet_fw_cfg = {.count = UINT8_MAX}; |
| 33 | #endif |
| 34 | |
| 35 | const char *fw_cfg_arch_key_name(uint16_t key) |
| 36 | { |
| 37 | static const struct { |
| 38 | uint16_t key; |
| 39 | const char *name; |
| 40 | } fw_cfg_arch_wellknown_keys[] = { |
| 41 | {FW_CFG_ACPI_TABLES, "acpi_tables"}, |
| 42 | {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"}, |
| 43 | {FW_CFG_IRQ0_OVERRIDE, "irq0_override"}, |
| 44 | {FW_CFG_HPET, "hpet"}, |
| 45 | }; |
| 46 | |
| 47 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { |
| 48 | if (fw_cfg_arch_wellknown_keys[i].key == key) { |
| 49 | return fw_cfg_arch_wellknown_keys[i].name; |
| 50 | } |
| 51 | } |
| 52 | return NULL; |
| 53 | } |
| 54 | |
| 55 | /* Add etc/e820 late, once all regions should be present */ |
| 56 | void fw_cfg_add_e820(FWCfgState *fw_cfg) |
| 57 | { |
| 58 | struct e820_entry *table; |
| 59 | int nr_e820 = e820_get_table(&table); |
| 60 | |
| 61 | fw_cfg_add_file(fw_cfg, "etc/e820", table, nr_e820 * sizeof(*table)); |
| 62 | } |
| 63 | |
| 64 | void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg, |
| 65 | SmbiosEntryPointType ep_type) |
| 66 | { |
| 67 | #ifdef CONFIG_SMBIOS |
| 68 | uint8_t *smbios_tables, *smbios_anchor; |
| 69 | size_t smbios_tables_len, smbios_anchor_len; |
| 70 | struct smbios_phys_mem_area *mem_array; |
| 71 | unsigned i, array_count; |
| 72 | MachineState *ms = MACHINE(pcms); |
| 73 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
| 74 | MachineClass *mc = MACHINE_GET_CLASS(pcms); |
| 75 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); |
| 76 | int nr_e820; |
| 77 | |
| 78 | if (pcmc->smbios_defaults) { |
| 79 | /* These values are guest ABI, do not change */ |
| 80 | smbios_set_defaults("QEMU", mc->desc, mc->name); |
| 81 | } |
| 82 | |
| 83 | /* tell smbios about cpuid version and features */ |
| 84 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); |
| 85 | |
| 86 | if (pcmc->smbios_legacy_mode) { |
| 87 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len, |
| 88 | &error_fatal); |
| 89 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
| 90 | smbios_tables, smbios_tables_len); |
| 91 | return; |
| 92 | } |
| 93 | |
| 94 | /* build the array of physical mem area from e820 table */ |
| 95 | nr_e820 = e820_get_table(NULL); |
| 96 | mem_array = g_new0(struct smbios_phys_mem_area, nr_e820); |
| 97 | for (i = 0, array_count = 0; i < nr_e820; i++) { |
| 98 | uint64_t addr, len; |
| 99 | |
| 100 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { |
| 101 | mem_array[array_count].address = addr; |
| 102 | mem_array[array_count].length = len; |
| 103 | array_count++; |
| 104 | } |
| 105 | } |
| 106 | smbios_get_tables(ms, ep_type, mem_array, array_count, |
| 107 | &smbios_tables, &smbios_tables_len, |
| 108 | &smbios_anchor, &smbios_anchor_len, |
| 109 | &error_fatal); |
| 110 | g_free(mem_array); |
| 111 | |
| 112 | if (smbios_anchor) { |
| 113 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", |
| 114 | smbios_tables, smbios_tables_len); |
| 115 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", |
| 116 | smbios_anchor, smbios_anchor_len); |
| 117 | } |
| 118 | #endif |
| 119 | } |
| 120 | |
| 121 | FWCfgState *fw_cfg_arch_create(MachineState *ms, |
| 122 | uint16_t boot_cpus, |
| 123 | uint16_t apic_id_limit) |
| 124 | { |
| 125 | FWCfgState *fw_cfg; |
| 126 | uint64_t *numa_fw_cfg; |
| 127 | int i; |
| 128 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
| 129 | const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms); |
| 130 | int nb_numa_nodes = ms->numa_state->num_nodes; |
| 131 | |
| 132 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, &address_space_memory); |
| 133 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus); |
| 134 | |
| 135 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
| 136 | * |
| 137 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for |
| 138 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, |
| 139 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface |
| 140 | * for CPU hotplug also uses APIC ID and not "CPU index". |
| 141 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", |
| 142 | * but the "limit to the APIC ID values SeaBIOS may see". |
| 143 | * |
| 144 | * So for compatibility reasons with old BIOSes we are stuck with |
| 145 | * "etc/max-cpus" actually being apic_id_limit |
| 146 | */ |
| 147 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit); |
| 148 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size); |
| 149 | if (acpi_builtin()) { |
| 150 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
| 151 | acpi_tables, acpi_tables_len); |
| 152 | } |
| 153 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1); |
| 154 | |
| 155 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_fw_cfg, sizeof(hpet_fw_cfg)); |
| 156 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
| 157 | * of nodes, one word for each VCPU->node and one word for each node to |
| 158 | * hold the amount of memory. |
| 159 | */ |
| 160 | numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); |
| 161 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
| 162 | for (i = 0; i < cpus->len; i++) { |
| 163 | unsigned int apic_id = cpus->cpus[i].arch_id; |
| 164 | assert(apic_id < apic_id_limit); |
| 165 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); |
| 166 | } |
| 167 | for (i = 0; i < nb_numa_nodes; i++) { |
| 168 | numa_fw_cfg[apic_id_limit + 1 + i] = |
| 169 | cpu_to_le64(ms->numa_state->nodes[i].node_mem); |
| 170 | } |
| 171 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
| 172 | (1 + apic_id_limit + nb_numa_nodes) * |
| 173 | sizeof(*numa_fw_cfg)); |
| 174 | |
| 175 | return fw_cfg; |
| 176 | } |
| 177 | |
| 178 | void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) |
| 179 | { |
| 180 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); |
| 181 | CPUX86State *env = &cpu->env; |
| 182 | uint32_t unused, ebx, ecx, edx; |
| 183 | uint64_t feature_control_bits = 0; |
| 184 | uint64_t *val; |
| 185 | |
| 186 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); |
| 187 | |
| 188 | /* |
| 189 | * Hyper-V in 26100 disallows this bit to be set. |
| 190 | * Otherwise a #GP gets raised. |
| 191 | */ |
| 192 | if (!(whpx_enabled())) { |
| 193 | if (ecx & CPUID_EXT_VMX) { |
| 194 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == |
| 199 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && |
| 200 | (env->mcg_cap & MCG_LMCE_P)) { |
| 201 | feature_control_bits |= FEATURE_CONTROL_LMCE; |
| 202 | } |
| 203 | |
| 204 | if (env->cpuid_level >= 7) { |
| 205 | cpu_x86_cpuid(env, 0x7, 0, &unused, &ebx, &ecx, &unused); |
| 206 | if (ebx & CPUID_7_0_EBX_SGX) { |
| 207 | feature_control_bits |= FEATURE_CONTROL_SGX; |
| 208 | } |
| 209 | if (ecx & CPUID_7_0_ECX_SGX_LC) { |
| 210 | feature_control_bits |= FEATURE_CONTROL_SGX_LC; |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | if (!feature_control_bits) { |
| 215 | return; |
| 216 | } |
| 217 | |
| 218 | val = g_new(uint64_t, 1); |
| 219 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); |
| 220 | fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); |
| 221 | } |
| 222 | |
| 223 | #ifdef CONFIG_ACPI |
| 224 | void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) |
| 225 | { |
| 226 | uint8_t io_size; |
| 227 | Aml *dev = aml_device("FWCF"); |
| 228 | Aml *crs = aml_resource_template(); |
| 229 | |
| 230 | /* |
| 231 | * when using port i/o, the 8-bit data register *always* overlaps |
| 232 | * with half of the 16-bit control register. Hence, the total size |
| 233 | * of the i/o region used is FW_CFG_CTL_SIZE; And the DMA control |
| 234 | * register is located at FW_CFG_DMA_IO_BASE + 4 |
| 235 | */ |
| 236 | assert(fw_cfg_dma_enabled(fw_cfg)); |
| 237 | io_size = ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t); |
| 238 | |
| 239 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); |
| 240 | |
| 241 | /* device present, functioning, decoding, not shown in UI */ |
| 242 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); |
| 243 | |
| 244 | aml_append(crs, |
| 245 | aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)); |
| 246 | |
| 247 | aml_append(dev, aml_name_decl("_CRS", crs)); |
| 248 | aml_append(scope, dev); |
| 249 | } |
| 250 | #endif |