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1 /*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Lots of defines copied from kernel/include/linux/intel-iommu.h:
22 * Copyright (C) 2006-2008 Intel Corporation
23 * Author: Ashok Raj <ashok.raj@intel.com>
24 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
25 *
26 */
27
28 #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
29 #define HW_I386_INTEL_IOMMU_INTERNAL_H
30 #include "hw/i386/intel_iommu.h"
31 #include "system/host_iommu_device.h"
32
33 /*
34 * Intel IOMMU register specification
35 */
36 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
37 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
38 #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
39 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
40 #define DMAR_ECAP_REG_HI 0X14
41 #define DMAR_GCMD_REG 0x18 /* Global command */
42 #define DMAR_GSTS_REG 0x1c /* Global status */
43 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
44 #define DMAR_RTADDR_REG_HI 0X24
45 #define DMAR_CCMD_REG 0x28 /* Context command */
46 #define DMAR_CCMD_REG_HI 0x2c
47 #define DMAR_FSTS_REG 0x34 /* Fault status */
48 #define DMAR_FECTL_REG 0x38 /* Fault control */
49 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */
50 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */
51 #define DMAR_FEUADDR_REG 0x44 /* Upper address */
52 #define DMAR_AFLOG_REG 0x58 /* Advanced fault control */
53 #define DMAR_AFLOG_REG_HI 0X5c
54 #define DMAR_PMEN_REG 0x64 /* Enable protected memory region */
55 #define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */
56 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
57 #define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */
58 #define DMAR_PHMBASE_REG_HI 0X74
59 #define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */
60 #define DMAR_PHMLIMIT_REG_HI 0x7c
61 #define DMAR_IQH_REG 0x80 /* Invalidation queue head */
62 #define DMAR_IQH_REG_HI 0X84
63 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
64 #define DMAR_IQT_REG_HI 0X8c
65 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
66 #define DMAR_IQA_REG_HI 0x94
67 #define DMAR_ICS_REG 0x9c /* Invalidation complete status */
68 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */
69 #define DMAR_IRTA_REG_HI 0xbc
70 #define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
71 #define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
72 #define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
73 #define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
74 #define DMAR_PQH_REG 0xc0 /* Page request queue head */
75 #define DMAR_PQH_REG_HI 0xc4
76 #define DMAR_PQT_REG 0xc8 /* Page request queue tail*/
77 #define DMAR_PQT_REG_HI 0xcc
78 #define DMAR_PQA_REG 0xd0 /* Page request queue address */
79 #define DMAR_PQA_REG_HI 0xd4
80 #define DMAR_PRS_REG 0xdc /* Page request status */
81 #define DMAR_PECTL_REG 0xe0 /* Page request event control */
82 #define DMAR_PEDATA_REG 0xe4 /* Page request event data */
83 #define DMAR_PEADDR_REG 0xe8 /* Page request event address */
84 #define DMAR_PEUADDR_REG 0xec /* Page event upper address */
85 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */
86 #define DMAR_MTRRCAP_REG_HI 0x104
87 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */
88 #define DMAR_MTRRDEF_REG_HI 0x10c
89
90 /* IOTLB registers */
91 #define DMAR_IOTLB_REG_OFFSET 0xf0 /* Offset to the IOTLB registers */
92 #define DMAR_IVA_REG DMAR_IOTLB_REG_OFFSET /* Invalidate address */
93 #define DMAR_IVA_REG_HI (DMAR_IVA_REG + 4)
94 /* IOTLB invalidate register */
95 #define DMAR_IOTLB_REG (DMAR_IOTLB_REG_OFFSET + 0x8)
96 #define DMAR_IOTLB_REG_HI (DMAR_IOTLB_REG + 4)
97
98 /* FRCD */
99 #define DMAR_FRCD_REG_OFFSET 0x220 /* Offset to the fault recording regs */
100 /* NOTICE: If you change the DMAR_FRCD_REG_NR, please remember to change the
101 * DMAR_REG_SIZE in include/hw/i386/intel_iommu.h.
102 * #define DMAR_REG_SIZE (DMAR_FRCD_REG_OFFSET + 16 * DMAR_FRCD_REG_NR)
103 */
104 #define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */
105
106 #define DMAR_FRCD_REG_0_0 0x220 /* The 0th fault recording regs */
107 #define DMAR_FRCD_REG_0_1 0x224
108 #define DMAR_FRCD_REG_0_2 0x228
109 #define DMAR_FRCD_REG_0_3 0x22c
110
111 /* Interrupt Address Range */
112 #define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL
113 #define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL
114 #define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \
115 VTD_INTERRUPT_ADDR_FIRST + 1)
116
117 /* The shift of source_id in the key of IOTLB hash table */
118 #define VTD_IOTLB_SID_SHIFT 26
119 #define VTD_IOTLB_LVL_SHIFT 42
120 #define VTD_IOTLB_PASID_SHIFT 44
121 #define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */
122
123 /* IOTLB_REG */
124 #define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
125 #define VTD_TLB_DSI_FLUSH (2ULL << 60) /* Domain-selective */
126 #define VTD_TLB_PSI_FLUSH (3ULL << 60) /* Page-selective */
127 #define VTD_TLB_FLUSH_GRANU_MASK (3ULL << 60)
128 #define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
129 #define VTD_TLB_DSI_FLUSH_A (2ULL << 57)
130 #define VTD_TLB_PSI_FLUSH_A (3ULL << 57)
131 #define VTD_TLB_FLUSH_GRANU_MASK_A (3ULL << 57)
132 #define VTD_TLB_IVT (1ULL << 63)
133 #define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK)
134
135 /* IVA_REG */
136 #define VTD_IVA_ADDR(val) ((val) & ~0xfffULL)
137 #define VTD_IVA_AM(val) ((val) & 0x3fULL)
138
139 /* GCMD_REG */
140 #define VTD_GCMD_TE (1UL << 31)
141 #define VTD_GCMD_SRTP (1UL << 30)
142 #define VTD_GCMD_SFL (1UL << 29)
143 #define VTD_GCMD_EAFL (1UL << 28)
144 #define VTD_GCMD_WBF (1UL << 27)
145 #define VTD_GCMD_QIE (1UL << 26)
146 #define VTD_GCMD_IRE (1UL << 25)
147 #define VTD_GCMD_SIRTP (1UL << 24)
148 #define VTD_GCMD_CFI (1UL << 23)
149
150 /* GSTS_REG */
151 #define VTD_GSTS_TES (1UL << 31)
152 #define VTD_GSTS_RTPS (1UL << 30)
153 #define VTD_GSTS_FLS (1UL << 29)
154 #define VTD_GSTS_AFLS (1UL << 28)
155 #define VTD_GSTS_WBFS (1UL << 27)
156 #define VTD_GSTS_QIES (1UL << 26)
157 #define VTD_GSTS_IRES (1UL << 25)
158 #define VTD_GSTS_IRTPS (1UL << 24)
159 #define VTD_GSTS_CFIS (1UL << 23)
160
161 /* CCMD_REG */
162 #define VTD_CCMD_ICC (1ULL << 63)
163 #define VTD_CCMD_GLOBAL_INVL (1ULL << 61)
164 #define VTD_CCMD_DOMAIN_INVL (2ULL << 61)
165 #define VTD_CCMD_DEVICE_INVL (3ULL << 61)
166 #define VTD_CCMD_CIRG_MASK (3ULL << 61)
167 #define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59)
168 #define VTD_CCMD_DOMAIN_INVL_A (2ULL << 59)
169 #define VTD_CCMD_DEVICE_INVL_A (3ULL << 59)
170 #define VTD_CCMD_CAIG_MASK (3ULL << 59)
171 #define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
172 #define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL)
173 #define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL)
174
175 /* RTADDR_REG */
176 #define VTD_RTADDR_SMT (1ULL << 10)
177 #define VTD_RTADDR_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
178
179 /* IRTA_REG */
180 #define VTD_IRTA_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
181 #define VTD_IRTA_EIME (1ULL << 11)
182 #define VTD_IRTA_SIZE_MASK (0xfULL)
183
184 /* ECAP_REG */
185 /* (offset >> 4) << 8 */
186 #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
187 #define VTD_ECAP_QI (1ULL << 1)
188 #define VTD_ECAP_DT (1ULL << 2)
189 /* Interrupt Remapping support */
190 #define VTD_ECAP_IR (1ULL << 3)
191 #define VTD_ECAP_EIM (1ULL << 4)
192 #define VTD_ECAP_PT (1ULL << 6)
193 #define VTD_ECAP_SC (1ULL << 7)
194 #define VTD_ECAP_PRS (1ULL << 29)
195 #define VTD_ECAP_MHMV (15ULL << 20)
196 #define VTD_ECAP_SRS (1ULL << 31)
197 #define VTD_ECAP_NWFS (1ULL << 33)
198 #define VTD_ECAP_SET_PSS(x, v) ((x)->ecap = deposit64((x)->ecap, 35, 5, v))
199 #define VTD_ECAP_GET_PSS(ecap) extract64(ecap, 35, 5)
200 #define VTD_ECAP_PASID (1ULL << 40)
201 #define VTD_ECAP_PDS (1ULL << 42)
202 #define VTD_ECAP_SMTS (1ULL << 43)
203 #define VTD_ECAP_SSTS (1ULL << 46)
204 #define VTD_ECAP_FSTS (1ULL << 47)
205
206 /* CAP_REG */
207 /* (offset >> 4) << 24 */
208 #define VTD_CAP_FRO (DMAR_FRCD_REG_OFFSET << 20)
209 #define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40)
210 #define VTD_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */
211 #define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
212 #define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
213 #define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
214 #define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
215 #define VTD_MAMV 18ULL
216 #define VTD_CAP_MAMV (VTD_MAMV << 48)
217 #define VTD_CAP_PSI (1ULL << 39)
218 #define VTD_CAP_SSLPS ((1ULL << 34) | (1ULL << 35))
219 #define VTD_CAP_DRAIN_WRITE (1ULL << 54)
220 #define VTD_CAP_DRAIN_READ (1ULL << 55)
221 #define VTD_CAP_FS1GP (1ULL << 56)
222 #define VTD_CAP_ESRTPS (1ULL << 63)
223 #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
224 #define VTD_CAP_CM (1ULL << 7)
225 #define VTD_PASID_ID_SHIFT 20
226 #define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1)
227
228 /* Supported Adjusted Guest Address Widths */
229 #define VTD_CAP_SAGAW_SHIFT 8
230 #define VTD_CAP_SAGAW_MASK (0x1fULL << VTD_CAP_SAGAW_SHIFT)
231 /* 39-bit AGAW, 3-level page-table */
232 #define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
233 /* 48-bit AGAW, 4-level page-table */
234 #define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
235
236 /* IQT_REG */
237 #define VTD_IQT_QT(dw_bit, val) (dw_bit ? (((val) >> 5) & 0x3fffULL) : \
238 (((val) >> 4) & 0x7fffULL))
239 #define VTD_IQT_QT_256_RSV_BIT 0x10
240
241 /* IQA_REG */
242 #define VTD_IQA_IQA_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
243 #define VTD_IQA_QS 0x7ULL
244 #define VTD_IQA_DW_MASK 0x800
245
246 /* IQH_REG */
247 #define VTD_IQH_QH_SHIFT_4 4
248 #define VTD_IQH_QH_SHIFT_5 5
249 #define VTD_IQH_QH_MASK 0x7fff0ULL
250
251 /* ICS_REG */
252 #define VTD_ICS_IWC 1UL
253
254 /* IECTL_REG */
255 #define VTD_IECTL_IM (1UL << 31)
256 #define VTD_IECTL_IP (1UL << 30)
257
258 /* FSTS_REG */
259 #define VTD_FSTS_FRI_MASK 0xff00UL
260 #define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK)
261 #define VTD_FSTS_IQE (1UL << 4)
262 #define VTD_FSTS_PPF (1UL << 1)
263 #define VTD_FSTS_PFO 1UL
264
265 /* FECTL_REG */
266 #define VTD_FECTL_IM (1UL << 31)
267 #define VTD_FECTL_IP (1UL << 30)
268
269 /* Fault Recording Register */
270 /* For the high 64-bit of 128-bit */
271 #define VTD_FRCD_F (1ULL << 63)
272 #define VTD_FRCD_T (1ULL << 62)
273 #define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32)
274 #define VTD_FRCD_SID_MASK 0xffffULL
275 #define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
276 #define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40)
277 #define VTD_FRCD_PP(val) (((val) & 0x1ULL) << 31)
278 /* For the low 64-bit of 128-bit */
279 #define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
280 #define VTD_FRCD_IR_IDX(val) (((val) & 0xffffULL) << 48)
281
282 /* DMA Remapping Fault Conditions */
283 typedef enum VTDFaultReason {
284 VTD_FR_RESERVED = 0, /* Reserved for Advanced Fault logging */
285 VTD_FR_ROOT_ENTRY_P = 1, /* The Present(P) field of root-entry is 0 */
286 VTD_FR_CONTEXT_ENTRY_P, /* The Present(P) field of context-entry is 0 */
287 VTD_FR_CONTEXT_ENTRY_INV, /* Invalid programming of a context-entry */
288 VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */
289 VTD_FR_WRITE, /* No write permission */
290 VTD_FR_READ, /* No read permission */
291 /* Fail to access a second-stage paging entry (not SS_PML4E) */
292 VTD_FR_PAGING_ENTRY_INV,
293 VTD_FR_ROOT_TABLE_INV, /* Fail to access a root-entry */
294 VTD_FR_CONTEXT_TABLE_INV, /* Fail to access a context-entry */
295 /* Non-zero reserved field in a present root-entry */
296 VTD_FR_ROOT_ENTRY_RSVD,
297 /* Non-zero reserved field in a present context-entry */
298 VTD_FR_CONTEXT_ENTRY_RSVD,
299 /*
300 * Non-zero reserved field in a second-stage paging entry with at lease one
301 * Read(R) and Write(W) or Execute(E) field is Set.
302 */
303 VTD_FR_PAGING_ENTRY_RSVD,
304 /* Translation request or translated request explicitly blocked dut to the
305 * programming of the Translation Type (T) field in the present
306 * context-entry.
307 */
308 VTD_FR_CONTEXT_ENTRY_TT,
309 /* Output address in the interrupt address range */
310 VTD_FR_INTERRUPT_ADDR = 0xE,
311
312 /* Interrupt remapping transition faults */
313 VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved
314 * fields set */
315 VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */
316 VTD_FR_IR_ENTRY_P = 0x22, /* Present (P) not set in IRTE */
317 VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */
318 VTD_FR_IR_IRTE_RSVD = 0x24, /* IRTE Rsvd field non-zero with
319 * Present flag set */
320 VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR
321 * request while disabled */
322 VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
323
324 VTD_FR_RTADDR_INV_TTM = 0x31, /* Invalid TTM in RTADDR */
325
326 VTD_FR_SM_PRE_ABS = 0x47, /* SCT.8 : PRE bit in a present SM CE is 0 */
327
328 /* PASID directory entry access failure */
329 VTD_FR_PASID_DIR_ACCESS_ERR = 0x50,
330 /* The Present(P) field of pasid directory entry is 0 */
331 VTD_FR_PASID_DIR_ENTRY_P = 0x51,
332 VTD_FR_PASID_TABLE_ACCESS_ERR = 0x58, /* PASID table entry access failure */
333 /* The Present(P) field of pasid table entry is 0 */
334 VTD_FR_PASID_ENTRY_P = 0x59,
335 VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */
336
337 /* Fail to access a first-stage paging entry (not FS_PML4E) */
338 VTD_FR_FS_PAGING_ENTRY_INV = 0x70,
339 VTD_FR_FS_PAGING_ENTRY_P = 0x71,
340 /* Non-zero reserved field in present first-stage paging entry */
341 VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72,
342 VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */
343 VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/
344 VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */
345 VTD_FR_SM_WRITE = 0x85, /* No write permission */
346
347 /* Output address in the interrupt address range for scalable mode */
348 VTD_FR_SM_INTERRUPT_ADDR = 0x87,
349 VTD_FR_FS_BIT_UPDATE_FAILED = 0x91, /* SFS.10 */
350 VTD_FR_MAX, /* Guard */
351 } VTDFaultReason;
352
353 #define VTD_CONTEXT_CACHE_GEN_MAX 0xffffffffUL
354
355 /* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
356 struct VTDInvDescIEC {
357 #if HOST_BIG_ENDIAN
358 uint64_t reserved_2:16;
359 uint64_t index:16; /* Start index to invalidate */
360 uint64_t index_mask:5; /* 2^N for continuous int invalidation */
361 uint64_t resved_1:22;
362 uint64_t granularity:1; /* If set, it's global IR invalidation */
363 uint64_t type:4; /* Should always be 0x4 */
364 #else
365 uint32_t type:4; /* Should always be 0x4 */
366 uint32_t granularity:1; /* If set, it's global IR invalidation */
367 uint32_t resved_1:22;
368 uint32_t index_mask:5; /* 2^N for continuous int invalidation */
369 uint32_t index:16; /* Start index to invalidate */
370 uint32_t reserved_2:16;
371 #endif
372 };
373 typedef struct VTDInvDescIEC VTDInvDescIEC;
374
375 /* Queued Invalidation Descriptor */
376 union VTDInvDesc {
377 struct {
378 uint64_t lo;
379 uint64_t hi;
380 };
381 struct {
382 uint64_t val[4];
383 };
384 union {
385 VTDInvDescIEC iec;
386 };
387 };
388 typedef union VTDInvDesc VTDInvDesc;
389
390 /* Page Request Descriptor */
391 union VTDPRDesc {
392 struct {
393 uint64_t lo;
394 uint64_t hi;
395 };
396 struct {
397 uint64_t val[4];
398 };
399 };
400 typedef union VTDPRDesc VTDPRDesc;
401
402 /* Masks for struct VTDInvDesc */
403 #define VTD_INV_DESC_ALL_ONE -1ULL
404 #define VTD_INV_DESC_TYPE(val) ((((val) >> 5) & 0x70ULL) | \
405 ((val) & 0xfULL))
406 #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */
407 #define VTD_INV_DESC_IOTLB 0x2
408 #define VTD_INV_DESC_DEVICE 0x3
409 #define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache
410 Invalidate Descriptor */
411 #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
412 #define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc */
413 #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */
414 #define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc*/
415 #define VTD_INV_DESC_PGRESP 0x9 /* Page Group Response Desc */
416 #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
417
418 /* Masks for Invalidation Wait Descriptor*/
419 #define VTD_INV_DESC_WAIT_SW (1ULL << 5)
420 #define VTD_INV_DESC_WAIT_IF (1ULL << 4)
421 #define VTD_INV_DESC_WAIT_FN (1ULL << 6)
422 #define VTD_INV_DESC_WAIT_DATA_SHIFT 32
423 #define VTD_INV_DESC_WAIT_RSVD_LO(ecap) (0Xfffff100ULL | \
424 (((ecap) & VTD_ECAP_PDS) \
425 ? 0 : (1 << 7)))
426 #define VTD_INV_DESC_WAIT_RSVD_HI 3ULL
427
428 /* Masks for Context-cache Invalidation Descriptor */
429 #define VTD_INV_DESC_CC_G (3ULL << 4)
430 #define VTD_INV_DESC_CC_GLOBAL (1ULL << 4)
431 #define VTD_INV_DESC_CC_DOMAIN (2ULL << 4)
432 #define VTD_INV_DESC_CC_DEVICE (3ULL << 4)
433 #define VTD_INV_DESC_CC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
434 #define VTD_INV_DESC_CC_SID(val) (((val) >> 32) & 0xffffUL)
435 #define VTD_INV_DESC_CC_FM(val) (((val) >> 48) & 3UL)
436 #define VTD_INV_DESC_CC_RSVD 0xfffc00000000f1c0ULL
437
438 /* Masks for IOTLB Invalidate Descriptor */
439 #define VTD_INV_DESC_IOTLB_G (3ULL << 4)
440 #define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4)
441 #define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4)
442 #define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4)
443 #define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
444 #define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL)
445 #define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
446 #define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000f100ULL
447 #define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
448
449 /* Mask for Device IOTLB Invalidate Descriptor */
450 #define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
451 #define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
452 #define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL)
453 #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
454 #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0f1f0
455
456 /* Masks for Interrupt Entry Invalidate Descriptor */
457 #define VTD_INV_DESC_IEC_RSVD 0xffff000007fff1e0ULL
458
459 /* Masks for PASID based Device IOTLB Invalidate Descriptor */
460 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \
461 0xfffffffffffff000ULL)
462 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1)
463 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1)
464 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffULL)
465 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffULL)
466 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0 0xfff000000000f000ULL
467 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1 0x7feULL
468
469 /* Mask for Page Group Response Descriptor */
470 #define VTD_INV_DESC_PGRESP_RSVD_HI 0xfffffffffffff003ULL
471 #define VTD_INV_DESC_PGRESP_RSVD_LO 0xfff00000000001e0ULL
472 #define VTD_INV_DESC_PGRESP_PP(val) (((val) >> 4) & 0x1ULL)
473 #define VTD_INV_DESC_PGRESP_RC(val) (((val) >> 12) & 0xfULL)
474 #define VTD_INV_DESC_PGRESP_RID(val) (((val) >> 16) & 0xffffULL)
475 #define VTD_INV_DESC_PGRESP_PASID(val) (((val) >> 32) & 0xfffffULL)
476 #define VTD_INV_DESC_PGRESP_PRGI(val) (((val) >> 3) & 0x1ffULL)
477
478 /* Rsvd field masks for spte */
479 #define VTD_SPTE_SNP 0x800ULL
480
481 #define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, stale_tm) \
482 stale_tm ? \
483 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM)) : \
484 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
485 #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
486 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
487 #define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \
488 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
489 #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
490 (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
491
492 #define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, stale_tm) \
493 stale_tm ? \
494 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM)) : \
495 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
496 #define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, stale_tm) \
497 stale_tm ? \
498 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM)) : \
499 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM))
500
501 /* Rsvd field masks for fpte */
502 #define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL
503 #define VTD_FPTE_PAGE_L1_RSVD_MASK(aw) \
504 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
505 #define VTD_FPTE_PAGE_L2_RSVD_MASK(aw) \
506 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
507 #define VTD_FPTE_PAGE_L3_RSVD_MASK(aw) \
508 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
509 #define VTD_FPTE_PAGE_L4_RSVD_MASK(aw) \
510 (0x80ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
511
512 #define VTD_FPTE_LPAGE_L2_RSVD_MASK(aw) \
513 (0x1fe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
514 #define VTD_FPTE_LPAGE_L3_RSVD_MASK(aw) \
515 (0x3fffe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
516
517 /* Masks for PIOTLB Invalidate Descriptor */
518 #define VTD_INV_DESC_PIOTLB_G (3ULL << 4)
519 #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4)
520 #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
521 #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
522 #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
523 #define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
524 #define VTD_INV_DESC_PIOTLB_IH(x) extract64((x)->val[1], 6, 1)
525 #define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
526 #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL
527 #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
528
529 /* PASID-cache Invalidate Descriptor (pc_inv_dsc) fields */
530 #define VTD_INV_DESC_PASIDC_G(x) extract64((x)->val[0], 4, 2)
531 #define VTD_INV_DESC_PASIDC_G_DSI 0
532 #define VTD_INV_DESC_PASIDC_G_PASID_SI 1
533 #define VTD_INV_DESC_PASIDC_G_GLOBAL 3
534 #define VTD_INV_DESC_PASIDC_DID(x) extract64((x)->val[0], 16, 16)
535 #define VTD_INV_DESC_PASIDC_PASID(x) extract64((x)->val[0], 32, 20)
536 #define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL
537
538 /* Page Request Descriptor */
539 /* For the low 64-bit of 128-bit */
540 #define VTD_PRD_TYPE (1ULL)
541 #define VTD_PRD_PP(val) (((val) & 1ULL) << 8)
542 #define VTD_PRD_RID(val) (((val) & 0xffffULL) << 16)
543 #define VTD_PRD_PASID(val) (((val) & 0xfffffULL) << 32)
544 #define VTD_PRD_EXR(val) (((val) & 1ULL) << 52)
545 #define VTD_PRD_PMR(val) (((val) & 1ULL) << 53)
546 /* For the high 64-bit of 128-bit */
547 #define VTD_PRD_RDR(val) ((val) & 1ULL)
548 #define VTD_PRD_WRR(val) (((val) & 1ULL) << 1)
549 #define VTD_PRD_LPIG(val) (((val) & 1ULL) << 2)
550 #define VTD_PRD_PRGI(val) (((val) & 0x1ffULL) << 3)
551 #define VTD_PRD_ADDR(val) ((val) & 0xfffffffffffff000ULL)
552
553 /* Page Request Queue constants */
554 #define VTD_PQA_ENTRY_SIZE 32 /* Size of an entry in bytes */
555 /* Page Request Queue masks */
556 #define VTD_PQA_ADDR 0xfffffffffffff000ULL /* PR queue address */
557 #define VTD_PQA_SIZE 0x7ULL /* PR queue size */
558 #define VTD_PR_STATUS_PPR 1UL /* Pending page request */
559 #define VTD_PR_STATUS_PRO 2UL /* Page request overflow */
560 #define VTD_PR_PECTL_IP 0x40000000UL /* PR control interrup pending */
561 #define VTD_PR_PECTL_IM 0x80000000UL /* PR control interrup mask */
562
563 /* Information about page-selective IOTLB invalidate */
564 struct VTDIOTLBPageInvInfo {
565 uint16_t domain_id;
566 uint32_t pasid;
567 uint64_t addr;
568 uint64_t mask;
569 };
570 typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
571
572 /* Pagesize of VTD paging structures, including root and context tables */
573 #define VTD_PAGE_SHIFT 12
574 #define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
575
576 #define VTD_PAGE_SHIFT_4K 12
577 #define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
578 #define VTD_PAGE_SHIFT_2M 21
579 #define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
580 #define VTD_PAGE_SHIFT_1G 30
581 #define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
582
583 struct VTDRootEntry {
584 uint64_t lo;
585 uint64_t hi;
586 };
587 typedef struct VTDRootEntry VTDRootEntry;
588
589 /* Masks for struct VTDRootEntry */
590 #define VTD_ROOT_ENTRY_P 1ULL
591 #define VTD_ROOT_ENTRY_CTP (~0xfffULL)
592
593 #define VTD_ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDRootEntry))
594 #define VTD_ROOT_ENTRY_RSVD(aw) (0xffeULL | ~VTD_HAW_MASK(aw))
595
596 #define VTD_DEVFN_CHECK_MASK 0x80
597
598 /* Masks for struct VTDContextEntry */
599 /* lo */
600 #define VTD_CONTEXT_ENTRY_P (1ULL << 0)
601 #define VTD_CONTEXT_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
602 #define VTD_CONTEXT_ENTRY_TT (3ULL << 2) /* Translation Type */
603 #define VTD_CONTEXT_TT_MULTI_LEVEL 0
604 #define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2)
605 #define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2)
606 /* Second Stage Page Translation Pointer*/
607 #define VTD_CONTEXT_ENTRY_SSPTPTR (~0xfffULL)
608 #define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw))
609 /* hi */
610 #define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */
611 #define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK)
612 #define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL
613
614 #define VTD_CONTEXT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDContextEntry))
615
616 #define VTD_CTX_ENTRY_LEGACY_SIZE 16
617 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32
618
619 #define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3)
620 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw))
621 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL
622 #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL
623
624 /* context entry operations */
625 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \
626 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
627 #define VTD_CE_GET_PRE(ce) \
628 ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)
629
630 typedef struct VTDPASIDCacheInfo {
631 uint8_t type;
632 uint16_t did;
633 uint32_t pasid;
634 bool accel_pce_deleted;
635 } VTDPASIDCacheInfo;
636
637 typedef struct VTDPIOTLBInvInfo {
638 uint16_t domain_id;
639 uint32_t pasid;
640 struct iommu_hwpt_vtd_s1_invalidate *inv_data;
641 } VTDPIOTLBInvInfo;
642
643 /* PASID Table Related Definitions */
644 #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL)
645 #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL)
646 #define VTD_PASID_DIR_ENTRY_SIZE 8
647 #define VTD_PASID_ENTRY_SIZE 64
648 #define VTD_PASID_DIR_BITS_MASK (0x3fffULL)
649 #define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS_MASK)
650 #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disable */
651 #define VTD_PASID_TABLE_ENTRY_NUM (1ULL << 6)
652 #define VTD_PASID_TABLE_BITS_MASK (0x3fULL)
653 #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK)
654 #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
655
656 /* PASID Granular Translation Type Mask */
657 #define VTD_PASID_ENTRY_P 1ULL
658 #define VTD_SM_PASID_ENTRY_PGTT(x) extract64((x)->val[0], 6, 3)
659 #define VTD_SM_PASID_ENTRY_FST 1
660 #define VTD_SM_PASID_ENTRY_SST 2
661 #define VTD_SM_PASID_ENTRY_NESTED 3
662 #define VTD_SM_PASID_ENTRY_PT 4
663
664 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */
665 #define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16)
666
667 #define VTD_SM_PASID_ENTRY_SRE(x) extract64((x)->val[2], 0, 1)
668 #define VTD_SM_PASID_ENTRY_FSPM(x) extract64((x)->val[2], 2, 2)
669 #define VTD_SM_PASID_ENTRY_WPE(x) extract64((x)->val[2], 4, 1)
670 #define VTD_SM_PASID_ENTRY_EAFE(x) extract64((x)->val[2], 7, 1)
671 #define VTD_SM_PASID_ENTRY_FSPTPFN(x) extract64((x)->val[2], 12, 52)
672
673 /* First Stage Paging Structure */
674 /* Masks for First Stage Paging Entry */
675 #define VTD_FS_P 1ULL
676 #define VTD_FS_RW (1ULL << 1)
677 #define VTD_FS_US (1ULL << 2)
678 #define VTD_FS_A (1ULL << 5)
679 #define VTD_FS_D (1ULL << 6)
680
681 /* Second Stage Page Translation Pointer*/
682 #define VTD_SM_PASID_ENTRY_SSPTPTR (~0xfffULL)
683
684 /* Second Stage Paging Structure */
685 /* Masks for Second Stage Paging Entry */
686 #define VTD_SS_RW_MASK 3ULL
687 #define VTD_SS_R 1ULL
688 #define VTD_SS_W (1ULL << 1)
689 #define VTD_SS_IGN_COM 0xbff0000000000000ULL
690 #define VTD_SS_TM (1ULL << 62)
691
692 /* Common for both First Stage and Second Stage */
693 #define VTD_PML4_LEVEL 4
694 #define VTD_PDP_LEVEL 3
695 #define VTD_PD_LEVEL 2
696 #define VTD_PT_LEVEL 1
697 #define VTD_PT_ENTRY_NR 512
698 #define VTD_PT_PAGE_SIZE_MASK (1ULL << 7)
699 #define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
700
701 /* Bits to decide the offset for each level */
702 #define VTD_LEVEL_BITS 9
703
704 /* IOMMU Index */
705 typedef enum VTDIOMMUIndex {
706 VTD_IDX_UNTRANSLATED = 0, /* Default */
707 VTD_IDX_TRANSLATED = 1,
708 VTD_IDX_ATS = 2,
709 VTD_IDX_COUNT = 3, /* Number of supported indexes */
710 } VTDIOMMUIndex;
711
712 typedef struct VTDHostIOMMUDevice {
713 IntelIOMMUState *iommu_state;
714 PCIBus *bus;
715 uint8_t devfn;
716 HostIOMMUDevice *hiod;
717 QLIST_HEAD(, VTDAccelPASIDCacheEntry) pasid_cache_list;
718 } VTDHostIOMMUDevice;
719
720 /*
721 * PCI bus number (or SID) is not reliable since the device is usaully
722 * initialized before guest can configure the PCI bridge
723 * (SECONDARY_BUS_NUMBER).
724 */
725 struct vtd_as_key {
726 PCIBus *bus;
727 uint8_t devfn;
728 uint32_t pasid;
729 };
730
731 static inline dma_addr_t vtd_pe_get_fspt_base(VTDPASIDEntry *pe)
732 {
733 return VTD_SM_PASID_ENTRY_FSPTPFN(pe) << VTD_PAGE_SHIFT;
734 }
735
736 /*
737 * First stage IOVA address width: 48 bits for 4-level paging(FSPM=00)
738 * 57 bits for 5-level paging(FSPM=01)
739 */
740 static inline uint32_t vtd_pe_get_fs_aw(VTDPASIDEntry *pe)
741 {
742 /*
743 * Paging mode for first-stage translation (VTD spec Figure 9-6)
744 * 00: 4-level paging, 01: 5-level paging
745 */
746 return VTD_HOST_AW_48BIT + VTD_SM_PASID_ENTRY_FSPM(pe) * 9;
747 }
748
749 static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe)
750 {
751 return (VTD_SM_PASID_ENTRY_PGTT(pe) == VTD_SM_PASID_ENTRY_PT);
752 }
753
754 /* check if PGTT is first stage translation */
755 static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *pe)
756 {
757 return (VTD_SM_PASID_ENTRY_PGTT(pe) == VTD_SM_PASID_ENTRY_FST);
758 }
759
760 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
761 {
762 return pdire->val & 1;
763 }
764
765 static inline bool vtd_pe_present(VTDPASIDEntry *pe)
766 {
767 return pe->val[0] & VTD_PASID_ENTRY_P;
768 }
769
770 static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)
771 {
772 return memcmp(p1, p2, sizeof(*p1));
773 }
774
775 static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce)
776 {
777 return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7);
778 }
779
780 int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,
781 VTDPASIDDirEntry *pdire);
782 int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,
783 dma_addr_t addr, VTDPASIDEntry *pe);
784 int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
785 uint8_t devfn, VTDContextEntry *ce);
786 VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid);
787 int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, uint8_t devfn,
788 uint32_t pasid, VTDPASIDEntry *pe);
789 #endif