| 1 | /* |
| 2 | * KVM in-kernel APIC support |
| 3 | * |
| 4 | * Copyright (c) 2011 Siemens AG |
| 5 | * |
| 6 | * Authors: |
| 7 | * Jan Kiszka <jan.kiszka@siemens.com> |
| 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL version 2. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | */ |
| 12 | |
| 13 | #include "qemu/osdep.h" |
| 14 | #include "qemu/module.h" |
| 15 | #include "hw/i386/apic_internal.h" |
| 16 | #include "hw/pci/msi.h" |
| 17 | #include "system/hw_accel.h" |
| 18 | #include "system/kvm.h" |
| 19 | #include "kvm/kvm_i386.h" |
| 20 | #include "kvm/tdx.h" |
| 21 | |
| 22 | static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, |
| 23 | int reg_id, uint32_t val) |
| 24 | { |
| 25 | *((uint32_t *)(kapic->regs + (reg_id << 4))) = val; |
| 26 | } |
| 27 | |
| 28 | static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic, |
| 29 | int reg_id) |
| 30 | { |
| 31 | return *((uint32_t *)(kapic->regs + (reg_id << 4))); |
| 32 | } |
| 33 | |
| 34 | static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) |
| 35 | { |
| 36 | int i; |
| 37 | |
| 38 | memset(kapic, 0, sizeof(*kapic)); |
| 39 | if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { |
| 40 | kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id); |
| 41 | } else { |
| 42 | kvm_apic_set_reg(kapic, 0x2, s->id << 24); |
| 43 | } |
| 44 | kvm_apic_set_reg(kapic, 0x8, s->tpr); |
| 45 | kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24); |
| 46 | kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff); |
| 47 | kvm_apic_set_reg(kapic, 0xf, s->spurious_vec); |
| 48 | for (i = 0; i < 8; i++) { |
| 49 | kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]); |
| 50 | kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]); |
| 51 | kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]); |
| 52 | } |
| 53 | kvm_apic_set_reg(kapic, 0x28, s->esr); |
| 54 | kvm_apic_set_reg(kapic, 0x30, s->icr[0]); |
| 55 | kvm_apic_set_reg(kapic, 0x31, s->icr[1]); |
| 56 | for (i = 0; i < APIC_LVT_NB; i++) { |
| 57 | kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]); |
| 58 | } |
| 59 | kvm_apic_set_reg(kapic, 0x38, s->initial_count); |
| 60 | kvm_apic_set_reg(kapic, 0x3e, s->divide_conf); |
| 61 | } |
| 62 | |
| 63 | void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) |
| 64 | { |
| 65 | int i, v; |
| 66 | |
| 67 | if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { |
| 68 | assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id); |
| 69 | } else { |
| 70 | s->id = kvm_apic_get_reg(kapic, 0x2) >> 24; |
| 71 | } |
| 72 | s->tpr = kvm_apic_get_reg(kapic, 0x8); |
| 73 | s->arb_id = kvm_apic_get_reg(kapic, 0x9); |
| 74 | s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24; |
| 75 | s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28; |
| 76 | s->spurious_vec = kvm_apic_get_reg(kapic, 0xf); |
| 77 | for (i = 0; i < 8; i++) { |
| 78 | s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i); |
| 79 | s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i); |
| 80 | s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i); |
| 81 | } |
| 82 | s->esr = kvm_apic_get_reg(kapic, 0x28); |
| 83 | s->icr[0] = kvm_apic_get_reg(kapic, 0x30); |
| 84 | s->icr[1] = kvm_apic_get_reg(kapic, 0x31); |
| 85 | for (i = 0; i < APIC_LVT_NB; i++) { |
| 86 | s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i); |
| 87 | } |
| 88 | s->initial_count = kvm_apic_get_reg(kapic, 0x38); |
| 89 | s->divide_conf = kvm_apic_get_reg(kapic, 0x3e); |
| 90 | |
| 91 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
| 92 | s->count_shift = (v + 1) & 7; |
| 93 | |
| 94 | s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 95 | apic_next_timer(s, s->initial_count_load_time); |
| 96 | } |
| 97 | |
| 98 | static int kvm_apic_set_base(APICCommonState *s, uint64_t val) |
| 99 | { |
| 100 | s->apicbase = val; |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val) |
| 105 | { |
| 106 | s->tpr = (val & 0x0f) << 4; |
| 107 | } |
| 108 | |
| 109 | static uint8_t kvm_apic_get_tpr(APICCommonState *s) |
| 110 | { |
| 111 | return s->tpr >> 4; |
| 112 | } |
| 113 | |
| 114 | static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable) |
| 115 | { |
| 116 | struct kvm_tpr_access_ctl ctl = { |
| 117 | .enabled = enable |
| 118 | }; |
| 119 | |
| 120 | kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl); |
| 121 | } |
| 122 | |
| 123 | static void kvm_apic_vapic_base_update(APICCommonState *s) |
| 124 | { |
| 125 | struct kvm_vapic_addr vapid_addr = { |
| 126 | .vapic_addr = s->vapic_paddr, |
| 127 | }; |
| 128 | int ret; |
| 129 | |
| 130 | ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr); |
| 131 | if (ret < 0) { |
| 132 | fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", |
| 133 | strerror(-ret)); |
| 134 | abort(); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | static void kvm_apic_put(CPUState *cs, run_on_cpu_data data) |
| 139 | { |
| 140 | APICCommonState *s = data.host_ptr; |
| 141 | struct kvm_lapic_state kapic; |
| 142 | int ret; |
| 143 | |
| 144 | if (is_tdx_vm()) { |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | kvm_put_apicbase(s->cpu, s->apicbase); |
| 149 | kvm_put_apic_state(s, &kapic); |
| 150 | |
| 151 | ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); |
| 152 | if (ret < 0) { |
| 153 | fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(-ret)); |
| 154 | abort(); |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | static void kvm_apic_post_load(APICCommonState *s) |
| 159 | { |
| 160 | run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); |
| 161 | } |
| 162 | |
| 163 | static void do_inject_external_nmi(CPUState *cpu, run_on_cpu_data data) |
| 164 | { |
| 165 | APICCommonState *s = data.host_ptr; |
| 166 | uint32_t lvt; |
| 167 | int ret; |
| 168 | |
| 169 | cpu_synchronize_state(cpu); |
| 170 | |
| 171 | lvt = s->lvt[APIC_LVT_LINT1]; |
| 172 | if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) { |
| 173 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); |
| 174 | if (ret < 0) { |
| 175 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", |
| 176 | strerror(-ret)); |
| 177 | } |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | static void kvm_apic_external_nmi(APICCommonState *s) |
| 182 | { |
| 183 | run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s)); |
| 184 | } |
| 185 | |
| 186 | static void kvm_send_msi(MSIMessage *msg) |
| 187 | { |
| 188 | int ret; |
| 189 | |
| 190 | /* |
| 191 | * The message has already passed through interrupt remapping if enabled, |
| 192 | * but the legacy extended destination ID in low bits still needs to be |
| 193 | * handled. |
| 194 | */ |
| 195 | msg->address = kvm_swizzle_msi_ext_dest_id(msg->address); |
| 196 | |
| 197 | ret = kvm_irqchip_send_msi(kvm_state, *msg); |
| 198 | if (ret < 0) { |
| 199 | fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", |
| 200 | strerror(-ret)); |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, |
| 205 | unsigned size) |
| 206 | { |
| 207 | return ~(uint64_t)0; |
| 208 | } |
| 209 | |
| 210 | static void kvm_apic_mem_write(void *opaque, hwaddr addr, |
| 211 | uint64_t data, unsigned size) |
| 212 | { |
| 213 | MSIMessage msg = { .address = addr, .data = data }; |
| 214 | |
| 215 | kvm_send_msi(&msg); |
| 216 | } |
| 217 | |
| 218 | static const MemoryRegionOps kvm_apic_io_ops = { |
| 219 | .read = kvm_apic_mem_read, |
| 220 | .write = kvm_apic_mem_write, |
| 221 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 222 | }; |
| 223 | |
| 224 | static void kvm_apic_reset(APICCommonState *s) |
| 225 | { |
| 226 | /* Not used by KVM, which uses the CPU mp_state instead. */ |
| 227 | s->wait_for_sipi = 0; |
| 228 | |
| 229 | run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); |
| 230 | } |
| 231 | |
| 232 | static void kvm_apic_realize(DeviceState *dev, Error **errp) |
| 233 | { |
| 234 | APICCommonState *s = APIC_COMMON(dev); |
| 235 | |
| 236 | memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s, |
| 237 | "kvm-apic-msi", APIC_SPACE_SIZE); |
| 238 | |
| 239 | assert(kvm_has_gsi_routing()); |
| 240 | msi_nonbroken = true; |
| 241 | } |
| 242 | |
| 243 | static void kvm_apic_unrealize(DeviceState *dev) |
| 244 | { |
| 245 | } |
| 246 | |
| 247 | static void kvm_apic_class_init(ObjectClass *klass, const void *data) |
| 248 | { |
| 249 | APICCommonClass *k = APIC_COMMON_CLASS(klass); |
| 250 | |
| 251 | k->realize = kvm_apic_realize; |
| 252 | k->unrealize = kvm_apic_unrealize; |
| 253 | k->reset = kvm_apic_reset; |
| 254 | k->set_base = kvm_apic_set_base; |
| 255 | k->set_tpr = kvm_apic_set_tpr; |
| 256 | k->get_tpr = kvm_apic_get_tpr; |
| 257 | k->post_load = kvm_apic_post_load; |
| 258 | k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting; |
| 259 | k->vapic_base_update = kvm_apic_vapic_base_update; |
| 260 | k->external_nmi = kvm_apic_external_nmi; |
| 261 | k->send_msi = kvm_send_msi; |
| 262 | } |
| 263 | |
| 264 | static const TypeInfo kvm_apic_info = { |
| 265 | .name = "kvm-apic", |
| 266 | .parent = TYPE_APIC_COMMON, |
| 267 | .instance_size = sizeof(APICCommonState), |
| 268 | .class_init = kvm_apic_class_init, |
| 269 | }; |
| 270 | |
| 271 | static void kvm_apic_register_types(void) |
| 272 | { |
| 273 | type_register_static(&kvm_apic_info); |
| 274 | } |
| 275 | |
| 276 | type_init(kvm_apic_register_types) |