| 1 | /* |
| 2 | * microvm device tree support |
| 3 | * |
| 4 | * This generates an device tree for microvm and exports it via fw_cfg |
| 5 | * as "etc/fdt" to the firmware (edk2 specifically). |
| 6 | * |
| 7 | * The use case is to allow edk2 find the pcie ecam and the virtio |
| 8 | * devices, without adding an ACPI parser, reusing the fdt parser |
| 9 | * which is needed anyway for the arm platform. |
| 10 | * |
| 11 | * Note 1: The device tree is incomplete. CPUs and memory is missing |
| 12 | * for example, those can be detected using other fw_cfg files. |
| 13 | * Also pci ecam irq routing is not there, edk2 doesn't use |
| 14 | * interrupts. |
| 15 | * |
| 16 | * Note 2: This is for firmware only. OSes should use the more |
| 17 | * complete ACPI tables for hardware discovery. |
| 18 | * |
| 19 | * ---------------------------------------------------------------------- |
| 20 | * |
| 21 | * This program is free software; you can redistribute it and/or modify it |
| 22 | * under the terms and conditions of the GNU General Public License, |
| 23 | * version 2 or later, as published by the Free Software Foundation. |
| 24 | * |
| 25 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 26 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 27 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 28 | * more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License along with |
| 31 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 32 | */ |
| 33 | #include "qemu/osdep.h" |
| 34 | #include "qemu/cutils.h" |
| 35 | #include "qapi/error.h" |
| 36 | #include "system/device_tree.h" |
| 37 | #include "hw/char/serial-isa.h" |
| 38 | #include "hw/i386/fw_cfg.h" |
| 39 | #include "hw/rtc/mc146818rtc.h" |
| 40 | #include "hw/core/sysbus.h" |
| 41 | #include "hw/virtio/virtio-mmio.h" |
| 42 | #include "hw/usb/xhci.h" |
| 43 | |
| 44 | #include "microvm-dt.h" |
| 45 | |
| 46 | static bool debug; |
| 47 | |
| 48 | static void dt_add_microvm_irq(MicrovmMachineState *mms, |
| 49 | const char *nodename, uint32_t irq) |
| 50 | { |
| 51 | MachineState *ms = MACHINE(mms); |
| 52 | int index = 0; |
| 53 | |
| 54 | if (irq >= IO_APIC_SECONDARY_IRQBASE) { |
| 55 | irq -= IO_APIC_SECONDARY_IRQBASE; |
| 56 | index++; |
| 57 | } |
| 58 | |
| 59 | qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", |
| 60 | mms->ioapic_phandle[index]); |
| 61 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0); |
| 62 | } |
| 63 | |
| 64 | static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio) |
| 65 | { |
| 66 | MachineState *ms = MACHINE(mms); |
| 67 | SysBusDevice *dev = SYS_BUS_DEVICE(mmio); |
| 68 | VirtioBusState *mmio_virtio_bus = &mmio->bus; |
| 69 | BusState *mmio_bus = &mmio_virtio_bus->parent_obj; |
| 70 | char *nodename; |
| 71 | |
| 72 | if (QTAILQ_EMPTY(&mmio_bus->children)) { |
| 73 | return; |
| 74 | } |
| 75 | |
| 76 | hwaddr base = dev->mmio[0].addr; |
| 77 | hwaddr size = 512; |
| 78 | unsigned index = (base - VIRTIO_MMIO_BASE) / size; |
| 79 | uint32_t irq = mms->virtio_irq_base + index; |
| 80 | |
| 81 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); |
| 82 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 83 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "virtio,mmio"); |
| 84 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); |
| 85 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
| 86 | dt_add_microvm_irq(mms, nodename, irq); |
| 87 | g_free(nodename); |
| 88 | } |
| 89 | |
| 90 | static void dt_add_xhci(MicrovmMachineState *mms) |
| 91 | { |
| 92 | const char compat[] = "generic-xhci"; |
| 93 | MachineState *ms = MACHINE(mms); |
| 94 | uint32_t irq = MICROVM_XHCI_IRQ; |
| 95 | hwaddr base = MICROVM_XHCI_BASE; |
| 96 | hwaddr size = XHCI_LEN_REGS; |
| 97 | char *nodename; |
| 98 | |
| 99 | nodename = g_strdup_printf("/usb@%" PRIx64, base); |
| 100 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 101 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); |
| 102 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); |
| 103 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
| 104 | dt_add_microvm_irq(mms, nodename, irq); |
| 105 | g_free(nodename); |
| 106 | } |
| 107 | |
| 108 | static void dt_add_pcie(MicrovmMachineState *mms) |
| 109 | { |
| 110 | MachineState *ms = MACHINE(mms); |
| 111 | hwaddr base = PCIE_MMIO_BASE; |
| 112 | int nr_pcie_buses; |
| 113 | char *nodename; |
| 114 | |
| 115 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
| 116 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 117 | qemu_fdt_setprop_string(ms->fdt, nodename, |
| 118 | "compatible", "pci-host-ecam-generic"); |
| 119 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); |
| 120 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); |
| 121 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); |
| 122 | qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); |
| 123 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
| 124 | |
| 125 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
| 126 | 2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE); |
| 127 | if (mms->gpex.mmio64.size) { |
| 128 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", |
| 129 | |
| 130 | 1, FDT_PCI_RANGE_MMIO, |
| 131 | 2, mms->gpex.mmio32.base, |
| 132 | 2, mms->gpex.mmio32.base, |
| 133 | 2, mms->gpex.mmio32.size, |
| 134 | |
| 135 | 1, FDT_PCI_RANGE_MMIO_64BIT, |
| 136 | 2, mms->gpex.mmio64.base, |
| 137 | 2, mms->gpex.mmio64.base, |
| 138 | 2, mms->gpex.mmio64.size); |
| 139 | } else { |
| 140 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", |
| 141 | |
| 142 | 1, FDT_PCI_RANGE_MMIO, |
| 143 | 2, mms->gpex.mmio32.base, |
| 144 | 2, mms->gpex.mmio32.base, |
| 145 | 2, mms->gpex.mmio32.size); |
| 146 | } |
| 147 | |
| 148 | nr_pcie_buses = PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN; |
| 149 | qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, |
| 150 | nr_pcie_buses - 1); |
| 151 | |
| 152 | g_free(nodename); |
| 153 | } |
| 154 | |
| 155 | static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev) |
| 156 | { |
| 157 | MachineState *ms = MACHINE(mms); |
| 158 | hwaddr base = dev->mmio[0].addr; |
| 159 | char *nodename; |
| 160 | uint32_t ph; |
| 161 | int index; |
| 162 | |
| 163 | switch (base) { |
| 164 | case IO_APIC_DEFAULT_ADDRESS: |
| 165 | index = 0; |
| 166 | break; |
| 167 | case IO_APIC_SECONDARY_ADDRESS: |
| 168 | index = 1; |
| 169 | break; |
| 170 | default: |
| 171 | fprintf(stderr, "unknown ioapic @ %" PRIx64 "\n", base); |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | nodename = g_strdup_printf("/ioapic%d@%" PRIx64, index + 1, base); |
| 176 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 177 | qemu_fdt_setprop_string(ms->fdt, nodename, |
| 178 | "compatible", "intel,ce4100-ioapic"); |
| 179 | qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); |
| 180 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 0x2); |
| 181 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); |
| 182 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
| 183 | 2, base, 2, 0x1000); |
| 184 | |
| 185 | ph = qemu_fdt_alloc_phandle(ms->fdt); |
| 186 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", ph); |
| 187 | qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,phandle", ph); |
| 188 | mms->ioapic_phandle[index] = ph; |
| 189 | |
| 190 | g_free(nodename); |
| 191 | } |
| 192 | |
| 193 | static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev) |
| 194 | { |
| 195 | const char compat[] = "ns16550"; |
| 196 | uint32_t irq = object_property_get_int(OBJECT(dev), "irq", &error_fatal); |
| 197 | hwaddr base = object_property_get_int(OBJECT(dev), "iobase", &error_fatal); |
| 198 | MachineState *ms = MACHINE(mms); |
| 199 | hwaddr size = 8; |
| 200 | char *nodename; |
| 201 | |
| 202 | nodename = g_strdup_printf("/serial@%" PRIx64, base); |
| 203 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 204 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); |
| 205 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); |
| 206 | dt_add_microvm_irq(mms, nodename, irq); |
| 207 | |
| 208 | if (base == 0x3f8 /* com1 */) { |
| 209 | qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); |
| 210 | } |
| 211 | |
| 212 | g_free(nodename); |
| 213 | } |
| 214 | |
| 215 | static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev) |
| 216 | { |
| 217 | const char compat[] = "motorola,mc146818"; |
| 218 | uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal); |
| 219 | hwaddr base = object_property_get_uint(OBJECT(dev), "iobase", &error_fatal); |
| 220 | MachineState *ms = MACHINE(mms); |
| 221 | hwaddr size = 8; |
| 222 | char *nodename; |
| 223 | |
| 224 | nodename = g_strdup_printf("/rtc@%" PRIx64, base); |
| 225 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 226 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); |
| 227 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); |
| 228 | dt_add_microvm_irq(mms, nodename, irq); |
| 229 | g_free(nodename); |
| 230 | } |
| 231 | |
| 232 | static void dt_setup_isa_bus(MicrovmMachineState *mms, DeviceState *bridge) |
| 233 | { |
| 234 | BusState *bus = qdev_get_child_bus(bridge, "isa.0"); |
| 235 | BusChild *kid; |
| 236 | Object *obj; |
| 237 | |
| 238 | QTAILQ_FOREACH(kid, &bus->children, sibling) { |
| 239 | DeviceState *dev = kid->child; |
| 240 | |
| 241 | /* serial */ |
| 242 | obj = object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL); |
| 243 | if (obj) { |
| 244 | dt_add_isa_serial(mms, ISA_DEVICE(obj)); |
| 245 | continue; |
| 246 | } |
| 247 | |
| 248 | /* rtc */ |
| 249 | obj = object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC); |
| 250 | if (obj) { |
| 251 | dt_add_isa_rtc(mms, ISA_DEVICE(obj)); |
| 252 | continue; |
| 253 | } |
| 254 | |
| 255 | if (debug) { |
| 256 | fprintf(stderr, "%s: unhandled: %s\n", __func__, |
| 257 | object_get_typename(OBJECT(dev))); |
| 258 | } |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | static void dt_setup_sys_bus(MicrovmMachineState *mms) |
| 263 | { |
| 264 | BusState *bus; |
| 265 | BusChild *kid; |
| 266 | Object *obj; |
| 267 | |
| 268 | /* sysbus devices */ |
| 269 | bus = sysbus_get_default(); |
| 270 | QTAILQ_FOREACH(kid, &bus->children, sibling) { |
| 271 | DeviceState *dev = kid->child; |
| 272 | |
| 273 | /* ioapic */ |
| 274 | obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC); |
| 275 | if (obj) { |
| 276 | dt_add_ioapic(mms, SYS_BUS_DEVICE(obj)); |
| 277 | continue; |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | QTAILQ_FOREACH(kid, &bus->children, sibling) { |
| 282 | DeviceState *dev = kid->child; |
| 283 | |
| 284 | /* virtio */ |
| 285 | obj = object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO); |
| 286 | if (obj) { |
| 287 | dt_add_virtio(mms, VIRTIO_MMIO(obj)); |
| 288 | continue; |
| 289 | } |
| 290 | |
| 291 | /* xhci */ |
| 292 | obj = object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS); |
| 293 | if (obj) { |
| 294 | dt_add_xhci(mms); |
| 295 | continue; |
| 296 | } |
| 297 | |
| 298 | /* pcie */ |
| 299 | obj = object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST); |
| 300 | if (obj) { |
| 301 | dt_add_pcie(mms); |
| 302 | continue; |
| 303 | } |
| 304 | |
| 305 | /* isa */ |
| 306 | obj = object_dynamic_cast(OBJECT(dev), "isabus-bridge"); |
| 307 | if (obj) { |
| 308 | dt_setup_isa_bus(mms, DEVICE(obj)); |
| 309 | continue; |
| 310 | } |
| 311 | |
| 312 | if (debug) { |
| 313 | obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC); |
| 314 | if (obj) { |
| 315 | /* ioapic already added in first pass */ |
| 316 | continue; |
| 317 | } |
| 318 | fprintf(stderr, "%s: unhandled: %s\n", __func__, |
| 319 | object_get_typename(OBJECT(dev))); |
| 320 | } |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | void dt_setup_microvm(MicrovmMachineState *mms) |
| 325 | { |
| 326 | X86MachineState *x86ms = X86_MACHINE(mms); |
| 327 | MachineState *ms = MACHINE(mms); |
| 328 | int size = 0; |
| 329 | |
| 330 | ms->fdt = create_device_tree(&size); |
| 331 | |
| 332 | /* root node */ |
| 333 | qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "linux,microvm"); |
| 334 | qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); |
| 335 | qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); |
| 336 | |
| 337 | qemu_fdt_add_subnode(ms->fdt, "/chosen"); |
| 338 | dt_setup_sys_bus(mms); |
| 339 | |
| 340 | /* add to fw_cfg */ |
| 341 | if (debug) { |
| 342 | fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__); |
| 343 | } |
| 344 | fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", ms->fdt, size); |
| 345 | |
| 346 | if (debug) { |
| 347 | fprintf(stderr, "%s: writing microvm.fdt\n", __func__); |
| 348 | if (!g_file_set_contents("microvm.fdt", ms->fdt, size, NULL)) { |
| 349 | fprintf(stderr, "%s: writing microvm.fdt failed\n", __func__); |
| 350 | return; |
| 351 | } |
| 352 | int ret = system("dtc -I dtb -O dts microvm.fdt"); |
| 353 | if (ret != 0) { |
| 354 | fprintf(stderr, "%s: oops, dtc not installed?\n", __func__); |
| 355 | } |
| 356 | } |
| 357 | } |