@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 1,814 lines 58.5 KB
Raw
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "exec/target_page.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial-isa.h"
30 #include "hw/char/parallel.h"
31 #include "hw/hyperv/hv-balloon.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "hw/i386/vmport.h"
34 #include "system/cpus.h"
35 #include "hw/ide/ide-bus.h"
36 #include "hw/timer/hpet.h"
37 #include "hw/core/loader.h"
38 #include "hw/rtc/mc146818rtc.h"
39 #include "hw/intc/i8259.h"
40 #include "hw/timer/i8254.h"
41 #include "hw/input/i8042.h"
42 #include "hw/audio/pcspk.h"
43 #include "system/system.h"
44 #include "system/xen.h"
45 #include "system/reset.h"
46 #include "kvm/kvm_i386.h"
47 #include "kvm/tdx.h"
48 #include "hw/xen/xen.h"
49 #include "qobject/qlist.h"
50 #include "qemu/error-report.h"
51 #include "hw/acpi/acpi.h"
52 #include "hw/acpi/pc-hotplug.h"
53 #include "acpi-build.h"
54 #include "hw/mem/nvdimm.h"
55 #include "hw/cxl/cxl_host.h"
56 #include "hw/usb/usb.h"
57 #include "hw/i386/intel_iommu.h"
58 #include "hw/net/ne2000-isa.h"
59 #include "hw/virtio/virtio-iommu.h"
60 #include "hw/virtio/virtio-md-pci.h"
61 #include "hw/i386/kvm/xen_overlay.h"
62 #include "hw/i386/kvm/xen_evtchn.h"
63 #include "hw/i386/kvm/xen_gnttab.h"
64 #include "hw/i386/kvm/xen_xenstore.h"
65 #include "hw/mem/memory-device.h"
66 #include "hw/mem/sp-mem.h"
67 #include "e820_memory_layout.h"
68 #include "trace.h"
69 #include "sev.h"
70 #include CONFIG_DEVICES
71
72 #ifdef CONFIG_XEN_EMU
73 #include "hw/xen/xen-legacy-backend.h"
74 #include "hw/xen/xen-bus.h"
75 #endif
76
77 GlobalProperty pc_compat_11_1[] = {};
78 const size_t pc_compat_11_1_len = G_N_ELEMENTS(pc_compat_11_1);
79
80 GlobalProperty pc_compat_11_0[] = {};
81 const size_t pc_compat_11_0_len = G_N_ELEMENTS(pc_compat_11_0);
82
83 GlobalProperty pc_compat_10_2[] = {};
84 const size_t pc_compat_10_2_len = G_N_ELEMENTS(pc_compat_10_2);
85
86 GlobalProperty pc_compat_10_1[] = {
87 { "mch", "extended-tseg-mbytes", "16" },
88 { TYPE_X86_CPU, "x-migrate-error-code", "false" },
89 };
90 const size_t pc_compat_10_1_len = G_N_ELEMENTS(pc_compat_10_1);
91
92 GlobalProperty pc_compat_10_0[] = {
93 { TYPE_X86_CPU, "x-consistent-cache", "false" },
94 { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" },
95 { TYPE_X86_CPU, "x-arch-cap-always-on", "true" },
96 { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" },
97 };
98 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0);
99
100 GlobalProperty pc_compat_9_2[] = {};
101 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2);
102
103 GlobalProperty pc_compat_9_1[] = {
104 { "ICH9-LPC", "x-smi-swsmi-timer", "off" },
105 { "ICH9-LPC", "x-smi-periodic-timer", "off" },
106 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" },
107 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" },
108 };
109 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1);
110
111 GlobalProperty pc_compat_9_0[] = {
112 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" },
113 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" },
114 { TYPE_X86_CPU, "guest-phys-bits", "0" },
115 { "sev-guest", "legacy-vm-type", "on" },
116 { TYPE_X86_CPU, "legacy-multi-node", "on" },
117 };
118 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
119
120 GlobalProperty pc_compat_8_2[] = {};
121 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
122
123 GlobalProperty pc_compat_8_1[] = {};
124 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
125
126 GlobalProperty pc_compat_8_0[] = {
127 { "virtio-mem", "unplugged-inaccessible", "auto" },
128 };
129 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
130
131 GlobalProperty pc_compat_7_2[] = {
132 { "ICH9-LPC", "noreboot", "true" },
133 };
134 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
135
136 GlobalProperty pc_compat_7_1[] = {};
137 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
138
139 GlobalProperty pc_compat_7_0[] = {};
140 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
141
142 GlobalProperty pc_compat_6_2[] = {
143 { "virtio-mem", "unplugged-inaccessible", "off" },
144 };
145 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
146
147 GlobalProperty pc_compat_6_1[] = {
148 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
149 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
150 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
151 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
152 };
153 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
154
155 GlobalProperty pc_compat_6_0[] = {
156 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
157 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
158 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
159 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
160 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
161 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
162 };
163 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
164
165 GlobalProperty pc_compat_5_2[] = {
166 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
167 };
168 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
169
170 GlobalProperty pc_compat_5_1[] = {
171 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
172 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
173 };
174 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
175
176 GlobalProperty pc_compat_5_0[] = {
177 };
178 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
179
180 GlobalProperty pc_compat_4_2[] = {
181 { "mch", "smbase-smram", "off" },
182 };
183 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
184
185 GlobalProperty pc_compat_4_1[] = {};
186 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
187
188 /*
189 * @PC_FW_DATA:
190 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
191 * and other BIOS datastructures.
192 *
193 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K
194 * reported to be used at the moment, 32K should be enough for a while.
195 */
196 #define PC_FW_DATA (0x20000 + 0x8000)
197
198 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
199 {
200 GSIState *s;
201
202 s = g_new0(GSIState, 1);
203 if (kvm_ioapic_in_kernel()) {
204 kvm_pc_setup_irq_routing(pci_enabled);
205 }
206 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
207
208 return s;
209 }
210
211 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
212 unsigned size)
213 {
214 }
215
216 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
217 {
218 return 0xffffffffffffffffULL;
219 }
220
221 /* MS-DOS compatibility mode FPU exception support */
222 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
223 unsigned size)
224 {
225 if (tcg_enabled()) {
226 cpu_set_ignne();
227 }
228 }
229
230 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
231 {
232 return 0xffffffffffffffffULL;
233 }
234
235 /* PC cmos mappings */
236
237 #define REG_EQUIPMENT_BYTE 0x14
238
239 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
240 int16_t cylinders, int8_t heads, int8_t sectors)
241 {
242 mc146818rtc_set_cmos_data(s, type_ofs, 47);
243 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
244 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
245 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
246 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
247 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
248 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
249 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
250 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
251 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
252 }
253
254 /* convert boot_device letter to something recognizable by the bios */
255 static int boot_device2nibble(char boot_device)
256 {
257 switch(boot_device) {
258 case 'a':
259 case 'b':
260 return 0x01; /* floppy boot */
261 case 'c':
262 return 0x02; /* hard drive boot */
263 case 'd':
264 return 0x03; /* CD-ROM boot */
265 case 'n':
266 return 0x04; /* Network boot */
267 }
268 return 0;
269 }
270
271 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s,
272 const char *boot_device, Error **errp)
273 {
274 #define PC_MAX_BOOT_DEVICES 3
275 int nbds, bds[3] = { 0, };
276 int i;
277
278 nbds = strlen(boot_device);
279 if (nbds > PC_MAX_BOOT_DEVICES) {
280 error_setg(errp, "Too many boot devices for PC");
281 return;
282 }
283 for (i = 0; i < nbds; i++) {
284 bds[i] = boot_device2nibble(boot_device[i]);
285 if (bds[i] == 0) {
286 error_setg(errp, "Invalid boot device for PC: '%c'",
287 boot_device[i]);
288 return;
289 }
290 }
291 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
292 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk);
293 }
294
295 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
296 {
297 PCMachineState *pcms = opaque;
298 X86MachineState *x86ms = X86_MACHINE(pcms);
299
300 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp);
301 }
302
303 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
304 {
305 int val, nb;
306 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
307 FLOPPY_DRIVE_TYPE_NONE };
308
309 #ifdef CONFIG_FDC_ISA
310 /* floppy type */
311 if (floppy) {
312 for (int i = 0; i < 2; i++) {
313 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
314 }
315 }
316 #endif
317
318 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
319 cmos_get_fd_drive_type(fd_type[1]);
320 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
321
322 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
323 nb = 0;
324 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
325 nb++;
326 }
327 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
328 nb++;
329 }
330 switch (nb) {
331 case 0:
332 break;
333 case 1:
334 val |= 0x01; /* 1 drive, ready for boot */
335 break;
336 case 2:
337 val |= 0x41; /* 2 drives, ready for boot */
338 break;
339 }
340 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
341 }
342
343 typedef struct check_fdc_state {
344 ISADevice *floppy;
345 bool multiple;
346 } CheckFdcState;
347
348 static int check_fdc(Object *obj, void *opaque)
349 {
350 CheckFdcState *state = opaque;
351 Object *fdc;
352 uint32_t iobase;
353 Error *local_err = NULL;
354
355 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
356 if (!fdc) {
357 return 0;
358 }
359
360 iobase = object_property_get_uint(obj, "iobase", &local_err);
361 if (local_err || iobase != 0x3f0) {
362 error_free(local_err);
363 return 0;
364 }
365
366 if (state->floppy) {
367 state->multiple = true;
368 } else {
369 state->floppy = ISA_DEVICE(obj);
370 }
371 return 0;
372 }
373
374 static const char * const fdc_container_path[] = {
375 "unattached", "peripheral", "peripheral-anon"
376 };
377
378 /*
379 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
380 * and ACPI objects.
381 */
382 static ISADevice *pc_find_fdc0(void)
383 {
384 int i;
385 Object *container;
386 CheckFdcState state = { 0 };
387
388 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
389 container = machine_get_container(fdc_container_path[i]);
390 object_child_foreach(container, check_fdc, &state);
391 }
392
393 if (state.multiple) {
394 warn_report("multiple floppy disk controllers with "
395 "iobase=0x3f0 have been found");
396 error_printf("the one being picked for CMOS setup might not reflect "
397 "your intent");
398 }
399
400 return state.floppy;
401 }
402
403 static void pc_cmos_init_late(PCMachineState *pcms)
404 {
405 X86MachineState *x86ms = X86_MACHINE(pcms);
406 MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
407 int16_t cylinders;
408 int8_t heads, sectors;
409 int val;
410 int i, trans;
411
412 val = 0;
413 if (pcms->idebus[0] &&
414 ide_get_geometry(pcms->idebus[0], 0,
415 &cylinders, &heads, &sectors) >= 0) {
416 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
417 val |= 0xf0;
418 }
419 if (pcms->idebus[0] &&
420 ide_get_geometry(pcms->idebus[0], 1,
421 &cylinders, &heads, &sectors) >= 0) {
422 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
423 val |= 0x0f;
424 }
425 mc146818rtc_set_cmos_data(s, 0x12, val);
426
427 val = 0;
428 for (i = 0; i < 4; i++) {
429 /* NOTE: ide_get_geometry() returns the physical
430 geometry. It is always such that: 1 <= sects <= 63, 1
431 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
432 geometry can be different if a translation is done. */
433 BusState *idebus = pcms->idebus[i / 2];
434 if (idebus &&
435 ide_get_geometry(idebus, i % 2,
436 &cylinders, &heads, &sectors) >= 0) {
437 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
438 assert((trans & ~3) == 0);
439 val |= trans << (i * 2);
440 }
441 }
442 mc146818rtc_set_cmos_data(s, 0x39, val);
443
444 pc_cmos_init_floppy(s, pc_find_fdc0());
445
446 /* various important CMOS locations needed by PC/Bochs bios */
447
448 /* memory size */
449 /* base memory (first MiB) */
450 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
451 mc146818rtc_set_cmos_data(s, 0x15, val);
452 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
453 /* extended memory (next 64MiB) */
454 if (x86ms->below_4g_mem_size > 1 * MiB) {
455 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
456 } else {
457 val = 0;
458 }
459 if (val > 65535)
460 val = 65535;
461 mc146818rtc_set_cmos_data(s, 0x17, val);
462 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
463 mc146818rtc_set_cmos_data(s, 0x30, val);
464 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
465 /* memory between 16MiB and 4GiB */
466 if (x86ms->below_4g_mem_size > 16 * MiB) {
467 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
468 } else {
469 val = 0;
470 }
471 if (val > 65535)
472 val = 65535;
473 mc146818rtc_set_cmos_data(s, 0x34, val);
474 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
475 /* memory above 4GiB */
476 val = x86ms->above_4g_mem_size / 65536;
477 mc146818rtc_set_cmos_data(s, 0x5b, val);
478 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
479 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
480
481 val = 0;
482 val |= 0x02; /* FPU is there */
483 val |= 0x04; /* PS/2 mouse installed */
484 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
485 }
486
487 static void handle_a20_line_change(void *opaque, int irq, int level)
488 {
489 X86CPU *cpu = opaque;
490
491 /* XXX: send to all CPUs ? */
492 /* XXX: add logic to handle multiple A20 line sources */
493 x86_cpu_set_a20(cpu, level);
494 }
495
496 #define NE2000_NB_MAX 6
497
498 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
499 0x280, 0x380 };
500 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
501
502 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
503 {
504 static int nb_ne2k = 0;
505
506 if (nb_ne2k == NE2000_NB_MAX) {
507 error_setg(errp,
508 "maximum number of ISA NE2000 devices exceeded");
509 return false;
510 }
511 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
512 ne2000_irq[nb_ne2k], nd);
513 nb_ne2k++;
514 return true;
515 }
516
517 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
518 {
519 X86CPU *cpu = opaque;
520
521 if (level) {
522 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
523 }
524 }
525
526 static
527 void pc_machine_done(Notifier *notifier, void *data)
528 {
529 PCMachineState *pcms = container_of(notifier,
530 PCMachineState, machine_done);
531 X86MachineState *x86ms = X86_MACHINE(pcms);
532
533 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
534 &error_fatal);
535
536 if (pcms->cxl_devices_state.is_enabled) {
537 cxl_fmws_link_targets(&error_fatal);
538 }
539
540 /* set the number of CPUs */
541 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
542
543 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus,
544 &error_abort);
545
546 acpi_setup();
547 if (x86ms->fw_cfg) {
548 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type);
549 fw_cfg_add_e820(x86ms->fw_cfg);
550 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
551 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
552 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
553 }
554
555 pc_cmos_init_late(pcms);
556 }
557
558 /* setup pci memory address space mapping into system address space */
559 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
560 MemoryRegion *pci_address_space)
561 {
562 /* Set to lower priority than RAM */
563 memory_region_add_subregion_overlap(system_memory, 0x0,
564 pci_address_space, -1);
565 }
566
567 void xen_load_linux(PCMachineState *pcms)
568 {
569 int i;
570 FWCfgState *fw_cfg;
571 X86MachineState *x86ms = X86_MACHINE(pcms);
572
573 assert(MACHINE(pcms)->kernel_filename != NULL);
574
575 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, &address_space_memory);
576 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
577 rom_set_fw(fw_cfg);
578
579 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA);
580 for (i = 0; i < nb_option_roms; i++) {
581 assert(!strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
582 !strcmp(option_rom[i].name, "pvh.bin") ||
583 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
584 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
585 }
586 x86ms->fw_cfg = fw_cfg;
587 }
588
589 #define PC_ROM_MIN_VGA 0xc0000
590 #define PC_ROM_MIN_OPTION 0xc8000
591 #define PC_ROM_MAX 0xe0000
592 #define PC_ROM_ALIGN 0x800
593 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
594
595 static hwaddr pc_above_4g_end(PCMachineState *pcms)
596 {
597 X86MachineState *x86ms = X86_MACHINE(pcms);
598
599 if (pcms->sgx_epc.size != 0) {
600 return sgx_epc_above_4g_end(&pcms->sgx_epc);
601 }
602
603 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
604 }
605
606 static void pc_get_device_memory_range(PCMachineState *pcms,
607 hwaddr *base,
608 ram_addr_t *device_mem_size)
609 {
610 MachineState *machine = MACHINE(pcms);
611 ram_addr_t size;
612 hwaddr addr;
613
614 size = machine->maxram_size - machine->ram_size;
615 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
616
617 /* size device region assuming 1G page max alignment per slot */
618 size += (1 * GiB) * machine->ram_slots;
619
620 *base = addr;
621 *device_mem_size = size;
622 }
623
624 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
625 {
626 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
627 MachineState *ms = MACHINE(pcms);
628 hwaddr cxl_base;
629 ram_addr_t size;
630
631 if (pcmc->has_reserved_memory &&
632 (ms->ram_size < ms->maxram_size)) {
633 pc_get_device_memory_range(pcms, &cxl_base, &size);
634 cxl_base += size;
635 } else {
636 cxl_base = pc_above_4g_end(pcms);
637 }
638
639 return cxl_base;
640 }
641
642 static int cxl_get_fmw_end(Object *obj, void *opaque)
643 {
644 struct CXLFixedWindow *fw;
645 uint64_t *start = opaque;
646
647 if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {
648 return 0;
649 }
650 fw = CXL_FMW(obj);
651
652 *start += fw->size;
653
654 return 0;
655 }
656
657 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
658 {
659 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
660
661 /* Ordering doesn't matter so no need to build a sorted list */
662 object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end,
663 &start);
664 return start;
665 }
666
667 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
668 {
669 X86CPU *cpu = X86_CPU(first_cpu);
670 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
671 MachineState *ms = MACHINE(pcms);
672
673 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
674 /* 64-bit systems */
675 return pc_pci_hole64_start() + pci_hole64_size - 1;
676 }
677
678 /* 32-bit systems */
679 if (pcmc->broken_32bit_mem_addr_check) {
680 /* old value for compatibility reasons */
681 return ((hwaddr)1 << cpu->phys_bits) - 1;
682 }
683
684 /*
685 * 32-bit systems don't have hole64 but they might have a region for
686 * memory devices. Even if additional hotplugged memory devices might
687 * not be usable by most guest OSes, we need to still consider them for
688 * calculating the highest possible GPA so that we can properly report
689 * if someone configures them on a CPU that cannot possibly address them.
690 */
691 if (pcmc->has_reserved_memory &&
692 (ms->ram_size < ms->maxram_size)) {
693 hwaddr devmem_start;
694 ram_addr_t devmem_size;
695
696 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
697 devmem_start += devmem_size;
698 return devmem_start - 1;
699 }
700
701 /* configuration without any memory hotplug */
702 return pc_above_4g_end(pcms) - 1;
703 }
704
705 /*
706 * AMD systems with an IOMMU have an additional hole close to the
707 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
708 * on kernel version, VFIO may or may not let you DMA map those ranges.
709 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
710 * with certain memory sizes. It's also wrong to use those IOVA ranges
711 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
712 * The ranges reserved for Hyper-Transport are:
713 *
714 * FD_0000_0000h - FF_FFFF_FFFFh
715 *
716 * The ranges represent the following:
717 *
718 * Base Address Top Address Use
719 *
720 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
721 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
722 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
723 * FD_F910_0000h FD_F91F_FFFFh System Management
724 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
725 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
726 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
727 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
728 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
729 * FE_2000_0000h FF_FFFF_FFFFh Reserved
730 *
731 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
732 * Table 3: Special Address Controls (GPA) for more information.
733 */
734 #define AMD_HT_START 0xfd00000000UL
735 #define AMD_HT_END 0xffffffffffUL
736 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
737 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
738
739 void pc_memory_init(PCMachineState *pcms,
740 MemoryRegion *system_memory,
741 MemoryRegion *rom_memory,
742 uint64_t pci_hole64_size)
743 {
744 int linux_boot, i;
745 MemoryRegion *option_rom_mr;
746 MemoryRegion *ram_below_4g, *ram_above_4g;
747 FWCfgState *fw_cfg;
748 MachineState *machine = MACHINE(pcms);
749 MachineClass *mc = MACHINE_GET_CLASS(machine);
750 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
751 X86MachineState *x86ms = X86_MACHINE(pcms);
752 hwaddr maxphysaddr, maxusedaddr;
753 hwaddr cxl_base, cxl_resv_end = 0;
754 X86CPU *cpu = X86_CPU(first_cpu);
755 uint64_t res_mem_end;
756
757 assert(machine->ram_size == x86ms->below_4g_mem_size +
758 x86ms->above_4g_mem_size);
759
760 linux_boot = (machine->kernel_filename != NULL);
761
762 /*
763 * The HyperTransport range close to the 1T boundary is unique to AMD
764 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
765 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
766 * older machine types (<= 7.0) for compatibility purposes.
767 */
768 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
769 /* Bail out if max possible address does not cross HT range */
770 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
771 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
772 }
773
774 /*
775 * Advertise the HT region if address space covers the reserved
776 * region or if we relocate.
777 */
778 if (cpu->phys_bits >= 40) {
779 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
780 }
781 }
782
783 /*
784 * phys-bits is required to be appropriately configured
785 * to make sure max used GPA is reachable.
786 */
787 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
788 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
789 if (maxphysaddr < maxusedaddr) {
790 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
791 " phys-bits too low (%u)",
792 maxphysaddr, maxusedaddr, cpu->phys_bits);
793 exit(EXIT_FAILURE);
794 }
795
796 /*
797 * Split single memory region and use aliases to address portions of it,
798 * done for backwards compatibility with older qemus.
799 */
800 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
801 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
802 0, x86ms->below_4g_mem_size);
803 memory_region_add_subregion(system_memory, 0, ram_below_4g);
804 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
805 if (x86ms->above_4g_mem_size > 0) {
806 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
807 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
808 machine->ram,
809 x86ms->below_4g_mem_size,
810 x86ms->above_4g_mem_size);
811 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
812 ram_above_4g);
813 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
814 E820_RAM);
815 }
816
817 if (pcms->sgx_epc.size != 0) {
818 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
819 }
820
821 if (!pcmc->has_reserved_memory &&
822 (machine->ram_slots ||
823 (machine->maxram_size > machine->ram_size))) {
824
825 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
826 mc->name);
827 exit(EXIT_FAILURE);
828 }
829
830 /* initialize device memory address space */
831 if (pcmc->has_reserved_memory &&
832 (machine->ram_size < machine->maxram_size)) {
833 ram_addr_t device_mem_size;
834 hwaddr device_mem_base;
835
836 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
837 error_report("unsupported amount of memory slots: %"PRIu64,
838 machine->ram_slots);
839 exit(EXIT_FAILURE);
840 }
841
842 if (QEMU_ALIGN_UP(machine->maxram_size,
843 TARGET_PAGE_SIZE) != machine->maxram_size) {
844 error_report("maximum memory size must by aligned to multiple of "
845 "%d bytes", TARGET_PAGE_SIZE);
846 exit(EXIT_FAILURE);
847 }
848
849 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
850
851 if (device_mem_base + device_mem_size < device_mem_size) {
852 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
853 machine->maxram_size);
854 exit(EXIT_FAILURE);
855 }
856 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
857 }
858
859 if (pcms->cxl_devices_state.is_enabled) {
860 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
861 hwaddr cxl_size = MiB;
862
863 cxl_base = pc_get_cxl_range_start(pcms);
864 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
865 memory_region_add_subregion(system_memory, cxl_base, mr);
866 cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
867 cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr);
868 cxl_fmws_update_mmio();
869 }
870
871 /* Initialize PC system firmware */
872 pc_system_firmware_init(pcms, rom_memory);
873
874 if (!is_tdx_vm()) {
875 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
876 if (machine_require_guest_memfd(machine)) {
877 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom",
878 PC_ROM_SIZE, &error_fatal);
879 } else {
880 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
881 &error_fatal);
882 if (pcmc->pci_enabled) {
883 memory_region_set_readonly(option_rom_mr, true);
884 }
885 }
886 memory_region_add_subregion_overlap(rom_memory,
887 PC_ROM_MIN_VGA,
888 option_rom_mr,
889 1);
890 }
891
892 fw_cfg = fw_cfg_arch_create(machine,
893 x86ms->boot_cpus, x86ms->apic_id_limit);
894
895 rom_set_fw(fw_cfg);
896
897 if (pcms->cxl_devices_state.is_enabled) {
898 res_mem_end = cxl_resv_end;
899 } else if (machine->device_memory) {
900 res_mem_end = machine->device_memory->base
901 + memory_region_size(&machine->device_memory->mr);
902 } else {
903 res_mem_end = 0;
904 }
905
906 if (res_mem_end) {
907 uint64_t *val = g_malloc(sizeof(*val));
908 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
909 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
910 }
911
912 if (linux_boot) {
913 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA);
914 }
915
916 for (i = 0; i < nb_option_roms; i++) {
917 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
918 }
919 x86ms->fw_cfg = fw_cfg;
920
921 /* Init default IOAPIC address space */
922 x86ms->ioapic_as = &address_space_memory;
923
924 /* Init ACPI memory hotplug IO base address */
925 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
926 }
927
928 /*
929 * The 64bit pci hole starts after "above 4G RAM" and
930 * potentially the space reserved for memory hotplug.
931 */
932 uint64_t pc_pci_hole64_start(void)
933 {
934 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
935 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
936 MachineState *ms = MACHINE(pcms);
937 uint64_t hole64_start = 0;
938 ram_addr_t size = 0;
939
940 if (pcms->cxl_devices_state.is_enabled) {
941 hole64_start = pc_get_cxl_range_end(pcms);
942 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
943 pc_get_device_memory_range(pcms, &hole64_start, &size);
944 hole64_start += size;
945 } else {
946 hole64_start = pc_above_4g_end(pcms);
947 }
948
949 return ROUND_UP(hole64_start, 1 * GiB);
950 }
951
952 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
953 {
954 DeviceState *dev = NULL;
955
956 if (pci_bus) {
957 PCIDevice *pcidev = pci_vga_init(pci_bus);
958 dev = pcidev ? &pcidev->qdev : NULL;
959 } else if (isa_bus) {
960 ISADevice *isadev = isa_vga_init(isa_bus);
961 dev = isadev ? DEVICE(isadev) : NULL;
962 }
963
964 return dev;
965 }
966
967 static const MemoryRegionOps ioport80_io_ops = {
968 .write = ioport80_write,
969 .read = ioport80_read,
970 .endianness = DEVICE_LITTLE_ENDIAN,
971 .impl = {
972 .min_access_size = 1,
973 .max_access_size = 1,
974 },
975 };
976
977 static const MemoryRegionOps ioportF0_io_ops = {
978 .write = ioportF0_write,
979 .read = ioportF0_read,
980 .endianness = DEVICE_LITTLE_ENDIAN,
981 .impl = {
982 .min_access_size = 1,
983 .max_access_size = 1,
984 },
985 };
986
987 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
988 bool create_i8042, bool no_vmport, Error **errp)
989 {
990 int i;
991 DriveInfo *fd[MAX_FD];
992 qemu_irq *a20_line;
993 ISADevice *i8042, *port92, *vmmouse;
994
995 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
996 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
997
998 for (i = 0; i < MAX_FD; i++) {
999 fd[i] = drive_get(IF_FLOPPY, 0, i);
1000 create_fdctrl |= !!fd[i];
1001 }
1002 if (create_fdctrl) {
1003 #ifdef CONFIG_FDC_ISA
1004 ISADevice *fdc = isa_new(TYPE_ISA_FDC);
1005 if (fdc) {
1006 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1007 isa_fdc_init_drives(fdc, fd);
1008 }
1009 #endif
1010 }
1011
1012 if (!create_i8042) {
1013 if (!no_vmport) {
1014 error_setg(errp,
1015 "vmport requires the i8042 controller to be enabled");
1016 }
1017 return;
1018 }
1019
1020 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1021 if (!no_vmport) {
1022 isa_create_simple(isa_bus, TYPE_VMPORT);
1023 vmmouse = isa_try_new("vmmouse");
1024 } else {
1025 vmmouse = NULL;
1026 }
1027 if (vmmouse) {
1028 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1029 &error_abort);
1030 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1031 }
1032 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1033
1034 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1035 qdev_connect_gpio_out_named(DEVICE(i8042),
1036 I8042_A20_LINE, 0, a20_line[0]);
1037 qdev_connect_gpio_out_named(DEVICE(port92),
1038 PORT92_A20_LINE, 0, a20_line[1]);
1039 g_free(a20_line);
1040 }
1041
1042 void pc_basic_device_init(struct PCMachineState *pcms,
1043 ISABus *isa_bus, qemu_irq *gsi,
1044 ISADevice *rtc_state,
1045 bool create_fdctrl,
1046 uint32_t hpet_irqs)
1047 {
1048 int i;
1049 DeviceState *hpet = NULL;
1050 int pit_isa_irq = 0;
1051 qemu_irq pit_alt_irq = NULL;
1052 ISADevice *pit = NULL;
1053 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1054 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1055 X86MachineState *x86ms = X86_MACHINE(pcms);
1056
1057 memory_region_init_io(ioport80_io, OBJECT(pcms), &ioport80_io_ops, NULL,
1058 "ioport80", 1);
1059 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1060
1061 memory_region_init_io(ioportF0_io, OBJECT(pcms), &ioportF0_io_ops, NULL,
1062 "ioportF0", 1);
1063 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1064
1065 /*
1066 * Check if an HPET shall be created.
1067 */
1068 if (pcms->hpet_enabled) {
1069 qemu_irq rtc_irq;
1070
1071 hpet = qdev_try_new(TYPE_HPET);
1072 if (!hpet) {
1073 error_report("couldn't create HPET device");
1074 exit(1);
1075 }
1076 /*
1077 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1078 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1079 * the property, use whatever mask they specified.
1080 */
1081 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1082 HPET_INTCAP, NULL);
1083 if (!compat) {
1084 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1085 }
1086 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1087 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1088
1089 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1090 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1091 }
1092 pit_isa_irq = -1;
1093 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1094 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1095
1096 /* overwrite connection created by south bridge */
1097 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1098 }
1099
1100 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1101 "date");
1102
1103 #ifdef CONFIG_XEN_EMU
1104 if (xen_mode == XEN_EMULATE) {
1105 xen_overlay_create();
1106 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1107 xen_gnttab_create();
1108 xen_xenstore_create();
1109 if (pcms->pcibus) {
1110 pci_create_simple(pcms->pcibus, -1, "xen-platform");
1111 }
1112 xen_bus_init();
1113 }
1114 #endif
1115
1116 qemu_register_boot_set(pc_boot_set, pcms);
1117 set_boot_dev(pcms, MC146818_RTC(rtc_state),
1118 MACHINE(pcms)->boot_config.order, &error_fatal);
1119
1120 if (!xen_enabled() &&
1121 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1122 if (kvm_pit_in_kernel()) {
1123 pit = kvm_pit_init(isa_bus, 0x40);
1124 } else {
1125 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1126 }
1127 if (hpet) {
1128 /* connect PIT to output control line of the HPET */
1129 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1130 }
1131 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1132 OBJECT(pit), &error_fatal);
1133 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1134 }
1135
1136 if (pcms->vmport == ON_OFF_AUTO_AUTO) {
1137 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled)
1138 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
1139 }
1140
1141 /* Super I/O */
1142 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1143 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal);
1144
1145 pcms->machine_done.notify = pc_machine_done;
1146 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1147 }
1148
1149 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1150 {
1151 MachineClass *mc = MACHINE_CLASS(pcmc);
1152 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1153 NICInfo *nd;
1154
1155 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1156 pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1157 }
1158
1159 /* Anything remaining should be a PCI NIC */
1160 if (pci_bus) {
1161 pci_init_nic_devices(pci_bus, mc->default_nic);
1162 }
1163 }
1164
1165 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1166 {
1167 qemu_irq *i8259;
1168
1169 if (kvm_pic_in_kernel()) {
1170 i8259 = kvm_i8259_init(isa_bus);
1171 } else if (xen_enabled()) {
1172 i8259 = xen_interrupt_controller_init();
1173 } else {
1174 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1175 }
1176
1177 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1178 i8259_irqs[i] = i8259[i];
1179 }
1180
1181 g_free(i8259);
1182 }
1183
1184 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1185 Error **errp)
1186 {
1187 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1188 const MachineState *ms = MACHINE(hotplug_dev);
1189 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1190 Error *local_err = NULL;
1191
1192 /*
1193 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1194 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1195 * addition to cover this case.
1196 */
1197 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1198 error_setg(errp,
1199 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1200 return;
1201 }
1202
1203 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1204 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1205 return;
1206 }
1207
1208 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1209 if (local_err) {
1210 error_propagate(errp, local_err);
1211 return;
1212 }
1213
1214 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
1215 }
1216
1217 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1218 DeviceState *dev, Error **errp)
1219 {
1220 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1221 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1222 MachineState *ms = MACHINE(hotplug_dev);
1223 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1224
1225 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1226
1227 if (is_nvdimm) {
1228 nvdimm_plug(ms->nvdimms_state);
1229 }
1230
1231 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1232 }
1233
1234 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1235 DeviceState *dev, Error **errp)
1236 {
1237 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1238
1239 /*
1240 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1241 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1242 * addition to cover this case.
1243 */
1244 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1245 error_setg(errp,
1246 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1247 return;
1248 }
1249
1250 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1251 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1252 return;
1253 }
1254
1255 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1256 errp);
1257 }
1258
1259 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1260 DeviceState *dev, Error **errp)
1261 {
1262 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1263 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1264 Error *local_err = NULL;
1265
1266 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1267 if (local_err) {
1268 goto out;
1269 }
1270
1271 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1272 qdev_unrealize(dev);
1273 out:
1274 error_propagate(errp, local_err);
1275 }
1276
1277 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1278 DeviceState *dev, Error **errp)
1279 {
1280 /* The vmbus handler has no hotplug handler; we should never end up here. */
1281 g_assert(!dev->hotplugged);
1282 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp);
1283 }
1284
1285 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1286 DeviceState *dev, Error **errp)
1287 {
1288 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1289 }
1290
1291 static void pc_sp_mem_pre_plug(HotplugHandler *hotplug_dev,
1292 DeviceState *dev, Error **errp)
1293 {
1294 MachineState *ms = MACHINE(hotplug_dev);
1295 SpMemDevice *spm = SP_MEM(dev);
1296
1297 if (ms->numa_state && spm->node >= ms->numa_state->num_nodes) {
1298 error_setg(errp,
1299 "'node' property value %" PRIu32
1300 " exceeds the number of NUMA nodes (%d)",
1301 spm->node, ms->numa_state->num_nodes);
1302 return;
1303 }
1304 memory_device_pre_plug(MEMORY_DEVICE(dev), ms, errp);
1305 }
1306
1307 static void pc_sp_mem_plug(HotplugHandler *hotplug_dev,
1308 DeviceState *dev, Error **errp)
1309 {
1310 SpMemDevice *spm = SP_MEM(dev);
1311 MemoryDeviceClass *mdc = MEMORY_DEVICE_GET_CLASS(MEMORY_DEVICE(dev));
1312 uint64_t addr, size;
1313
1314 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1315
1316 addr = mdc->get_addr(MEMORY_DEVICE(dev));
1317 size = memory_region_size(host_memory_backend_get_memory(spm->hostmem));
1318 e820_add_entry(addr, size, E820_SOFT_RESERVED);
1319 }
1320
1321 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1322 DeviceState *dev, Error **errp)
1323 {
1324 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1325 pc_memory_pre_plug(hotplug_dev, dev, errp);
1326 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SP_MEM)) {
1327 pc_sp_mem_pre_plug(hotplug_dev, dev, errp);
1328 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1329 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1330 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1331 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1332 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1333 /* Declare the APIC range as the reserved MSI region */
1334 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1335 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1336 QList *reserved_regions = qlist_new();
1337
1338 qlist_append_str(reserved_regions, resv_prop_str);
1339 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1340
1341 g_free(resv_prop_str);
1342 }
1343
1344 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1345 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1346 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1347
1348 if (pcms->iommu) {
1349 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1350 "for x86 yet.");
1351 return;
1352 }
1353 pcms->iommu = dev;
1354 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1355 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1356 }
1357 }
1358
1359 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1360 DeviceState *dev, Error **errp)
1361 {
1362 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1363 pc_memory_plug(hotplug_dev, dev, errp);
1364 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SP_MEM)) {
1365 pc_sp_mem_plug(hotplug_dev, dev, errp);
1366 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1367 x86_cpu_plug(hotplug_dev, dev, errp);
1368 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1369 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1370 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1371 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1372 }
1373 }
1374
1375 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1376 DeviceState *dev, Error **errp)
1377 {
1378 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1379 pc_memory_unplug_request(hotplug_dev, dev, errp);
1380 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1381 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1383 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1384 errp);
1385 } else {
1386 error_setg(errp, "acpi: device unplug request for not supported device"
1387 " type: %s", object_get_typename(OBJECT(dev)));
1388 }
1389 }
1390
1391 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1392 DeviceState *dev, Error **errp)
1393 {
1394 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1395 pc_memory_unplug(hotplug_dev, dev, errp);
1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1397 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1399 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1400 } else {
1401 error_setg(errp, "acpi: device unplug for not supported device"
1402 " type: %s", object_get_typename(OBJECT(dev)));
1403 }
1404 }
1405
1406 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1407 DeviceState *dev)
1408 {
1409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1410 object_dynamic_cast(OBJECT(dev), TYPE_SP_MEM) ||
1411 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1412 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1413 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1414 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1415 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1416 return HOTPLUG_HANDLER(machine);
1417 }
1418
1419 return NULL;
1420 }
1421
1422 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1423 void *opaque, Error **errp)
1424 {
1425 PCMachineState *pcms = PC_MACHINE(obj);
1426 OnOffAuto vmport = pcms->vmport;
1427
1428 visit_type_OnOffAuto(v, name, &vmport, errp);
1429 }
1430
1431 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1432 void *opaque, Error **errp)
1433 {
1434 PCMachineState *pcms = PC_MACHINE(obj);
1435
1436 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1437 }
1438
1439 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp)
1440 {
1441 PCMachineState *pcms = PC_MACHINE(obj);
1442
1443 return pcms->fd_bootchk;
1444 }
1445
1446 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp)
1447 {
1448 PCMachineState *pcms = PC_MACHINE(obj);
1449
1450 pcms->fd_bootchk = value;
1451 }
1452
1453 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1454 {
1455 PCMachineState *pcms = PC_MACHINE(obj);
1456
1457 return pcms->smbus_enabled;
1458 }
1459
1460 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1461 {
1462 PCMachineState *pcms = PC_MACHINE(obj);
1463
1464 pcms->smbus_enabled = value;
1465 }
1466
1467 static bool pc_machine_get_sata(Object *obj, Error **errp)
1468 {
1469 PCMachineState *pcms = PC_MACHINE(obj);
1470
1471 return pcms->sata_enabled;
1472 }
1473
1474 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1475 {
1476 PCMachineState *pcms = PC_MACHINE(obj);
1477
1478 pcms->sata_enabled = value;
1479 }
1480
1481 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1482 {
1483 PCMachineState *pcms = PC_MACHINE(obj);
1484
1485 return pcms->hpet_enabled;
1486 }
1487
1488 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1489 {
1490 PCMachineState *pcms = PC_MACHINE(obj);
1491
1492 pcms->hpet_enabled = value;
1493 }
1494
1495 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1496 {
1497 PCMachineState *pcms = PC_MACHINE(obj);
1498
1499 return pcms->i8042_enabled;
1500 }
1501
1502 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1503 {
1504 PCMachineState *pcms = PC_MACHINE(obj);
1505
1506 pcms->i8042_enabled = value;
1507 }
1508
1509 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1510 {
1511 PCMachineState *pcms = PC_MACHINE(obj);
1512
1513 return pcms->default_bus_bypass_iommu;
1514 }
1515
1516 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1517 Error **errp)
1518 {
1519 PCMachineState *pcms = PC_MACHINE(obj);
1520
1521 pcms->default_bus_bypass_iommu = value;
1522 }
1523
1524 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1525 void *opaque, Error **errp)
1526 {
1527 PCMachineState *pcms = PC_MACHINE(obj);
1528 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1529
1530 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1531 }
1532
1533 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1534 void *opaque, Error **errp)
1535 {
1536 PCMachineState *pcms = PC_MACHINE(obj);
1537
1538 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1539 }
1540
1541 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1542 const char *name, void *opaque,
1543 Error **errp)
1544 {
1545 PCMachineState *pcms = PC_MACHINE(obj);
1546 uint64_t value = pcms->max_ram_below_4g;
1547
1548 visit_type_size(v, name, &value, errp);
1549 }
1550
1551 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1552 const char *name, void *opaque,
1553 Error **errp)
1554 {
1555 PCMachineState *pcms = PC_MACHINE(obj);
1556 uint64_t value;
1557
1558 if (!visit_type_size(v, name, &value, errp)) {
1559 return;
1560 }
1561 if (value > 4 * GiB) {
1562 error_setg(errp,
1563 "Machine option 'max-ram-below-4g=%"PRIu64
1564 "' expects size less than or equal to 4G", value);
1565 return;
1566 }
1567
1568 if (value < 1 * MiB) {
1569 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1570 "BIOS may not work with less than 1MiB", value);
1571 }
1572
1573 pcms->max_ram_below_4g = value;
1574 }
1575
1576 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1577 const char *name, void *opaque,
1578 Error **errp)
1579 {
1580 PCMachineState *pcms = PC_MACHINE(obj);
1581 uint64_t value = pcms->max_fw_size;
1582
1583 visit_type_size(v, name, &value, errp);
1584 }
1585
1586 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1587 const char *name, void *opaque,
1588 Error **errp)
1589 {
1590 PCMachineState *pcms = PC_MACHINE(obj);
1591 uint64_t value;
1592
1593 if (!visit_type_size(v, name, &value, errp)) {
1594 return;
1595 }
1596
1597 /*
1598 * We don't have a theoretically justifiable exact lower bound on the base
1599 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1600 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1601 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1602 * 16MiB in size.
1603 */
1604 if (value > 16 * MiB) {
1605 error_setg(errp,
1606 "User specified max allowed firmware size %" PRIu64 " is "
1607 "greater than 16MiB. If combined firmware size exceeds "
1608 "16MiB the system may not boot, or experience intermittent"
1609 "stability issues.",
1610 value);
1611 return;
1612 }
1613
1614 pcms->max_fw_size = value;
1615 }
1616
1617
1618 static void pc_machine_initfn(Object *obj)
1619 {
1620 PCMachineState *pcms = PC_MACHINE(obj);
1621 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1622
1623 #ifdef CONFIG_VMPORT
1624 pcms->vmport = ON_OFF_AUTO_AUTO;
1625 #else
1626 pcms->vmport = ON_OFF_AUTO_OFF;
1627 #endif /* CONFIG_VMPORT */
1628 pcms->max_ram_below_4g = 0; /* use default */
1629 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1630 pcms->south_bridge = pcmc->default_south_bridge;
1631
1632 /* acpi build is enabled by default if machine supports it */
1633 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1634 pcms->smbus_enabled = true;
1635 pcms->sata_enabled = true;
1636 pcms->i8042_enabled = true;
1637 pcms->max_fw_size = 8 * MiB;
1638 #if defined(CONFIG_HPET)
1639 pcms->hpet_enabled = true;
1640 #endif
1641 pcms->fd_bootchk = true;
1642 pcms->default_bus_bypass_iommu = false;
1643
1644 pc_system_flash_create(pcms);
1645 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1646 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1647 OBJECT(pcms->pcspk), "audiodev");
1648 if (pcmc->pci_enabled) {
1649 cxl_machine_init(obj, &pcms->cxl_devices_state);
1650 }
1651 }
1652
1653 static void pc_machine_finalize(Object *obj)
1654 {
1655 PCMachineState *pcms = PC_MACHINE(obj);
1656
1657 if (pcms->pcspk && !qdev_is_realized(DEVICE(pcms->pcspk))) {
1658 object_unref(OBJECT(pcms->pcspk));
1659 }
1660 }
1661
1662 static void pc_machine_reset(MachineState *machine, ResetType type)
1663 {
1664 CPUState *cs;
1665 X86CPU *cpu;
1666
1667 qemu_devices_reset(type);
1668
1669 /* Reset APIC after devices have been reset to cancel
1670 * any changes that qemu_devices_reset() might have done.
1671 */
1672 CPU_FOREACH(cs) {
1673 cpu = X86_CPU(cs);
1674
1675 x86_cpu_after_reset(cpu);
1676 }
1677 }
1678
1679 static void pc_machine_wakeup(MachineState *machine)
1680 {
1681 cpu_synchronize_all_states();
1682 pc_machine_reset(machine, RESET_TYPE_WAKEUP);
1683 cpu_synchronize_all_post_reset();
1684 }
1685
1686 static void pc_machine_class_init(ObjectClass *oc, const void *data)
1687 {
1688 MachineClass *mc = MACHINE_CLASS(oc);
1689 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1690 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1691 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1692
1693 pcmc->pci_enabled = true;
1694 pcmc->has_acpi_build = true;
1695 pcmc->smbios_defaults = true;
1696 pcmc->gigabyte_align = true;
1697 pcmc->has_reserved_memory = true;
1698 pcmc->enforce_amd_1tb_hole = true;
1699 pcmc->isa_bios_alias = true;
1700 pcmc->kvmclock_create_always = true;
1701 x86mc->apic_xrupt_override = true;
1702 assert(!mc->get_hotplug_handler);
1703 mc->get_hotplug_handler = pc_get_hotplug_handler;
1704 mc->auto_enable_numa_with_memhp = true;
1705 mc->auto_enable_numa_with_memdev = true;
1706 mc->has_hotpluggable_cpus = true;
1707 mc->default_boot_order = "cad";
1708 mc->block_default_type = IF_IDE;
1709 mc->max_cpus = 255;
1710 mc->reset = pc_machine_reset;
1711 mc->wakeup = pc_machine_wakeup;
1712 hc->pre_plug = pc_machine_device_pre_plug_cb;
1713 hc->plug = pc_machine_device_plug_cb;
1714 hc->unplug_request = pc_machine_device_unplug_request_cb;
1715 hc->unplug = pc_machine_device_unplug_cb;
1716 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1717 mc->nvdimm_supported = true;
1718 mc->smp_props.dies_supported = true;
1719 mc->smp_props.modules_supported = true;
1720 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
1721 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
1722 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
1723 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
1724 mc->default_ram_id = "pc.ram";
1725 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
1726
1727 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1728 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1729 NULL, NULL);
1730 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1731 "Maximum ram below the 4G boundary (32bit boundary)");
1732
1733 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1734 pc_machine_get_vmport, pc_machine_set_vmport,
1735 NULL, NULL);
1736 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1737 "Enable vmport (pc & q35)");
1738
1739 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1740 pc_machine_get_smbus, pc_machine_set_smbus);
1741 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1742 "Enable/disable system management bus");
1743
1744 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1745 pc_machine_get_sata, pc_machine_set_sata);
1746 object_class_property_set_description(oc, PC_MACHINE_SATA,
1747 "Enable/disable Serial ATA bus");
1748
1749 object_class_property_add_bool(oc, "hpet",
1750 pc_machine_get_hpet, pc_machine_set_hpet);
1751 object_class_property_set_description(oc, "hpet",
1752 "Enable/disable high precision event timer emulation");
1753
1754 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1755 pc_machine_get_i8042, pc_machine_set_i8042);
1756 object_class_property_set_description(oc, PC_MACHINE_I8042,
1757 "Enable/disable Intel 8042 PS/2 controller emulation");
1758
1759 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1760 pc_machine_get_default_bus_bypass_iommu,
1761 pc_machine_set_default_bus_bypass_iommu);
1762
1763 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1764 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1765 NULL, NULL);
1766 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1767 "Maximum combined firmware size");
1768
1769 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1770 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1771 NULL, NULL);
1772 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1773 "SMBIOS Entry Point type [32, 64]");
1774
1775 object_class_property_add_bool(oc, "fd-bootchk",
1776 pc_machine_get_fd_bootchk,
1777 pc_machine_set_fd_bootchk);
1778 object_class_property_set_description(oc, "fd-bootchk",
1779 "Enable/disable boot signature checking for floppy disks in BIOS");
1780
1781 #if defined(CONFIG_IGVM)
1782 object_class_property_add_link(oc, "igvm-cfg",
1783 TYPE_IGVM_CFG,
1784 offsetof(X86MachineState, igvm),
1785 object_property_allow_set_link,
1786 OBJ_PROP_LINK_STRONG);
1787 object_class_property_set_description(oc, "igvm-cfg",
1788 "Set IGVM configuration");
1789 #endif
1790
1791
1792 }
1793
1794 static const TypeInfo pc_machine_info = {
1795 .name = TYPE_PC_MACHINE,
1796 .parent = TYPE_X86_MACHINE,
1797 .abstract = true,
1798 .instance_size = sizeof(PCMachineState),
1799 .instance_init = pc_machine_initfn,
1800 .instance_finalize = pc_machine_finalize,
1801 .class_size = sizeof(PCMachineClass),
1802 .class_init = pc_machine_class_init,
1803 .interfaces = (const InterfaceInfo[]) {
1804 { TYPE_HOTPLUG_HANDLER },
1805 { }
1806 },
1807 };
1808
1809 static void pc_machine_register_types(void)
1810 {
1811 type_register_static(&pc_machine_info);
1812 }
1813
1814 type_init(pc_machine_register_types)