@samitouri / QOSamiQemu
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1 /*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/acpi/acpi.h"
34 #include "hw/char/parallel-isa.h"
35 #include "hw/core/loader.h"
36 #include "hw/i2c/smbus_eeprom.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "system/tcg.h"
39 #include "system/kvm.h"
40 #include "hw/i386/kvm/clock.h"
41 #include "hw/pci-host/q35.h"
42 #include "hw/pci/pcie_port.h"
43 #include "hw/core/qdev-properties.h"
44 #include "hw/i386/x86.h"
45 #include "hw/i386/pc.h"
46 #include "hw/i386/amd_iommu.h"
47 #include "hw/i386/intel_iommu.h"
48 #include "hw/vfio/types.h"
49 #include "hw/virtio/virtio-iommu.h"
50 #include "hw/display/ramfb.h"
51 #include "hw/ide/pci.h"
52 #include "hw/ide/ahci-pci.h"
53 #include "hw/intc/ioapic.h"
54 #include "hw/southbridge/ich9.h"
55 #include "hw/usb/usb.h"
56 #include "hw/usb/hcd-uhci.h"
57 #include "qapi/error.h"
58 #include "qemu/error-report.h"
59 #include "qom/compat-properties.h"
60 #include "system/numa.h"
61 #include "hw/hyperv/vmbus-bridge.h"
62 #include "hw/mem/nvdimm.h"
63 #include "hw/uefi/var-service-api.h"
64 #include "hw/i386/acpi-build.h"
65 #include "target/i386/cpu.h"
66
67 /* ICH9 AHCI has 6 ports */
68 #define MAX_SATA_PORTS 6
69
70 static GlobalProperty pc_q35_compat_defaults[] = {
71 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "39" },
72 { TYPE_RAMFB_DEVICE, "use-legacy-x86-rom", "true" },
73 { TYPE_VFIO_PCI_NOHOTPLUG, "use-legacy-x86-rom", "true" },
74 };
75 static const size_t pc_q35_compat_defaults_len =
76 G_N_ELEMENTS(pc_q35_compat_defaults);
77
78 struct ehci_companions {
79 const char *name;
80 int func;
81 int port;
82 };
83
84 static const struct ehci_companions ich9_1d[] = {
85 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
86 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
87 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
88 };
89
90 static const struct ehci_companions ich9_1a[] = {
91 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
92 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
93 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
94 };
95
96 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
97 {
98 const struct ehci_companions *comp;
99 PCIDevice *ehci, *uhci;
100 BusState *usbbus;
101 const char *name;
102 int i;
103
104 switch (slot) {
105 case 0x1d:
106 name = "ich9-usb-ehci1";
107 comp = ich9_1d;
108 break;
109 case 0x1a:
110 name = "ich9-usb-ehci2";
111 comp = ich9_1a;
112 break;
113 default:
114 return -1;
115 }
116
117 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name);
118 pci_realize_and_unref(ehci, bus, &error_fatal);
119 usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
120
121 for (i = 0; i < 3; i++) {
122 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func),
123 comp[i].name);
124 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
125 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
126 pci_realize_and_unref(uhci, bus, &error_fatal);
127 }
128 return 0;
129 }
130
131 /* PC hardware initialisation */
132 static void pc_q35_init(MachineState *machine)
133 {
134 PCMachineState *pcms = PC_MACHINE(machine);
135 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
136 X86MachineState *x86ms = X86_MACHINE(machine);
137 Object *phb;
138 PCIDevice *lpc;
139 DeviceState *lpc_dev;
140 MemoryRegion *system_memory = get_system_memory();
141 MemoryRegion *system_io = get_system_io();
142 MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
143 GSIState *gsi_state;
144 ISABus *isa_bus;
145 int i;
146 ram_addr_t lowmem;
147 DriveInfo *hd[MAX_SATA_PORTS];
148 MachineClass *mc = MACHINE_GET_CLASS(machine);
149 bool acpi_pcihp;
150 bool keep_pci_slot_hpc;
151 uint64_t pci_hole64_size = 0;
152
153 assert(pcmc->pci_enabled);
154
155 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
156 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
157 * also known as MMCFG).
158 * If it doesn't, we need to split it in chunks below and above 4G.
159 * In any case, try to make sure that guest addresses aligned at
160 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
161 */
162 if (machine->ram_size >= 0xb0000000) {
163 lowmem = 0x80000000;
164 } else {
165 lowmem = 0xb0000000;
166 }
167
168 /* Handle the machine opt max-ram-below-4g. It is basically doing
169 * min(qemu limit, user limit).
170 */
171 if (!pcms->max_ram_below_4g) {
172 pcms->max_ram_below_4g = 4 * GiB;
173 }
174 if (lowmem > pcms->max_ram_below_4g) {
175 lowmem = pcms->max_ram_below_4g;
176 if (machine->ram_size - lowmem > lowmem &&
177 lowmem & (1 * GiB - 1)) {
178 warn_report("There is possibly poor performance as the ram size "
179 " (0x%" PRIx64 ") is more then twice the size of"
180 " max-ram-below-4g (%"PRIu64") and"
181 " max-ram-below-4g is not a multiple of 1G.",
182 (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
183 }
184 }
185
186 if (machine->ram_size >= lowmem) {
187 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
188 x86ms->below_4g_mem_size = lowmem;
189 } else {
190 x86ms->above_4g_mem_size = 0;
191 x86ms->below_4g_mem_size = machine->ram_size;
192 }
193
194 pc_machine_init_sgx_epc(pcms);
195 x86_cpus_init(x86ms, pcmc->default_cpu_version);
196
197 if (kvm_enabled()) {
198 kvmclock_create(pcmc->kvmclock_create_always);
199 }
200
201 /* create pci host bus */
202 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
203
204 pci_hole64_size = object_property_get_uint(phb,
205 PCI_HOST_PROP_PCI_HOLE64_SIZE,
206 &error_abort);
207
208 /* allocate ram and load rom/bios */
209 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
210 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size);
211
212 object_property_add_child(OBJECT(machine), "q35", phb);
213 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
214 OBJECT(machine->ram), NULL);
215 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
216 OBJECT(pci_memory), NULL);
217 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
218 OBJECT(system_memory), NULL);
219 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
220 OBJECT(system_io), NULL);
221 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
222 x86ms->below_4g_mem_size, NULL);
223 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
224 x86ms->above_4g_mem_size, NULL);
225 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU,
226 pcms->default_bus_bypass_iommu, NULL);
227 object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES,
228 x86_machine_is_smm_enabled(x86ms), NULL);
229 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
230
231 /* pci */
232 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
233
234 /* irq lines */
235 gsi_state = pc_gsi_create(&x86ms->gsi, true);
236
237 /* create ISA bus */
238 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
239 TYPE_ICH9_LPC_DEVICE);
240 lpc_dev = DEVICE(lpc);
241 qdev_prop_set_bit(lpc_dev, "smm-enabled",
242 x86_machine_is_smm_enabled(x86ms));
243 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
244 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
245 }
246 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal);
247
248 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
249
250 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
251 TYPE_HOTPLUG_HANDLER,
252 (Object **)&x86ms->acpi_dev,
253 object_property_allow_set_link,
254 OBJ_PROP_LINK_STRONG);
255 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
256 OBJECT(lpc), &error_abort);
257
258 acpi_pcihp = object_property_get_bool(OBJECT(lpc),
259 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
260 NULL);
261
262 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
263 "x-keep-pci-slot-hpc",
264 NULL);
265
266 if (!keep_pci_slot_hpc && acpi_pcihp) {
267 object_register_sugar_prop(TYPE_PCIE_SLOT,
268 "x-do-not-expose-native-hotplug-cap",
269 "true", true);
270 }
271
272 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
273
274 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
275 pc_i8259_create(isa_bus, gsi_state->i8259_irq);
276 }
277
278 ioapic_init_gsi(gsi_state, OBJECT(phb));
279
280 if (tcg_enabled()) {
281 x86_register_ferr_irq(x86ms->gsi[13]);
282 }
283
284 /* init basic PC hardware */
285 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy,
286 0xff0104);
287
288 if (pcms->sata_enabled) {
289 PCIDevice *pdev;
290 AHCIPCIState *ich9;
291
292 /* ahci and SATA device, for q35 1 ahci controller is built-in */
293 pdev = pci_create_simple_multifunction(pcms->pcibus,
294 PCI_DEVFN(ICH9_SATA1_DEV,
295 ICH9_SATA1_FUNC),
296 "ich9-ahci");
297 ich9 = ICH9_AHCI(pdev);
298 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
299 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
300 g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
301 ide_drive_get(hd, ich9->ahci.ports);
302 ahci_ide_create_devs(&ich9->ahci, hd);
303 }
304
305 if (machine_usb(machine)) {
306 /* Should we create 6 UHCI according to ich9 spec? */
307 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d);
308 }
309
310 if (pcms->smbus_enabled) {
311 PCIDevice *smb;
312
313 /* TODO: Populate SPD eeprom data. */
314 smb = pci_create_simple_multifunction(pcms->pcibus,
315 PCI_DEVFN(ICH9_SMB_DEV,
316 ICH9_SMB_FUNC),
317 TYPE_ICH9_SMB_DEVICE);
318 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
319
320 smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
321 }
322
323 /* the rest devices to which pci devfn is automatically assigned */
324 pc_vga_init(isa_bus, pcms->pcibus);
325 pc_nic_init(pcmc, isa_bus, pcms->pcibus);
326
327 if (machine->nvdimms_state->is_enabled) {
328 nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
329 x86_nvdimm_acpi_dsmio,
330 x86ms->fw_cfg, OBJECT(pcms));
331 }
332 }
333
334 static bool pc_q35_machine_get_wdat(Object *o, Error **errp)
335 {
336 PCMachineState *pcms = PC_MACHINE(o);
337 return pcms->wdat_enabled;
338 }
339
340 static void pc_q35_machine_set_wdat(Object *o, bool value, Error **errp)
341 {
342 PCMachineState *pcms = PC_MACHINE(o);
343 pcms->wdat_enabled = value;
344 }
345
346 #define DEFINE_Q35_MACHINE(major, minor) \
347 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor);
348
349 #define DEFINE_Q35_MACHINE_AS_LATEST(major, minor) \
350 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, "q35", major, minor);
351
352 #define DEFINE_Q35_MACHINE_BUGFIX(major, minor, micro) \
353 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor, micro);
354
355 static void pc_q35_machine_options(MachineClass *m)
356 {
357 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
358 ObjectClass *oc = OBJECT_CLASS(m);
359 pcmc->pci_root_uid = 0;
360 pcmc->default_cpu_version = 1;
361
362 m->family = "pc_q35";
363 m->desc = "Standard PC (Q35 + ICH9, 2009)";
364 m->units_per_default_bus = 1;
365 m->default_machine_opts = "firmware=bios-256k.bin";
366 m->default_display = "std";
367 m->default_nic = "e1000e";
368 m->default_kernel_irqchip_split = false;
369 m->no_floppy = 1;
370 m->max_cpus = 4096;
371 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
372 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
373 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
374 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
375 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
376 machine_class_allow_dynamic_sysbus_dev(m, TYPE_UEFI_VARS_X64);
377 object_class_property_add_bool(oc, "wdat",
378 pc_q35_machine_get_wdat, pc_q35_machine_set_wdat);
379 object_class_property_set_description(oc, "wdat",
380 "Enable WDAT watchdog support. Default: off");
381
382 compat_props_add(m->compat_props,
383 pc_q35_compat_defaults, pc_q35_compat_defaults_len);
384 }
385
386 static void pc_q35_machine_11_2_options(MachineClass *m)
387 {
388 pc_q35_machine_options(m);
389 }
390
391 DEFINE_Q35_MACHINE_AS_LATEST(11, 2);
392
393 static void pc_q35_machine_11_1_options(MachineClass *m)
394 {
395 pc_q35_machine_11_2_options(m);
396 compat_props_add(m->compat_props, hw_compat_11_1, hw_compat_11_1_len);
397 compat_props_add(m->compat_props, pc_compat_11_1, pc_compat_11_1_len);
398 }
399
400 DEFINE_Q35_MACHINE(11, 1);
401
402 static void pc_q35_machine_11_0_options(MachineClass *m)
403 {
404 pc_q35_machine_11_1_options(m);
405 compat_props_add(m->compat_props, hw_compat_11_0, hw_compat_11_0_len);
406 compat_props_add(m->compat_props, pc_compat_11_0, pc_compat_11_0_len);
407 }
408
409 DEFINE_Q35_MACHINE(11, 0);
410
411 static void pc_q35_machine_10_2_options(MachineClass *m)
412 {
413 pc_q35_machine_11_0_options(m);
414 compat_props_add(m->compat_props, hw_compat_10_2, hw_compat_10_2_len);
415 compat_props_add(m->compat_props, pc_compat_10_2, pc_compat_10_2_len);
416 }
417
418 DEFINE_Q35_MACHINE(10, 2);
419
420 static void pc_q35_machine_10_1_options(MachineClass *m)
421 {
422 pc_q35_machine_10_2_options(m);
423 m->smbios_memory_device_size = 2047 * TiB;
424 compat_props_add(m->compat_props, hw_compat_10_1, hw_compat_10_1_len);
425 compat_props_add(m->compat_props, pc_compat_10_1, pc_compat_10_1_len);
426 }
427
428 DEFINE_Q35_MACHINE(10, 1);
429
430 static void pc_q35_machine_10_0_options(MachineClass *m)
431 {
432 pc_q35_machine_10_1_options(m);
433 compat_props_add(m->compat_props, hw_compat_10_0, hw_compat_10_0_len);
434 compat_props_add(m->compat_props, pc_compat_10_0, pc_compat_10_0_len);
435 }
436
437 DEFINE_Q35_MACHINE(10, 0);
438
439 static void pc_q35_machine_9_2_options(MachineClass *m)
440 {
441 pc_q35_machine_10_0_options(m);
442 compat_props_add(m->compat_props, hw_compat_9_2, hw_compat_9_2_len);
443 compat_props_add(m->compat_props, pc_compat_9_2, pc_compat_9_2_len);
444 }
445
446 DEFINE_Q35_MACHINE(9, 2);
447
448 static void pc_q35_machine_9_1_options(MachineClass *m)
449 {
450 pc_q35_machine_9_2_options(m);
451 compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len);
452 compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len);
453 }
454
455 DEFINE_Q35_MACHINE(9, 1);
456
457 static void pc_q35_machine_9_0_options(MachineClass *m)
458 {
459 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
460 pc_q35_machine_9_1_options(m);
461 m->smbios_memory_device_size = 16 * GiB;
462 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len);
463 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len);
464 pcmc->isa_bios_alias = false;
465 }
466
467 DEFINE_Q35_MACHINE(9, 0);
468
469 static void pc_q35_machine_8_2_options(MachineClass *m)
470 {
471 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
472 pc_q35_machine_9_0_options(m);
473 m->max_cpus = 1024;
474 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len);
475 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len);
476 /* For pc-q35-8.2 and 8.1, use SMBIOS 3.X by default */
477 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
478 }
479
480 DEFINE_Q35_MACHINE(8, 2);
481
482 static void pc_q35_machine_8_1_options(MachineClass *m)
483 {
484 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
485 pc_q35_machine_8_2_options(m);
486 pcmc->broken_32bit_mem_addr_check = true;
487 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len);
488 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len);
489 }
490
491 DEFINE_Q35_MACHINE(8, 1);
492
493 static void pc_q35_machine_8_0_options(MachineClass *m)
494 {
495 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
496
497 pc_q35_machine_8_1_options(m);
498 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
499 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
500
501 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */
502 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
503 m->max_cpus = 288;
504 }
505
506 DEFINE_Q35_MACHINE(8, 0);
507
508 static void pc_q35_machine_7_2_options(MachineClass *m)
509 {
510 pc_q35_machine_8_0_options(m);
511 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
512 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
513 }
514
515 DEFINE_Q35_MACHINE(7, 2);
516
517 static void pc_q35_machine_7_1_options(MachineClass *m)
518 {
519 pc_q35_machine_7_2_options(m);
520 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
521 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
522 }
523
524 DEFINE_Q35_MACHINE(7, 1);
525
526 static void pc_q35_machine_7_0_options(MachineClass *m)
527 {
528 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
529 pc_q35_machine_7_1_options(m);
530 pcmc->enforce_amd_1tb_hole = false;
531 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
532 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
533 }
534
535 DEFINE_Q35_MACHINE(7, 0);
536
537 static void pc_q35_machine_6_2_options(MachineClass *m)
538 {
539 pc_q35_machine_7_0_options(m);
540 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
541 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
542 }
543
544 DEFINE_Q35_MACHINE(6, 2);
545
546 static void pc_q35_machine_6_1_options(MachineClass *m)
547 {
548 pc_q35_machine_6_2_options(m);
549 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
550 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
551 m->smp_props.prefer_sockets = true;
552 }
553
554 DEFINE_Q35_MACHINE(6, 1);
555
556 static void pc_q35_machine_6_0_options(MachineClass *m)
557 {
558 pc_q35_machine_6_1_options(m);
559 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
560 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
561 }
562
563 DEFINE_Q35_MACHINE(6, 0);
564
565 static void pc_q35_machine_5_2_options(MachineClass *m)
566 {
567 pc_q35_machine_6_0_options(m);
568 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
569 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
570 }
571
572 DEFINE_Q35_MACHINE(5, 2);
573
574 static void pc_q35_machine_5_1_options(MachineClass *m)
575 {
576 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
577
578 pc_q35_machine_5_2_options(m);
579 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
580 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
581 pcmc->kvmclock_create_always = false;
582 pcmc->pci_root_uid = 1;
583 }
584
585 DEFINE_Q35_MACHINE(5, 1);
586
587 static void pc_q35_machine_5_0_options(MachineClass *m)
588 {
589 pc_q35_machine_5_1_options(m);
590 m->numa_mem_supported = true;
591 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
592 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
593 m->auto_enable_numa_with_memdev = false;
594 }
595
596 DEFINE_Q35_MACHINE(5, 0);
597
598 static void pc_q35_machine_4_2_options(MachineClass *m)
599 {
600 pc_q35_machine_5_0_options(m);
601 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
602 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
603 }
604
605 DEFINE_Q35_MACHINE(4, 2);
606
607 static void pc_q35_machine_4_1_options(MachineClass *m)
608 {
609 pc_q35_machine_4_2_options(m);
610 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
611 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
612 }
613
614 DEFINE_Q35_MACHINE(4, 1);