| 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 2 | |
| 3 | # x86-iommu.c |
| 4 | x86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%d index=%" PRIu32 " mask=%" PRIu32 |
| 5 | |
| 6 | # intel_iommu.c |
| 7 | vtd_inv_desc(const char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" low 0x%"PRIx64 |
| 8 | vtd_inv_desc_cc_domain(uint16_t domain) "context invalidate domain 0x%"PRIx16 |
| 9 | vtd_inv_desc_cc_global(void) "context invalidate globally" |
| 10 | vtd_inv_desc_cc_device(uint8_t bus, uint8_t dev, uint8_t fn) "context invalidate device %02"PRIx8":%02"PRIx8".%02"PRIx8 |
| 11 | vtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "context invalidate devices sid 0x%"PRIx16" fmask 0x%"PRIx16 |
| 12 | vtd_inv_desc_iotlb_global(void) "iotlb invalidate global" |
| 13 | vtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16 |
| 14 | vtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8 |
| 15 | vtd_inv_desc_iotlb_pasid_pages(uint16_t domain, uint64_t addr, uint8_t mask, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8" pasid 0x%"PRIx32 |
| 16 | vtd_inv_desc_iotlb_pasid(uint16_t domain, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" pasid 0x%"PRIx32 |
| 17 | vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32 |
| 18 | vtd_inv_desc_wait_irq(const char *msg) "%s" |
| 19 | vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64 |
| 20 | vtd_inv_desc_iec(uint32_t granularity, uint32_t index, uint32_t mask) "granularity 0x%"PRIx32" index 0x%"PRIx32" mask 0x%"PRIx32 |
| 21 | vtd_inv_qi_enable(bool enable) "enabled %d" |
| 22 | vtd_inv_qi_setup(uint64_t addr, int size) "addr 0x%"PRIx64" size %d" |
| 23 | vtd_inv_qi_head(uint16_t head) "read head %d" |
| 24 | vtd_inv_qi_tail(uint16_t head) "write tail %d" |
| 25 | vtd_inv_qi_fetch(void) "" |
| 26 | vtd_context_cache_reset(void) "" |
| 27 | vtd_pasid_cache_reset(void) "" |
| 28 | vtd_inv_desc_pasid_cache_gsi(void) "" |
| 29 | vtd_inv_desc_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation domain 0x%"PRIx16 |
| 30 | vtd_inv_desc_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 |
| 31 | vtd_pasid_cache_devsi(uint8_t bus, uint8_t dev, uint8_t fn) "Dev selective PC invalidation dev: %02"PRIx8":%02"PRIx8".%02"PRIx8 |
| 32 | vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" |
| 33 | vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present" |
| 34 | vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16 |
| 35 | vtd_iotlb_page_update(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page update sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16 |
| 36 | vtd_iotlb_cc_hit(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen) "IOTLB context hit bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32 |
| 37 | vtd_iotlb_cc_update(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen1, uint32_t gen2) "IOTLB context update bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32" -> gen %"PRIu32 |
| 38 | vtd_iotlb_reset(const char *reason) "IOTLB reset (reason: %s)" |
| 39 | vtd_fault_disabled(void) "Fault processing disabled for context entry" |
| 40 | vtd_replay_ce_valid(const char *mode, uint8_t bus, uint8_t dev, uint8_t fn, uint16_t domain, uint64_t hi, uint64_t lo) "%s: replay valid context device %02"PRIx8":%02"PRIx8".%02"PRIx8" domain 0x%"PRIx16" hi 0x%"PRIx64" lo 0x%"PRIx64 |
| 41 | vtd_replay_ce_invalid(uint8_t bus, uint8_t dev, uint8_t fn) "replay invalid context device %02"PRIx8":%02"PRIx8".%02"PRIx8 |
| 42 | vtd_page_walk_level(uint64_t addr, uint32_t level, uint64_t start, uint64_t end) "walk (base=0x%"PRIx64", level=%"PRIu32") iova range 0x%"PRIx64" - 0x%"PRIx64 |
| 43 | vtd_page_walk_one(uint16_t domain, uint64_t iova, uint64_t gpa, uint64_t mask, int perm) "domain 0x%"PRIx16" iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mask 0x%"PRIx64" perm %d" |
| 44 | vtd_page_walk_one_skip_map(uint64_t iova, uint64_t mask, uint64_t translated) "iova 0x%"PRIx64" mask 0x%"PRIx64" translated 0x%"PRIx64 |
| 45 | vtd_page_walk_one_skip_unmap(uint64_t iova, uint64_t mask) "iova 0x%"PRIx64" mask 0x%"PRIx64 |
| 46 | vtd_page_walk_skip_read(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to unable to read" |
| 47 | vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to rsrv set" |
| 48 | vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)" |
| 49 | vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 |
| 50 | vtd_translate_pt(uint16_t sid, uint64_t addr) "source id 0x%"PRIx16", iova 0x%"PRIx64 |
| 51 | vtd_pt_enable_fast_path(uint16_t sid, bool success) "sid 0x%"PRIx16" %d" |
| 52 | vtd_irq_generate(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64 |
| 53 | vtd_reg_read(uint64_t addr, uint64_t size) "addr 0x%"PRIx64" size 0x%"PRIx64 |
| 54 | vtd_reg_write(uint64_t addr, uint64_t size, uint64_t val) "addr 0x%"PRIx64" size 0x%"PRIx64" value 0x%"PRIx64 |
| 55 | vtd_reg_dmar_root(uint64_t addr, bool scalable) "addr 0x%"PRIx64" scalable %d" |
| 56 | vtd_reg_ir_root(uint64_t addr, uint32_t size) "addr 0x%"PRIx64" size 0x%"PRIx32 |
| 57 | vtd_reg_write_gcmd(uint32_t status, uint32_t val) "status 0x%"PRIx32" value 0x%"PRIx32 |
| 58 | vtd_reg_write_fectl(uint32_t value) "value 0x%"PRIx32 |
| 59 | vtd_reg_write_iectl(uint32_t value) "value 0x%"PRIx32 |
| 60 | vtd_reg_ics_clear_ip(void) "" |
| 61 | vtd_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova, uint64_t gpa, uint64_t mask) "dev %02x:%02x.%02x iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mask 0x%"PRIx64 |
| 62 | vtd_dmar_enable(bool en) "enable %d" |
| 63 | vtd_dmar_fault(uint16_t sid, int fault, uint64_t addr, bool is_write) "sid 0x%"PRIx16" fault %d addr 0x%"PRIx64" write %d" |
| 64 | vtd_ir_enable(bool en) "enable %d" |
| 65 | vtd_ir_irte_get(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64 |
| 66 | vtd_ir_remap(int index, int tri, int vec, int deliver, uint32_t dest, int dest_mode) "index %d trigger %d vector %d deliver %d dest 0x%"PRIx32" mode %d" |
| 67 | vtd_ir_remap_type(const char *type) "%s" |
| 68 | vtd_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")" |
| 69 | vtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64 |
| 70 | vtd_fsts_ppf(bool set) "FSTS PPF bit set to %d" |
| 71 | vtd_fsts_clear_ip(void) "" |
| 72 | vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64 |
| 73 | vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 |
| 74 | vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"PRIx16" index %d vec %d (should be: %d)" |
| 75 | vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x%"PRIx16" index %d trigger %d (should be: %d)" |
| 76 | vtd_reset_exit(void) "" |
| 77 | vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" |
| 78 | vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %d pasid %d ret: %d" |
| 79 | vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" |
| 80 | |
| 81 | # amd_iommu.c |
| 82 | amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32 |
| 83 | amdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t slot, uint8_t func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx16" devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 |
| 84 | amdvi_completion_wait_fail(uint64_t addr) "error: fail to write at address 0x%"PRIx64 |
| 85 | amdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, uint64_t val, uint64_t offset) "%s write addr 0x%"PRIx64", size %u, val 0x%"PRIx64", offset 0x%"PRIx64 |
| 86 | amdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, uint64_t offset) "%s read addr 0x%"PRIx64", size %u offset 0x%"PRIx64 |
| 87 | amdvi_mmio_read_invalid(int max, uint64_t addr, unsigned size) "error: addr outside region (max 0x%x): read addr 0x%" PRIx64 ", size %u" |
| 88 | amdvi_command_error(uint64_t status) "error: Executing commands with command buffer disabled 0x%"PRIx64 |
| 89 | amdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fail to access memory at 0x%"PRIx64" + 0x%"PRIx32 |
| 90 | amdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "command buffer head at 0x%"PRIx32" command buffer tail at 0x%"PRIx32" command buffer base at 0x%"PRIx64 |
| 91 | amdvi_unhandled_command(uint8_t type) "unhandled command 0x%"PRIx8 |
| 92 | amdvi_intr_inval(void) "Interrupt table invalidated" |
| 93 | amdvi_iotlb_inval(void) "IOTLB pages invalidated" |
| 94 | amdvi_prefetch_pages(void) "Pre-fetch of AMD-Vi pages requested" |
| 95 | amdvi_pages_inval(uint16_t domid) "AMD-Vi pages for domain 0x%"PRIx16 " invalidated" |
| 96 | amdvi_all_inval(void) "Invalidation of all AMD-Vi cache requested " |
| 97 | amdvi_ppr_exec(void) "Execution of PPR queue requested " |
| 98 | amdvi_devtab_inval(uint8_t bus, uint8_t slot, uint8_t func) "device table entry for devid: %02x:%02x.%x invalidated" |
| 99 | amdvi_completion_wait(uint64_t addr, uint64_t data) "completion wait requested with store address 0x%"PRIx64" and store data 0x%"PRIx64 |
| 100 | amdvi_control_status(uint64_t val) "MMIO_STATUS state 0x%"PRIx64 |
| 101 | amdvi_iotlb_reset(void) "IOTLB exceed size limit - reset " |
| 102 | amdvi_dte_get_fail(uint64_t addr, uint32_t offset) "error: failed to access Device Entry devtab 0x%"PRIx64" offset 0x%"PRIx32 |
| 103 | amdvi_invalid_dte(uint64_t addr) "PTE entry at 0x%"PRIx64" is invalid " |
| 104 | amdvi_get_pte_hwerror(uint64_t addr) "hardware error eccessing PTE at addr 0x%"PRIx64 |
| 105 | amdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PRIx8" translating addr 0x%"PRIx64 |
| 106 | amdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 |
| 107 | amdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 |
| 108 | amdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 |
| 109 | amdvi_mem_ir_write_req(uint64_t addr, uint64_t val, uint32_t size) "addr 0x%"PRIx64" data 0x%"PRIx64" size 0x%"PRIx32 |
| 110 | amdvi_mem_ir_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" data 0x%"PRIx64 |
| 111 | amdvi_ir_remap_msi_req(uint64_t addr, uint64_t data, uint8_t devid) "addr 0x%"PRIx64" data 0x%"PRIx64" devid 0x%"PRIx8 |
| 112 | amdvi_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")" |
| 113 | amdvi_err(const char *str) "%s" |
| 114 | amdvi_ir_irte(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" offset 0x%"PRIx64 |
| 115 | amdvi_ir_irte_val(uint32_t data) "data 0x%"PRIx32 |
| 116 | amdvi_ir_err(const char *str) "%s" |
| 117 | amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8 |
| 118 | amdvi_ir_target_abort(const char *str) "%s" |
| 119 | amdvi_ir_delivery_mode(const char *str) "%s" |
| 120 | amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64 |
| 121 | amdvi_generate_msi_interrupt(const char *str) "Mode: %s" |
| 122 | |
| 123 | # vmport.c |
| 124 | vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p" |
| 125 | vmport_command(unsigned char command) "command: 0x%02x" |
| 126 | |
| 127 | # x86.c |
| 128 | x86_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d" |
| 129 | x86_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d" |
| 130 | |
| 131 | # port92.c |
| 132 | port92_read(uint8_t val) "port92: read 0x%02x" |
| 133 | port92_write(uint8_t val) "port92: write 0x%02x" |
| 134 | |
| 135 | # vmmouse.c |
| 136 | vmmouse_get_status(void) "" |
| 137 | vmmouse_queue_event(int x, int y, int dz, int buttons_state) "event: x=%d y=%d dz=%d state=%d" |
| 138 | vmmouse_init(void) "" |
| 139 | vmmouse_read_id(void) "" |
| 140 | vmmouse_request_relative(void) "" |
| 141 | vmmouse_request_absolute(void) "" |
| 142 | vmmouse_disable(void) "" |
| 143 | vmmouse_data(uint32_t size) "data: size=%" PRIu32 |