| 1 | /* |
| 2 | * TPR optimization for 32-bit Windows guests (XP and Server 2003) |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Qumranet Technologies |
| 5 | * Copyright (C) 2012 Jan Kiszka, Siemens AG |
| 6 | * |
| 7 | * This work is licensed under the terms of the GNU GPL version 2, or |
| 8 | * (at your option) any later version. See the COPYING file in the |
| 9 | * top-level directory. |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | #include "qemu/module.h" |
| 14 | #include "exec/target_page.h" |
| 15 | #include "system/system.h" |
| 16 | #include "system/cpus.h" |
| 17 | #include "system/hw_accel.h" |
| 18 | #include "system/kvm.h" |
| 19 | #include "system/whpx.h" |
| 20 | #include "system/runstate.h" |
| 21 | #include "system/address-spaces.h" |
| 22 | #include "system/physmem.h" |
| 23 | #include "hw/i386/apic_internal.h" |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "hw/core/boards.h" |
| 26 | #include "exec/cpu-common.h" |
| 27 | #include "migration/vmstate.h" |
| 28 | #include "qom/object.h" |
| 29 | |
| 30 | #define VAPIC_IO_PORT 0x7e |
| 31 | |
| 32 | #define VAPIC_CPU_SHIFT 7 |
| 33 | |
| 34 | #define ROM_BLOCK_SIZE 512 |
| 35 | #define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1)) |
| 36 | |
| 37 | /* Option ROM window on PC/Q35 machines; the vapic ROM must live in here. */ |
| 38 | #define OPTION_ROM_START 0xc0000 |
| 39 | #define OPTION_ROM_END 0xe0000 |
| 40 | |
| 41 | typedef enum VAPICMode { |
| 42 | VAPIC_INACTIVE = 0, |
| 43 | VAPIC_ACTIVE = 1, |
| 44 | VAPIC_STANDBY = 2, |
| 45 | } VAPICMode; |
| 46 | |
| 47 | typedef struct VAPICHandlers { |
| 48 | uint32_t set_tpr; |
| 49 | uint32_t set_tpr_eax; |
| 50 | uint32_t get_tpr[8]; |
| 51 | uint32_t get_tpr_stack; |
| 52 | } QEMU_PACKED VAPICHandlers; |
| 53 | |
| 54 | typedef struct GuestROMState { |
| 55 | char signature[8]; |
| 56 | uint32_t vaddr; |
| 57 | uint32_t fixup_start; |
| 58 | uint32_t fixup_end; |
| 59 | uint32_t vapic_vaddr; |
| 60 | uint32_t vapic_size; |
| 61 | uint32_t vcpu_shift; |
| 62 | uint32_t real_tpr_addr; |
| 63 | VAPICHandlers up; |
| 64 | VAPICHandlers mp; |
| 65 | } QEMU_PACKED GuestROMState; |
| 66 | |
| 67 | struct VAPICROMState { |
| 68 | SysBusDevice busdev; |
| 69 | |
| 70 | MemoryRegion io; |
| 71 | MemoryRegion rom; |
| 72 | uint32_t state; |
| 73 | uint32_t rom_state_paddr; |
| 74 | uint32_t rom_state_vaddr; |
| 75 | uint32_t vapic_paddr; |
| 76 | uint32_t real_tpr_addr; |
| 77 | GuestROMState rom_state; |
| 78 | size_t rom_size; |
| 79 | bool rom_mapped_writable; |
| 80 | VMChangeStateEntry *vmsentry; |
| 81 | }; |
| 82 | |
| 83 | #define TYPE_VAPIC "kvmvapic" |
| 84 | OBJECT_DECLARE_SIMPLE_TYPE(VAPICROMState, VAPIC) |
| 85 | |
| 86 | #define TPR_INSTR_ABS_MODRM 0x1 |
| 87 | #define TPR_INSTR_MATCH_MODRM_REG 0x2 |
| 88 | |
| 89 | typedef struct TPRInstruction { |
| 90 | uint8_t opcode; |
| 91 | uint8_t modrm_reg; |
| 92 | unsigned int flags; |
| 93 | TPRAccess access; |
| 94 | size_t length; |
| 95 | off_t addr_offset; |
| 96 | } TPRInstruction; |
| 97 | |
| 98 | /* must be sorted by length, shortest first */ |
| 99 | static const TPRInstruction tpr_instr[] = { |
| 100 | { /* mov abs to eax */ |
| 101 | .opcode = 0xa1, |
| 102 | .access = TPR_ACCESS_READ, |
| 103 | .length = 5, |
| 104 | .addr_offset = 1, |
| 105 | }, |
| 106 | { /* mov eax to abs */ |
| 107 | .opcode = 0xa3, |
| 108 | .access = TPR_ACCESS_WRITE, |
| 109 | .length = 5, |
| 110 | .addr_offset = 1, |
| 111 | }, |
| 112 | { /* mov r32 to r/m32 */ |
| 113 | .opcode = 0x89, |
| 114 | .flags = TPR_INSTR_ABS_MODRM, |
| 115 | .access = TPR_ACCESS_WRITE, |
| 116 | .length = 6, |
| 117 | .addr_offset = 2, |
| 118 | }, |
| 119 | { /* mov r/m32 to r32 */ |
| 120 | .opcode = 0x8b, |
| 121 | .flags = TPR_INSTR_ABS_MODRM, |
| 122 | .access = TPR_ACCESS_READ, |
| 123 | .length = 6, |
| 124 | .addr_offset = 2, |
| 125 | }, |
| 126 | { /* push r/m32 */ |
| 127 | .opcode = 0xff, |
| 128 | .modrm_reg = 6, |
| 129 | .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, |
| 130 | .access = TPR_ACCESS_READ, |
| 131 | .length = 6, |
| 132 | .addr_offset = 2, |
| 133 | }, |
| 134 | { /* mov imm32, r/m32 (c7/0) */ |
| 135 | .opcode = 0xc7, |
| 136 | .modrm_reg = 0, |
| 137 | .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, |
| 138 | .access = TPR_ACCESS_WRITE, |
| 139 | .length = 10, |
| 140 | .addr_offset = 2, |
| 141 | }, |
| 142 | }; |
| 143 | |
| 144 | static void read_guest_rom_state(VAPICROMState *s) |
| 145 | { |
| 146 | physical_memory_read(s->rom_state_paddr, &s->rom_state, |
| 147 | sizeof(GuestROMState)); |
| 148 | } |
| 149 | |
| 150 | static void write_guest_rom_state(VAPICROMState *s) |
| 151 | { |
| 152 | physical_memory_write(s->rom_state_paddr, &s->rom_state, |
| 153 | sizeof(GuestROMState)); |
| 154 | } |
| 155 | |
| 156 | static void update_guest_rom_state(VAPICROMState *s) |
| 157 | { |
| 158 | read_guest_rom_state(s); |
| 159 | |
| 160 | s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr); |
| 161 | s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT); |
| 162 | |
| 163 | write_guest_rom_state(s); |
| 164 | } |
| 165 | |
| 166 | static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) |
| 167 | { |
| 168 | CPUState *cs = env_cpu(env); |
| 169 | target_ulong addr; |
| 170 | |
| 171 | if (s->state == VAPIC_ACTIVE) { |
| 172 | return 0; |
| 173 | } |
| 174 | /* |
| 175 | * If there is no prior TPR access instruction we could analyze (which is |
| 176 | * the case after resume from hibernation), we need to scan the possible |
| 177 | * virtual address space for the APIC mapping. |
| 178 | */ |
| 179 | for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) { |
| 180 | TranslateForDebugResult tres; |
| 181 | |
| 182 | if (!cpu_translate_for_debug(cs, addr, &tres) || |
| 183 | tres.physaddr != APIC_DEFAULT_ADDRESS) { |
| 184 | continue; |
| 185 | } |
| 186 | s->real_tpr_addr = addr + 0x80; |
| 187 | update_guest_rom_state(s); |
| 188 | return 0; |
| 189 | } |
| 190 | return -1; |
| 191 | } |
| 192 | |
| 193 | static uint8_t modrm_reg(uint8_t modrm) |
| 194 | { |
| 195 | return (modrm >> 3) & 7; |
| 196 | } |
| 197 | |
| 198 | static bool is_abs_modrm(uint8_t modrm) |
| 199 | { |
| 200 | return (modrm & 0xc7) == 0x05; |
| 201 | } |
| 202 | |
| 203 | static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr) |
| 204 | { |
| 205 | return opcode[0] == instr->opcode && |
| 206 | (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) && |
| 207 | (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) || |
| 208 | modrm_reg(opcode[1]) == instr->modrm_reg); |
| 209 | } |
| 210 | |
| 211 | static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu, |
| 212 | target_ulong *pip, TPRAccess access) |
| 213 | { |
| 214 | CPUState *cs = CPU(cpu); |
| 215 | const TPRInstruction *instr; |
| 216 | target_ulong ip = *pip; |
| 217 | uint8_t opcode[2]; |
| 218 | uint32_t real_tpr_addr; |
| 219 | int i; |
| 220 | |
| 221 | if ((ip & 0xf0000000ULL) != 0x80000000ULL && |
| 222 | (ip & 0xf0000000ULL) != 0xe0000000ULL) { |
| 223 | return -1; |
| 224 | } |
| 225 | |
| 226 | /* |
| 227 | * Early Windows 2003 SMP initialization contains a |
| 228 | * |
| 229 | * mov imm32, r/m32 |
| 230 | * |
| 231 | * instruction that is patched by TPR optimization. The problem is that |
| 232 | * RSP, used by the patched instruction, is zero, so the guest gets a |
| 233 | * double fault and dies. |
| 234 | */ |
| 235 | if (cpu->env.regs[R_ESP] == 0) { |
| 236 | return -1; |
| 237 | } |
| 238 | |
| 239 | if ((kvm_enabled() && !kvm_irqchip_in_kernel()) |
| 240 | || (whpx_enabled() && !whpx_irqchip_in_kernel())) { |
| 241 | /* |
| 242 | * KVM without kernel-based TPR access reporting will pass an IP that |
| 243 | * points after the accessing instruction. So we need to look backward |
| 244 | * to find the reason. |
| 245 | */ |
| 246 | for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { |
| 247 | instr = &tpr_instr[i]; |
| 248 | if (instr->access != access) { |
| 249 | continue; |
| 250 | } |
| 251 | if (cpu_memory_rw_debug(cs, ip - instr->length, opcode, |
| 252 | sizeof(opcode), 0) < 0) { |
| 253 | return -1; |
| 254 | } |
| 255 | if (opcode_matches(opcode, instr)) { |
| 256 | ip -= instr->length; |
| 257 | goto instruction_ok; |
| 258 | } |
| 259 | } |
| 260 | return -1; |
| 261 | } else { |
| 262 | if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { |
| 263 | return -1; |
| 264 | } |
| 265 | for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { |
| 266 | instr = &tpr_instr[i]; |
| 267 | if (opcode_matches(opcode, instr)) { |
| 268 | goto instruction_ok; |
| 269 | } |
| 270 | } |
| 271 | return -1; |
| 272 | } |
| 273 | |
| 274 | instruction_ok: |
| 275 | /* |
| 276 | * Grab the virtual TPR address from the instruction |
| 277 | * and update the cached values. |
| 278 | */ |
| 279 | if (cpu_memory_rw_debug(cs, ip + instr->addr_offset, |
| 280 | (void *)&real_tpr_addr, |
| 281 | sizeof(real_tpr_addr), 0) < 0) { |
| 282 | return -1; |
| 283 | } |
| 284 | real_tpr_addr = le32_to_cpu(real_tpr_addr); |
| 285 | if ((real_tpr_addr & 0xfff) != 0x80) { |
| 286 | return -1; |
| 287 | } |
| 288 | s->real_tpr_addr = real_tpr_addr; |
| 289 | update_guest_rom_state(s); |
| 290 | |
| 291 | *pip = ip; |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) |
| 296 | { |
| 297 | CPUState *cs = env_cpu(env); |
| 298 | hwaddr paddr; |
| 299 | uint32_t rom_state_vaddr; |
| 300 | uint32_t pos, patch, offset; |
| 301 | TranslateForDebugResult tres; |
| 302 | |
| 303 | /* nothing to do if already activated */ |
| 304 | if (s->state == VAPIC_ACTIVE) { |
| 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | /* bail out if ROM init code was not executed (missing ROM?) */ |
| 309 | if (s->state == VAPIC_INACTIVE) { |
| 310 | return -1; |
| 311 | } |
| 312 | |
| 313 | /* find out virtual address of the ROM */ |
| 314 | rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000); |
| 315 | if (!cpu_translate_for_debug(cs, rom_state_vaddr, &tres)) { |
| 316 | return -1; |
| 317 | } |
| 318 | paddr = tres.physaddr; |
| 319 | if (paddr != s->rom_state_paddr) { |
| 320 | return -1; |
| 321 | } |
| 322 | read_guest_rom_state(s); |
| 323 | if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) { |
| 324 | return -1; |
| 325 | } |
| 326 | s->rom_state_vaddr = rom_state_vaddr; |
| 327 | |
| 328 | /* fixup addresses in ROM if needed */ |
| 329 | if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) { |
| 330 | return 0; |
| 331 | } |
| 332 | for (pos = le32_to_cpu(s->rom_state.fixup_start); |
| 333 | pos < le32_to_cpu(s->rom_state.fixup_end); |
| 334 | pos += 4) { |
| 335 | physical_memory_read(paddr + pos - s->rom_state.vaddr, |
| 336 | &offset, sizeof(offset)); |
| 337 | offset = le32_to_cpu(offset); |
| 338 | physical_memory_read(paddr + offset, &patch, sizeof(patch)); |
| 339 | patch = le32_to_cpu(patch); |
| 340 | patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr); |
| 341 | patch = cpu_to_le32(patch); |
| 342 | physical_memory_write(paddr + offset, &patch, sizeof(patch)); |
| 343 | } |
| 344 | read_guest_rom_state(s); |
| 345 | s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) - |
| 346 | le32_to_cpu(s->rom_state.vaddr); |
| 347 | |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | /* |
| 352 | * Tries to read the unique processor number from the Kernel Processor Control |
| 353 | * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR |
| 354 | * cannot be accessed or is considered invalid. This also ensures that we are |
| 355 | * not patching the wrong guest. |
| 356 | */ |
| 357 | static int get_kpcr_number(X86CPU *cpu) |
| 358 | { |
| 359 | CPUX86State *env = &cpu->env; |
| 360 | struct kpcr { |
| 361 | uint8_t fill1[0x1c]; |
| 362 | uint32_t self; |
| 363 | uint8_t fill2[0x31]; |
| 364 | uint8_t number; |
| 365 | } QEMU_PACKED kpcr; |
| 366 | |
| 367 | if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base, |
| 368 | (void *)&kpcr, sizeof(kpcr), 0) < 0 || |
| 369 | kpcr.self != env->segs[R_FS].base) { |
| 370 | return -1; |
| 371 | } |
| 372 | return kpcr.number; |
| 373 | } |
| 374 | |
| 375 | static int vapic_enable(VAPICROMState *s, X86CPU *cpu) |
| 376 | { |
| 377 | int cpu_number = get_kpcr_number(cpu); |
| 378 | hwaddr vapic_paddr; |
| 379 | static const uint8_t enabled = 1; |
| 380 | |
| 381 | if (cpu_number < 0) { |
| 382 | return -1; |
| 383 | } |
| 384 | vapic_paddr = s->vapic_paddr + |
| 385 | (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT); |
| 386 | physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled), |
| 387 | &enabled, sizeof(enabled)); |
| 388 | apic_enable_vapic(cpu->apic_state, vapic_paddr); |
| 389 | |
| 390 | s->state = VAPIC_ACTIVE; |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte) |
| 396 | { |
| 397 | cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1); |
| 398 | } |
| 399 | |
| 400 | static void patch_call(X86CPU *cpu, target_ulong ip, uint32_t target) |
| 401 | { |
| 402 | uint32_t offset; |
| 403 | |
| 404 | offset = cpu_to_le32(target - ip - 5); |
| 405 | patch_byte(cpu, ip, 0xe8); /* call near */ |
| 406 | cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1); |
| 407 | } |
| 408 | |
| 409 | typedef struct PatchInfo { |
| 410 | VAPICHandlers *handler; |
| 411 | target_ulong ip; |
| 412 | } PatchInfo; |
| 413 | |
| 414 | static void do_patch_instruction(CPUState *cs, run_on_cpu_data data) |
| 415 | { |
| 416 | X86CPU *x86_cpu = X86_CPU(cs); |
| 417 | PatchInfo *info = (PatchInfo *) data.host_ptr; |
| 418 | VAPICHandlers *handlers = info->handler; |
| 419 | target_ulong ip = info->ip; |
| 420 | uint8_t opcode[2]; |
| 421 | uint32_t imm32 = 0; |
| 422 | |
| 423 | cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0); |
| 424 | |
| 425 | switch (opcode[0]) { |
| 426 | case 0x89: /* mov r32 to r/m32 */ |
| 427 | patch_byte(x86_cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */ |
| 428 | patch_call(x86_cpu, ip + 1, handlers->set_tpr); |
| 429 | break; |
| 430 | case 0x8b: /* mov r/m32 to r32 */ |
| 431 | patch_byte(x86_cpu, ip, 0x90); |
| 432 | patch_call(x86_cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]); |
| 433 | break; |
| 434 | case 0xa1: /* mov abs to eax */ |
| 435 | patch_call(x86_cpu, ip, handlers->get_tpr[0]); |
| 436 | break; |
| 437 | case 0xa3: /* mov eax to abs */ |
| 438 | patch_call(x86_cpu, ip, handlers->set_tpr_eax); |
| 439 | break; |
| 440 | case 0xc7: /* mov imm32, r/m32 (c7/0) */ |
| 441 | patch_byte(x86_cpu, ip, 0x68); /* push imm32 */ |
| 442 | cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0); |
| 443 | cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1); |
| 444 | patch_call(x86_cpu, ip + 5, handlers->set_tpr); |
| 445 | break; |
| 446 | case 0xff: /* push r/m32 */ |
| 447 | patch_byte(x86_cpu, ip, 0x50); /* push eax */ |
| 448 | patch_call(x86_cpu, ip + 1, handlers->get_tpr_stack); |
| 449 | break; |
| 450 | default: |
| 451 | abort(); |
| 452 | } |
| 453 | |
| 454 | g_free(info); |
| 455 | } |
| 456 | |
| 457 | static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) |
| 458 | { |
| 459 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 460 | CPUState *cs = CPU(cpu); |
| 461 | VAPICHandlers *handlers; |
| 462 | PatchInfo *info; |
| 463 | |
| 464 | if (ms->smp.cpus == 1) { |
| 465 | handlers = &s->rom_state.up; |
| 466 | } else { |
| 467 | handlers = &s->rom_state.mp; |
| 468 | } |
| 469 | |
| 470 | info = g_new(PatchInfo, 1); |
| 471 | info->handler = handlers; |
| 472 | info->ip = ip; |
| 473 | |
| 474 | async_safe_run_on_cpu(cs, do_patch_instruction, RUN_ON_CPU_HOST_PTR(info)); |
| 475 | } |
| 476 | |
| 477 | void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip, |
| 478 | TPRAccess access) |
| 479 | { |
| 480 | VAPICROMState *s = VAPIC(dev); |
| 481 | X86CPU *cpu = X86_CPU(cs); |
| 482 | CPUX86State *env = &cpu->env; |
| 483 | |
| 484 | cpu_synchronize_state(cs); |
| 485 | |
| 486 | if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) { |
| 487 | if (s->state == VAPIC_ACTIVE) { |
| 488 | vapic_enable(s, cpu); |
| 489 | } |
| 490 | return; |
| 491 | } |
| 492 | if (update_rom_mapping(s, env, ip) < 0) { |
| 493 | return; |
| 494 | } |
| 495 | if (vapic_enable(s, cpu) < 0) { |
| 496 | return; |
| 497 | } |
| 498 | patch_instruction(s, cpu, ip); |
| 499 | } |
| 500 | |
| 501 | typedef struct VAPICEnableTPRReporting { |
| 502 | APICCommonState *apic; |
| 503 | bool enable; |
| 504 | } VAPICEnableTPRReporting; |
| 505 | |
| 506 | static void vapic_do_enable_tpr_reporting(CPUState *cpu, run_on_cpu_data data) |
| 507 | { |
| 508 | VAPICEnableTPRReporting *info = data.host_ptr; |
| 509 | apic_enable_tpr_access_reporting(info->apic, info->enable); |
| 510 | } |
| 511 | |
| 512 | static void vapic_enable_tpr_reporting(bool enable) |
| 513 | { |
| 514 | VAPICEnableTPRReporting info = { |
| 515 | .enable = enable, |
| 516 | }; |
| 517 | CPUState *cs; |
| 518 | X86CPU *cpu; |
| 519 | |
| 520 | CPU_FOREACH(cs) { |
| 521 | cpu = X86_CPU(cs); |
| 522 | info.apic = cpu->apic_state; |
| 523 | run_on_cpu(cs, vapic_do_enable_tpr_reporting, RUN_ON_CPU_HOST_PTR(&info)); |
| 524 | } |
| 525 | } |
| 526 | |
| 527 | static void vapic_reset(DeviceState *dev) |
| 528 | { |
| 529 | VAPICROMState *s = VAPIC(dev); |
| 530 | |
| 531 | s->state = VAPIC_INACTIVE; |
| 532 | s->rom_state_paddr = 0; |
| 533 | vapic_enable_tpr_reporting(false); |
| 534 | } |
| 535 | |
| 536 | /* |
| 537 | * Set the IRQ polling hypercalls to the supported variant: |
| 538 | * - vmcall if using KVM in-kernel irqchip |
| 539 | * - 32-bit VAPIC port write otherwise |
| 540 | */ |
| 541 | static int patch_hypercalls(VAPICROMState *s) |
| 542 | { |
| 543 | hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; |
| 544 | static const uint8_t vmcall_pattern[] = { /* vmcall */ |
| 545 | 0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1 |
| 546 | }; |
| 547 | static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */ |
| 548 | 0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e |
| 549 | }; |
| 550 | uint8_t alternates[2]; |
| 551 | const uint8_t *pattern; |
| 552 | const uint8_t *patch; |
| 553 | off_t pos; |
| 554 | uint8_t *rom; |
| 555 | |
| 556 | rom = g_malloc(s->rom_size); |
| 557 | physical_memory_read(rom_paddr, rom, s->rom_size); |
| 558 | |
| 559 | for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) { |
| 560 | if (kvm_enabled() && kvm_irqchip_in_kernel()) { |
| 561 | pattern = outl_pattern; |
| 562 | alternates[0] = outl_pattern[7]; |
| 563 | alternates[1] = outl_pattern[7]; |
| 564 | patch = &vmcall_pattern[5]; |
| 565 | } else { |
| 566 | pattern = vmcall_pattern; |
| 567 | alternates[0] = vmcall_pattern[7]; |
| 568 | alternates[1] = 0xd9; /* AMD's VMMCALL */ |
| 569 | patch = &outl_pattern[5]; |
| 570 | } |
| 571 | if (memcmp(rom + pos, pattern, 7) == 0 && |
| 572 | (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) { |
| 573 | physical_memory_write(rom_paddr + pos + 5, patch, 3); |
| 574 | /* |
| 575 | * Don't flush the tb here. Under ordinary conditions, the patched |
| 576 | * calls are miles away from the current IP. Under malicious |
| 577 | * conditions, the guest could trick us to crash. |
| 578 | */ |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | g_free(rom); |
| 583 | return 0; |
| 584 | } |
| 585 | |
| 586 | /* |
| 587 | * For TCG mode or the time KVM honors read-only memory regions, we need to |
| 588 | * enable write access to the option ROM so that variables can be updated by |
| 589 | * the guest. |
| 590 | */ |
| 591 | static int vapic_map_rom_writable(VAPICROMState *s) |
| 592 | { |
| 593 | hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; |
| 594 | MemoryRegionSection section; |
| 595 | MemoryRegion *mr = get_system_memory(); |
| 596 | size_t rom_size; |
| 597 | uint8_t *ram; |
| 598 | |
| 599 | /* |
| 600 | * The VAPIC region should be mapped in place, refuse mapping it |
| 601 | * outside of the option ROM window. |
| 602 | */ |
| 603 | if (rom_paddr < OPTION_ROM_START || rom_paddr >= OPTION_ROM_END) { |
| 604 | return -1; |
| 605 | } |
| 606 | |
| 607 | if (s->rom_mapped_writable) { |
| 608 | memory_region_del_subregion(mr, &s->rom); |
| 609 | object_unparent(OBJECT(&s->rom)); |
| 610 | } |
| 611 | |
| 612 | /* grab RAM memory region (region @rom_paddr may still be pc.rom) */ |
| 613 | section = memory_region_find(mr, 0, 1); |
| 614 | |
| 615 | /* read ROM size from RAM region */ |
| 616 | if (rom_paddr + 2 >= memory_region_size(section.mr)) { |
| 617 | memory_region_unref(section.mr); |
| 618 | return -1; |
| 619 | } |
| 620 | ram = memory_region_get_ram_ptr(section.mr); |
| 621 | rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE; |
| 622 | if (rom_size == 0 || rom_size > OPTION_ROM_END - rom_paddr) { |
| 623 | memory_region_unref(section.mr); |
| 624 | return -1; |
| 625 | } |
| 626 | |
| 627 | s->rom_size = rom_size; |
| 628 | |
| 629 | /* We need to round to avoid creating subpages |
| 630 | * from which we cannot run code. */ |
| 631 | rom_size += rom_paddr & ~TARGET_PAGE_MASK; |
| 632 | rom_paddr &= TARGET_PAGE_MASK; |
| 633 | rom_size = TARGET_PAGE_ALIGN(rom_size); |
| 634 | assert(rom_paddr >= OPTION_ROM_START && rom_paddr + rom_size <= OPTION_ROM_END); |
| 635 | |
| 636 | memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr, |
| 637 | rom_paddr, rom_size); |
| 638 | memory_region_add_subregion_overlap(mr, rom_paddr, &s->rom, 1000); |
| 639 | s->rom_mapped_writable = true; |
| 640 | memory_region_unref(section.mr); |
| 641 | |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | static int vapic_prepare(VAPICROMState *s) |
| 646 | { |
| 647 | if (vapic_map_rom_writable(s) < 0) { |
| 648 | return -1; |
| 649 | } |
| 650 | |
| 651 | if (patch_hypercalls(s) < 0) { |
| 652 | return -1; |
| 653 | } |
| 654 | |
| 655 | vapic_enable_tpr_reporting(true); |
| 656 | |
| 657 | return 0; |
| 658 | } |
| 659 | |
| 660 | static void vapic_write(void *opaque, hwaddr addr, uint64_t data, |
| 661 | unsigned int size) |
| 662 | { |
| 663 | VAPICROMState *s = opaque; |
| 664 | X86CPU *cpu; |
| 665 | CPUX86State *env; |
| 666 | hwaddr rom_paddr; |
| 667 | |
| 668 | if (!current_cpu) { |
| 669 | return; |
| 670 | } |
| 671 | |
| 672 | cpu_synchronize_state(current_cpu); |
| 673 | cpu = X86_CPU(current_cpu); |
| 674 | env = &cpu->env; |
| 675 | |
| 676 | /* |
| 677 | * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. |
| 678 | * o 16-bit write access: |
| 679 | * Reports the option ROM initialization to the hypervisor. Written |
| 680 | * value is the offset of the state structure in the ROM. |
| 681 | * o 8-bit write access: |
| 682 | * Reactivates the VAPIC after a guest hibernation, i.e. after the |
| 683 | * option ROM content has been re-initialized by a guest power cycle. |
| 684 | * o 32-bit write access: |
| 685 | * Poll for pending IRQs, considering the current VAPIC state. |
| 686 | */ |
| 687 | switch (size) { |
| 688 | case 2: |
| 689 | if (s->state == VAPIC_INACTIVE) { |
| 690 | rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK; |
| 691 | s->rom_state_paddr = rom_paddr + data; |
| 692 | |
| 693 | s->state = VAPIC_STANDBY; |
| 694 | } |
| 695 | if (vapic_prepare(s) < 0) { |
| 696 | s->state = VAPIC_INACTIVE; |
| 697 | s->rom_state_paddr = 0; |
| 698 | break; |
| 699 | } |
| 700 | break; |
| 701 | case 1: |
| 702 | if (kvm_enabled() || (whpx_enabled() && !whpx_irqchip_in_kernel())) { |
| 703 | /* |
| 704 | * Disable triggering instruction in ROM by writing a NOP. |
| 705 | * |
| 706 | * We cannot do this in TCG mode as the reported IP is not |
| 707 | * accurate. |
| 708 | * |
| 709 | * Oddly enough, KVM increments EIP _before_ the execution |
| 710 | * of the instruction is finished. |
| 711 | */ |
| 712 | pause_all_vcpus(); |
| 713 | if (!kvm_enabled()) { |
| 714 | patch_byte(cpu, env->eip, 0x66); |
| 715 | patch_byte(cpu, env->eip + 1, 0x90); |
| 716 | } |
| 717 | else { |
| 718 | patch_byte(cpu, env->eip - 2, 0x66); |
| 719 | patch_byte(cpu, env->eip - 1, 0x90); |
| 720 | } |
| 721 | resume_all_vcpus(); |
| 722 | } |
| 723 | |
| 724 | if (s->state == VAPIC_ACTIVE) { |
| 725 | break; |
| 726 | } |
| 727 | if (update_rom_mapping(s, env, env->eip) < 0) { |
| 728 | break; |
| 729 | } |
| 730 | if (find_real_tpr_addr(s, env) < 0) { |
| 731 | break; |
| 732 | } |
| 733 | vapic_enable(s, cpu); |
| 734 | break; |
| 735 | default: |
| 736 | case 4: |
| 737 | if (!kvm_irqchip_in_kernel() && !whpx_irqchip_in_kernel()) { |
| 738 | apic_poll_irq(cpu->apic_state); |
| 739 | } |
| 740 | break; |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) |
| 745 | { |
| 746 | return 0xffffffff; |
| 747 | } |
| 748 | |
| 749 | static const MemoryRegionOps vapic_ops = { |
| 750 | .write = vapic_write, |
| 751 | .read = vapic_read, |
| 752 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 753 | }; |
| 754 | |
| 755 | static void vapic_realize(DeviceState *dev, Error **errp) |
| 756 | { |
| 757 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 758 | VAPICROMState *s = VAPIC(dev); |
| 759 | |
| 760 | memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2); |
| 761 | memory_region_add_subregion(get_system_io(), VAPIC_IO_PORT, &s->io); |
| 762 | sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2); |
| 763 | |
| 764 | option_rom[nb_option_roms].name = "kvmvapic.bin"; |
| 765 | option_rom[nb_option_roms].bootindex = -1; |
| 766 | nb_option_roms++; |
| 767 | } |
| 768 | |
| 769 | static void do_vapic_enable(CPUState *cs, run_on_cpu_data data) |
| 770 | { |
| 771 | VAPICROMState *s = data.host_ptr; |
| 772 | X86CPU *cpu = X86_CPU(cs); |
| 773 | |
| 774 | static const uint8_t enabled = 1; |
| 775 | physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled), |
| 776 | &enabled, sizeof(enabled)); |
| 777 | apic_enable_vapic(cpu->apic_state, s->vapic_paddr); |
| 778 | s->state = VAPIC_ACTIVE; |
| 779 | } |
| 780 | |
| 781 | static void vapic_vm_state_change(void *opaque, bool running, RunState state) |
| 782 | { |
| 783 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 784 | VAPICROMState *s = opaque; |
| 785 | uint8_t *zero; |
| 786 | |
| 787 | if (!running) { |
| 788 | return; |
| 789 | } |
| 790 | |
| 791 | if (s->state == VAPIC_ACTIVE) { |
| 792 | if (ms->smp.cpus == 1) { |
| 793 | run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s)); |
| 794 | } else { |
| 795 | zero = g_malloc0(s->rom_state.vapic_size); |
| 796 | physical_memory_write(s->vapic_paddr, zero, |
| 797 | s->rom_state.vapic_size); |
| 798 | g_free(zero); |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | qemu_del_vm_change_state_handler(s->vmsentry); |
| 803 | s->vmsentry = NULL; |
| 804 | } |
| 805 | |
| 806 | static int vapic_post_load(void *opaque, int version_id) |
| 807 | { |
| 808 | VAPICROMState *s = opaque; |
| 809 | |
| 810 | /* |
| 811 | * The old implementation of qemu-kvm did not provide the state |
| 812 | * VAPIC_STANDBY. Reconstruct it. |
| 813 | */ |
| 814 | if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) { |
| 815 | s->state = VAPIC_STANDBY; |
| 816 | } |
| 817 | |
| 818 | if (s->state != VAPIC_INACTIVE) { |
| 819 | if (vapic_prepare(s) < 0) { |
| 820 | return -1; |
| 821 | } |
| 822 | } |
| 823 | |
| 824 | if (!s->vmsentry) { |
| 825 | s->vmsentry = |
| 826 | qemu_add_vm_change_state_handler(vapic_vm_state_change, s); |
| 827 | } |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | static const VMStateDescription vmstate_handlers = { |
| 832 | .name = "kvmvapic-handlers", |
| 833 | .version_id = 1, |
| 834 | .minimum_version_id = 1, |
| 835 | .fields = (const VMStateField[]) { |
| 836 | VMSTATE_UINT32(set_tpr, VAPICHandlers), |
| 837 | VMSTATE_UINT32(set_tpr_eax, VAPICHandlers), |
| 838 | VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8), |
| 839 | VMSTATE_UINT32(get_tpr_stack, VAPICHandlers), |
| 840 | VMSTATE_END_OF_LIST() |
| 841 | } |
| 842 | }; |
| 843 | |
| 844 | static const VMStateDescription vmstate_guest_rom = { |
| 845 | .name = "kvmvapic-guest-rom", |
| 846 | .version_id = 1, |
| 847 | .minimum_version_id = 1, |
| 848 | .fields = (const VMStateField[]) { |
| 849 | VMSTATE_UNUSED(8), /* signature */ |
| 850 | VMSTATE_UINT32(vaddr, GuestROMState), |
| 851 | VMSTATE_UINT32(fixup_start, GuestROMState), |
| 852 | VMSTATE_UINT32(fixup_end, GuestROMState), |
| 853 | VMSTATE_UINT32(vapic_vaddr, GuestROMState), |
| 854 | VMSTATE_UINT32(vapic_size, GuestROMState), |
| 855 | VMSTATE_UINT32(vcpu_shift, GuestROMState), |
| 856 | VMSTATE_UINT32(real_tpr_addr, GuestROMState), |
| 857 | VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers), |
| 858 | VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers), |
| 859 | VMSTATE_END_OF_LIST() |
| 860 | } |
| 861 | }; |
| 862 | |
| 863 | static const VMStateDescription vmstate_vapic = { |
| 864 | .name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */ |
| 865 | .version_id = 1, |
| 866 | .minimum_version_id = 1, |
| 867 | .post_load = vapic_post_load, |
| 868 | .fields = (const VMStateField[]) { |
| 869 | VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom, |
| 870 | GuestROMState), |
| 871 | VMSTATE_UINT32(state, VAPICROMState), |
| 872 | VMSTATE_UINT32(real_tpr_addr, VAPICROMState), |
| 873 | VMSTATE_UINT32(rom_state_vaddr, VAPICROMState), |
| 874 | VMSTATE_UINT32(vapic_paddr, VAPICROMState), |
| 875 | VMSTATE_UINT32(rom_state_paddr, VAPICROMState), |
| 876 | VMSTATE_END_OF_LIST() |
| 877 | } |
| 878 | }; |
| 879 | |
| 880 | static void vapic_class_init(ObjectClass *klass, const void *data) |
| 881 | { |
| 882 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 883 | |
| 884 | device_class_set_legacy_reset(dc, vapic_reset); |
| 885 | dc->vmsd = &vmstate_vapic; |
| 886 | dc->realize = vapic_realize; |
| 887 | } |
| 888 | |
| 889 | static const TypeInfo vapic_type = { |
| 890 | .name = TYPE_VAPIC, |
| 891 | .parent = TYPE_SYS_BUS_DEVICE, |
| 892 | .instance_size = sizeof(VAPICROMState), |
| 893 | .class_init = vapic_class_init, |
| 894 | }; |
| 895 | |
| 896 | static void vapic_register(void) |
| 897 | { |
| 898 | type_register_static(&vapic_type); |
| 899 | } |
| 900 | |
| 901 | type_init(vapic_register); |