| 1 | /* |
| 2 | * DesignWare I3C Controller |
| 3 | * |
| 4 | * Copyright (C) 2021 ASPEED Technology Inc. |
| 5 | * Copyright (C) 2025 Google, LLC |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qemu/log.h" |
| 12 | #include "qemu/error-report.h" |
| 13 | #include "hw/i3c/i3c.h" |
| 14 | #include "hw/i3c/dw-i3c.h" |
| 15 | #include "hw/core/registerfields.h" |
| 16 | #include "hw/core/qdev-properties.h" |
| 17 | #include "qapi/error.h" |
| 18 | #include "migration/vmstate.h" |
| 19 | #include "trace.h" |
| 20 | #include "hw/core/irq.h" |
| 21 | |
| 22 | /* |
| 23 | * Disable event command values. sent along with a DISEC CCC to disable certain |
| 24 | * events on targets. |
| 25 | */ |
| 26 | #define DISEC_HJ 0x08 |
| 27 | #define DISEC_CR 0x02 |
| 28 | #define DISEC_INT 0x01 |
| 29 | |
| 30 | REG32(DEVICE_CTRL, 0x00) |
| 31 | FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) |
| 32 | FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) |
| 33 | FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) |
| 34 | FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) |
| 35 | FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) |
| 36 | FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) |
| 37 | FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) |
| 38 | FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) |
| 39 | FIELD(DEVICE_CTRL, I3C_EN, 31, 1) |
| 40 | REG32(DEVICE_ADDR, 0x04) |
| 41 | FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) |
| 42 | FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) |
| 43 | FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) |
| 44 | FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 31, 1) |
| 45 | REG32(HW_CAPABILITY, 0x08) |
| 46 | FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 3) |
| 47 | FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) |
| 48 | FIELD(HW_CAPABILITY, HDR_TS, 4, 1) |
| 49 | REG32(COMMAND_QUEUE_PORT, 0x0c) |
| 50 | FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) |
| 51 | /* Transfer command structure */ |
| 52 | FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) |
| 53 | FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) |
| 54 | FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) |
| 55 | FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) |
| 56 | FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) |
| 57 | FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) |
| 58 | FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) |
| 59 | FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) |
| 60 | FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) |
| 61 | FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) |
| 62 | /* Transfer argument data structure */ |
| 63 | FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) |
| 64 | FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) |
| 65 | /* Short data argument data structure */ |
| 66 | FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) |
| 67 | FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) |
| 68 | FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) |
| 69 | FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) |
| 70 | /* Address assignment command structure */ |
| 71 | /* |
| 72 | * bits 3..21 and 26..31 are the same as the transfer command structure, or |
| 73 | * marked as reserved. |
| 74 | */ |
| 75 | FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) |
| 76 | REG32(RESPONSE_QUEUE_PORT, 0x10) |
| 77 | FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) |
| 78 | FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) |
| 79 | FIELD(RESPONSE_QUEUE_PORT, TID, 24, 3) |
| 80 | FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) |
| 81 | REG32(RX_TX_DATA_PORT, 0x14) |
| 82 | REG32(IBI_QUEUE_STATUS, 0x18) |
| 83 | FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) |
| 84 | FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) |
| 85 | FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) |
| 86 | FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) |
| 87 | FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) |
| 88 | REG32(IBI_QUEUE_DATA, 0x18) |
| 89 | REG32(QUEUE_THLD_CTRL, 0x1c) |
| 90 | FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); |
| 91 | FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); |
| 92 | FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 5); |
| 93 | FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); |
| 94 | REG32(DATA_BUFFER_THLD_CTRL, 0x20) |
| 95 | FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) |
| 96 | FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 8, 3) |
| 97 | FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) |
| 98 | FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) |
| 99 | REG32(IBI_QUEUE_CTRL, 0x24) |
| 100 | FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) |
| 101 | FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) |
| 102 | FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) |
| 103 | REG32(IBI_MR_REQ_REJECT, 0x2c) |
| 104 | REG32(IBI_SIR_REQ_REJECT, 0x30) |
| 105 | REG32(RESET_CTRL, 0x34) |
| 106 | FIELD(RESET_CTRL, CORE_RESET, 0, 1) |
| 107 | FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) |
| 108 | FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) |
| 109 | FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) |
| 110 | FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) |
| 111 | FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) |
| 112 | REG32(SLV_EVENT_CTRL, 0x38) |
| 113 | FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) |
| 114 | FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) |
| 115 | FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) |
| 116 | FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) |
| 117 | FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) |
| 118 | FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) |
| 119 | REG32(INTR_STATUS, 0x3c) |
| 120 | FIELD(INTR_STATUS, TX_THLD, 0, 1) |
| 121 | FIELD(INTR_STATUS, RX_THLD, 1, 1) |
| 122 | FIELD(INTR_STATUS, IBI_THLD, 2, 1) |
| 123 | FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) |
| 124 | FIELD(INTR_STATUS, RESP_RDY, 4, 1) |
| 125 | FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) |
| 126 | FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) |
| 127 | FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) |
| 128 | FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) |
| 129 | FIELD(INTR_STATUS, DEFSLV, 10, 1) |
| 130 | FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) |
| 131 | FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) |
| 132 | FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) |
| 133 | REG32(INTR_STATUS_EN, 0x40) |
| 134 | FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) |
| 135 | FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) |
| 136 | FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) |
| 137 | FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) |
| 138 | FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) |
| 139 | FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) |
| 140 | FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) |
| 141 | FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) |
| 142 | FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) |
| 143 | FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) |
| 144 | FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) |
| 145 | FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) |
| 146 | FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) |
| 147 | REG32(INTR_SIGNAL_EN, 0x44) |
| 148 | FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) |
| 149 | FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) |
| 150 | FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) |
| 151 | FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) |
| 152 | FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) |
| 153 | FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) |
| 154 | FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) |
| 155 | FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) |
| 156 | FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) |
| 157 | FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) |
| 158 | FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) |
| 159 | FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) |
| 160 | FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) |
| 161 | REG32(INTR_FORCE, 0x48) |
| 162 | FIELD(INTR_FORCE, TX_THLD, 0, 1) |
| 163 | FIELD(INTR_FORCE, RX_THLD, 1, 1) |
| 164 | FIELD(INTR_FORCE, IBI_THLD, 2, 1) |
| 165 | FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) |
| 166 | FIELD(INTR_FORCE, RESP_RDY, 4, 1) |
| 167 | FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) |
| 168 | FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) |
| 169 | FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) |
| 170 | FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) |
| 171 | FIELD(INTR_FORCE, DEFSLV, 10, 1) |
| 172 | FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) |
| 173 | FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) |
| 174 | FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) |
| 175 | REG32(QUEUE_STATUS_LEVEL, 0x4c) |
| 176 | FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) |
| 177 | FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) |
| 178 | FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) |
| 179 | FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) |
| 180 | REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) |
| 181 | FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) |
| 182 | FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) |
| 183 | REG32(PRESENT_STATE, 0x54) |
| 184 | FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) |
| 185 | FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) |
| 186 | FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) |
| 187 | FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) |
| 188 | FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) |
| 189 | FIELD(PRESENT_STATE, CMD_TID, 24, 4) |
| 190 | REG32(CCC_DEVICE_STATUS, 0x58) |
| 191 | FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) |
| 192 | FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 5, 1) |
| 193 | FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) |
| 194 | FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) |
| 195 | FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) |
| 196 | FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) |
| 197 | FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) |
| 198 | FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) |
| 199 | REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) |
| 200 | FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) |
| 201 | FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) |
| 202 | REG32(DEV_CHAR_TABLE_POINTER, 0x60) |
| 203 | FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) |
| 204 | FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) |
| 205 | FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) |
| 206 | REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) |
| 207 | FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) |
| 208 | REG32(SLV_MIPI_PID_VALUE, 0x70) |
| 209 | REG32(SLV_PID_VALUE, 0x74) |
| 210 | FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) |
| 211 | FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) |
| 212 | FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) |
| 213 | REG32(SLV_CHAR_CTRL, 0x78) |
| 214 | FIELD(SLV_CHAR_CTRL, BCR, 0, 8) |
| 215 | FIELD(SLV_CHAR_CTRL, DCR, 8, 8) |
| 216 | FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) |
| 217 | REG32(SLV_MAX_LEN, 0x7c) |
| 218 | FIELD(SLV_MAX_LEN, MWL, 0, 16) |
| 219 | FIELD(SLV_MAX_LEN, MRL, 16, 16) |
| 220 | REG32(MAX_READ_TURNAROUND, 0x80) |
| 221 | REG32(MAX_DATA_SPEED, 0x84) |
| 222 | REG32(SLV_DEBUG_STATUS, 0x88) |
| 223 | REG32(SLV_INTR_REQ, 0x8c) |
| 224 | FIELD(SLV_INTR_REQ, SIR, 0, 1) |
| 225 | FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) |
| 226 | FIELD(SLV_INTR_REQ, MIR, 3, 1) |
| 227 | FIELD(SLV_INTR_REQ, TS, 4, 1) |
| 228 | FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) |
| 229 | REG32(SLV_TSX_SYMBL_TIMING, 0x90) |
| 230 | FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) |
| 231 | REG32(DEVICE_CTRL_EXTENDED, 0xb0) |
| 232 | FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) |
| 233 | FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) |
| 234 | REG32(SCL_I3C_OD_TIMING, 0xb4) |
| 235 | FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) |
| 236 | FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) |
| 237 | REG32(SCL_I3C_PP_TIMING, 0xb8) |
| 238 | FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) |
| 239 | FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) |
| 240 | REG32(SCL_I2C_FM_TIMING, 0xbc) |
| 241 | REG32(SCL_I2C_FMP_TIMING, 0xc0) |
| 242 | FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) |
| 243 | FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) |
| 244 | REG32(SCL_EXT_LCNT_TIMING, 0xc8) |
| 245 | REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) |
| 246 | REG32(BUS_FREE_TIMING, 0xd4) |
| 247 | REG32(BUS_IDLE_TIMING, 0xd8) |
| 248 | FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) |
| 249 | REG32(I3C_VER_ID, 0xe0) |
| 250 | REG32(I3C_VER_TYPE, 0xe4) |
| 251 | REG32(EXTENDED_CAPABILITY, 0xe8) |
| 252 | REG32(SLAVE_CONFIG, 0xec) |
| 253 | /* Device characteristic table fields */ |
| 254 | REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) |
| 255 | REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) |
| 256 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) |
| 257 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) |
| 258 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) |
| 259 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) |
| 260 | REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) |
| 261 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) |
| 262 | REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) |
| 263 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) |
| 264 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) |
| 265 | REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) |
| 266 | FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) |
| 267 | /* Dev addr table fields */ |
| 268 | REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) |
| 269 | FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) |
| 270 | FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) |
| 271 | FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) |
| 272 | FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) |
| 273 | FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) |
| 274 | FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) |
| 275 | FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) |
| 276 | FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) |
| 277 | FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) |
| 278 | |
| 279 | static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { |
| 280 | /* Target mode is not supported, don't advertise it for now. */ |
| 281 | [R_HW_CAPABILITY] = 0x000e00b9, |
| 282 | [R_QUEUE_THLD_CTRL] = 0x01000101, |
| 283 | [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, |
| 284 | [R_SLV_EVENT_CTRL] = 0x0000000b, |
| 285 | [R_QUEUE_STATUS_LEVEL] = 0x00000010, |
| 286 | [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000040, |
| 287 | [R_PRESENT_STATE] = 0x00000003, |
| 288 | [R_I3C_VER_ID] = 0x3130302a, |
| 289 | [R_I3C_VER_TYPE] = 0x6c633033, |
| 290 | [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, |
| 291 | [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, |
| 292 | [R_SLV_CHAR_CTRL] = 0x00010000, |
| 293 | [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, |
| 294 | [R_SLV_MAX_LEN] = 0x00ff00ff, |
| 295 | [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, |
| 296 | [R_SCL_I3C_OD_TIMING] = 0x000a0010, |
| 297 | [R_SCL_I3C_PP_TIMING] = 0x000a000a, |
| 298 | [R_SCL_I2C_FM_TIMING] = 0x00100010, |
| 299 | [R_SCL_I2C_FMP_TIMING] = 0x00100010, |
| 300 | [R_SCL_EXT_LCNT_TIMING] = 0x20202020, |
| 301 | [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, |
| 302 | [R_BUS_FREE_TIMING] = 0x00200020, |
| 303 | [R_BUS_IDLE_TIMING] = 0x00000020, |
| 304 | [R_EXTENDED_CAPABILITY] = 0x00000239, |
| 305 | [R_SLAVE_CONFIG] = 0x00000023, |
| 306 | }; |
| 307 | |
| 308 | static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { |
| 309 | [R_DEVICE_CTRL] = 0x04fffe00, |
| 310 | [R_DEVICE_ADDR] = 0x7f807f80, |
| 311 | [R_HW_CAPABILITY] = 0xffffffff, |
| 312 | [R_IBI_QUEUE_STATUS] = 0xffffffff, |
| 313 | [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, |
| 314 | [R_IBI_QUEUE_CTRL] = 0xfffffff0, |
| 315 | [R_RESET_CTRL] = 0xffffffc0, |
| 316 | [R_SLV_EVENT_CTRL] = 0xffffff3f, |
| 317 | [R_INTR_STATUS] = 0xffff809f, |
| 318 | [R_INTR_STATUS_EN] = 0xffff8080, |
| 319 | [R_INTR_SIGNAL_EN] = 0xffff8080, |
| 320 | [R_INTR_FORCE] = 0xffff8000, |
| 321 | [R_QUEUE_STATUS_LEVEL] = 0xffffffff, |
| 322 | [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, |
| 323 | [R_PRESENT_STATE] = 0xffffffff, |
| 324 | [R_CCC_DEVICE_STATUS] = 0xffffffff, |
| 325 | [R_I3C_VER_ID] = 0xffffffff, |
| 326 | [R_I3C_VER_TYPE] = 0xffffffff, |
| 327 | [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, |
| 328 | [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, |
| 329 | [R_SLV_PID_VALUE] = 0xffff0fff, |
| 330 | [R_SLV_CHAR_CTRL] = 0xffffffff, |
| 331 | [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, |
| 332 | [R_SLV_MAX_LEN] = 0xffffffff, |
| 333 | [R_MAX_READ_TURNAROUND] = 0xffffffff, |
| 334 | [R_MAX_DATA_SPEED] = 0xffffffff, |
| 335 | [R_SLV_INTR_REQ] = 0xfffffff0, |
| 336 | [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, |
| 337 | [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, |
| 338 | [R_SCL_I3C_OD_TIMING] = 0xff00ff00, |
| 339 | [R_SCL_I3C_PP_TIMING] = 0xff00ff00, |
| 340 | [R_SCL_I2C_FMP_TIMING] = 0xff000000, |
| 341 | [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, |
| 342 | [R_BUS_IDLE_TIMING] = 0xfff00000, |
| 343 | [R_EXTENDED_CAPABILITY] = 0xffffffff, |
| 344 | [R_SLAVE_CONFIG] = 0xffffffff, |
| 345 | }; |
| 346 | |
| 347 | static void dw_i3c_cmd_queue_execute(DWI3C *s); |
| 348 | |
| 349 | static inline bool dw_i3c_has_hdr_ts(DWI3C *s) |
| 350 | { |
| 351 | return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); |
| 352 | } |
| 353 | |
| 354 | static inline bool dw_i3c_has_hdr_ddr(DWI3C *s) |
| 355 | { |
| 356 | return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR); |
| 357 | } |
| 358 | |
| 359 | static inline bool dw_i3c_can_transmit(DWI3C *s) |
| 360 | { |
| 361 | /* |
| 362 | * We can only transmit if we're enabled and the resume bit is cleared. |
| 363 | * The resume bit is set on a transaction error, and software must clear it. |
| 364 | */ |
| 365 | return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) && |
| 366 | !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); |
| 367 | } |
| 368 | |
| 369 | static inline uint8_t dw_i3c_ibi_slice_size(DWI3C *s) |
| 370 | { |
| 371 | uint8_t ibi_slice_size = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 372 | IBI_DATA_THLD); |
| 373 | /* The minimum supported slice size is 4 bytes. */ |
| 374 | if (ibi_slice_size == 0) { |
| 375 | ibi_slice_size = 1; |
| 376 | } |
| 377 | ibi_slice_size *= sizeof(uint32_t); |
| 378 | /* maximum supported size is 63 bytes. */ |
| 379 | if (ibi_slice_size >= 64) { |
| 380 | ibi_slice_size = 63; |
| 381 | } |
| 382 | |
| 383 | return ibi_slice_size; |
| 384 | } |
| 385 | |
| 386 | static inline uint8_t dw_i3c_fifo_threshold_from_reg(uint8_t regval) |
| 387 | { |
| 388 | return regval = regval ? (2 << regval) : 1; |
| 389 | } |
| 390 | |
| 391 | static void dw_i3c_update_irq(DWI3C *s) |
| 392 | { |
| 393 | bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); |
| 394 | qemu_set_irq(s->irq, level); |
| 395 | } |
| 396 | |
| 397 | static void dw_i3c_end_transfer(DWI3C *s, bool is_i2c) |
| 398 | { |
| 399 | if (is_i2c) { |
| 400 | legacy_i2c_end_transfer(s->bus); |
| 401 | } else { |
| 402 | i3c_end_transfer(s->bus); |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | static int dw_i3c_send_start(DWI3C *s, uint8_t addr, bool is_recv, bool is_i2c) |
| 407 | { |
| 408 | int ret; |
| 409 | |
| 410 | if (is_i2c) { |
| 411 | ret = legacy_i2c_start_transfer(s->bus, addr, is_recv); |
| 412 | } else { |
| 413 | ret = i3c_start_transfer(s->bus, addr, is_recv); |
| 414 | } |
| 415 | if (ret) { |
| 416 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 417 | qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed on TX with addr 0x%.2x\n", |
| 418 | path, addr); |
| 419 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 420 | DW_I3C_TRANSFER_STATE_HALT); |
| 421 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 422 | DW_I3C_TRANSFER_STATUS_HALT); |
| 423 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); |
| 424 | ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); |
| 425 | } |
| 426 | |
| 427 | return ret; |
| 428 | } |
| 429 | |
| 430 | static int dw_i3c_send(DWI3C *s, const uint8_t *data, uint32_t num_to_send, |
| 431 | uint32_t *num_sent, bool is_i2c) |
| 432 | { |
| 433 | int ret; |
| 434 | uint32_t i; |
| 435 | |
| 436 | *num_sent = 0; |
| 437 | if (is_i2c) { |
| 438 | /* Legacy I2C must be byte-by-byte. */ |
| 439 | for (i = 0; i < num_to_send; i++) { |
| 440 | ret = legacy_i2c_send(s->bus, data[i]); |
| 441 | if (ret) { |
| 442 | break; |
| 443 | } |
| 444 | (*num_sent)++; |
| 445 | } |
| 446 | } else { |
| 447 | ret = i3c_send(s->bus, data, num_to_send, num_sent); |
| 448 | } |
| 449 | if (ret) { |
| 450 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 451 | qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed sending byte 0x%.2x\n", |
| 452 | path, data[*num_sent]); |
| 453 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 454 | DW_I3C_TRANSFER_STATE_HALT); |
| 455 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 456 | DW_I3C_TRANSFER_STATUS_HALT); |
| 457 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); |
| 458 | ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); |
| 459 | } |
| 460 | |
| 461 | trace_dw_i3c_send(s->cfg.id, *num_sent); |
| 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
| 466 | static int dw_i3c_send_byte(DWI3C *s, uint8_t byte, bool is_i2c) |
| 467 | { |
| 468 | /* |
| 469 | * Ignored, the caller will know if we sent 0 or 1 bytes depending on if |
| 470 | * we were ACKed/NACKed. |
| 471 | */ |
| 472 | uint32_t num_sent; |
| 473 | return dw_i3c_send(s, &byte, 1, &num_sent, is_i2c); |
| 474 | } |
| 475 | |
| 476 | static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data, |
| 477 | uint16_t num_to_read, uint32_t *num_read) |
| 478 | { |
| 479 | int ret; |
| 480 | |
| 481 | if (is_i2c) { |
| 482 | for (uint16_t i = 0; i < num_to_read; i++) { |
| 483 | data[i] = legacy_i2c_recv(s->bus); |
| 484 | } |
| 485 | /* I2C devices can neither NACK a read, nor end transfers early. */ |
| 486 | *num_read = num_to_read; |
| 487 | trace_dw_i3c_recv_data(s->cfg.id, *num_read); |
| 488 | return 0; |
| 489 | } |
| 490 | /* I3C devices can NACK if the controller sends an unsupported CCC. */ |
| 491 | ret = i3c_recv(s->bus, data, num_to_read, num_read); |
| 492 | if (ret) { |
| 493 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 494 | qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed receiving byte\n", |
| 495 | path); |
| 496 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 497 | DW_I3C_TRANSFER_STATE_HALT); |
| 498 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 499 | DW_I3C_TRANSFER_STATUS_HALT); |
| 500 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); |
| 501 | ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); |
| 502 | } |
| 503 | |
| 504 | trace_dw_i3c_recv_data(s->cfg.id, *num_read); |
| 505 | |
| 506 | return ret; |
| 507 | } |
| 508 | |
| 509 | static void dw_i3c_ctrl_w(DWI3C *s, uint32_t val) |
| 510 | { |
| 511 | /* |
| 512 | * If the user is setting I3C_RESUME, the controller was halted. |
| 513 | * Try and resume execution and leave the bit cleared. |
| 514 | */ |
| 515 | if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) { |
| 516 | dw_i3c_cmd_queue_execute(s); |
| 517 | val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0); |
| 518 | } |
| 519 | /* |
| 520 | * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is |
| 521 | * sent. |
| 522 | */ |
| 523 | if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) { |
| 524 | dw_i3c_end_transfer(s, /*is_i2c=*/true); |
| 525 | dw_i3c_end_transfer(s, /*is_i2c=*/false); |
| 526 | val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0); |
| 527 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1); |
| 528 | dw_i3c_update_irq(s); |
| 529 | } |
| 530 | /* Update present state. */ |
| 531 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 532 | DW_I3C_TRANSFER_STATE_IDLE); |
| 533 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 534 | DW_I3C_TRANSFER_STATUS_IDLE); |
| 535 | |
| 536 | s->regs[R_DEVICE_CTRL] = val; |
| 537 | } |
| 538 | |
| 539 | static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset) |
| 540 | { |
| 541 | /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ |
| 542 | uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, |
| 543 | ADDR) / sizeof(uint32_t)) + offset; |
| 544 | return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, |
| 545 | LEGACY_I2C_DEVICE); |
| 546 | } |
| 547 | |
| 548 | static uint8_t dw_i3c_target_addr(DWI3C *s, uint16_t offset) |
| 549 | { |
| 550 | if (offset > s->cfg.num_addressable_devices) { |
| 551 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 552 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Device addr table offset %d out of " |
| 553 | "bounds\n", path, offset); |
| 554 | /* If we're out of bounds, return an address of 0. */ |
| 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ |
| 559 | uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, |
| 560 | ADDR) / sizeof(uint32_t)) + offset; |
| 561 | /* I2C devices use a static address. */ |
| 562 | if (dw_i3c_target_is_i2c(s, offset)) { |
| 563 | return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, |
| 564 | DEV_STATIC_ADDR); |
| 565 | } |
| 566 | return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, |
| 567 | DEV_DYNAMIC_ADDR); |
| 568 | } |
| 569 | |
| 570 | static int dw_i3c_addr_table_index_from_addr(DWI3C *s, uint8_t addr) |
| 571 | { |
| 572 | uint8_t table_size = ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, |
| 573 | DEPTH); |
| 574 | for (uint8_t i = 0; i < table_size; i++) { |
| 575 | if (dw_i3c_target_addr(s, i) == addr) { |
| 576 | return i; |
| 577 | } |
| 578 | } |
| 579 | return -1; |
| 580 | } |
| 581 | |
| 582 | static void dw_i3c_send_disec(DWI3C *s) |
| 583 | { |
| 584 | uint8_t ccc = I3C_CCC_DISEC; |
| 585 | if (s->ibi_data.send_direct_disec) { |
| 586 | ccc = I3C_CCCD_DISEC; |
| 587 | } |
| 588 | |
| 589 | dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, |
| 590 | /*is_i2c=*/false); |
| 591 | dw_i3c_send_byte(s, ccc, /*is_i2c=*/false); |
| 592 | if (s->ibi_data.send_direct_disec) { |
| 593 | dw_i3c_send_start(s, s->ibi_data.disec_addr, |
| 594 | /*is_recv=*/false, /*is_i2c=*/false); |
| 595 | } |
| 596 | dw_i3c_send_byte(s, s->ibi_data.disec_byte, /*is_i2c=*/false); |
| 597 | } |
| 598 | |
| 599 | static int dw_i3c_handle_hj(DWI3C *s) |
| 600 | { |
| 601 | if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN)) { |
| 602 | s->ibi_data.notify_ibi_nack = true; |
| 603 | } |
| 604 | |
| 605 | bool nack_and_disable = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, |
| 606 | HOT_JOIN_ACK_NACK_CTRL); |
| 607 | if (nack_and_disable) { |
| 608 | s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, |
| 609 | IBI_QUEUE_STATUS, |
| 610 | IBI_STATUS, 1); |
| 611 | s->ibi_data.ibi_nacked = true; |
| 612 | s->ibi_data.disec_byte = DISEC_HJ; |
| 613 | return -1; |
| 614 | } |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | static int dw_i3c_handle_ctlr_req(DWI3C *s, uint8_t addr) |
| 619 | { |
| 620 | if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ)) { |
| 621 | s->ibi_data.notify_ibi_nack = true; |
| 622 | } |
| 623 | |
| 624 | int table_offset = dw_i3c_addr_table_index_from_addr(s, addr); |
| 625 | /* Doesn't exist in the table, NACK it, don't DISEC. */ |
| 626 | if (table_offset < 0) { |
| 627 | return -1; |
| 628 | } |
| 629 | |
| 630 | /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ |
| 631 | table_offset += (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, |
| 632 | ADDR) / sizeof(uint32_t)); |
| 633 | if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, MR_REJECT)) { |
| 634 | s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, |
| 635 | IBI_QUEUE_STATUS, |
| 636 | IBI_STATUS, 1); |
| 637 | s->ibi_data.ibi_nacked = true; |
| 638 | s->ibi_data.disec_addr = addr; |
| 639 | /* Tell the requester to disable controller role requests. */ |
| 640 | s->ibi_data.disec_byte = DISEC_CR; |
| 641 | s->ibi_data.send_direct_disec = true; |
| 642 | return -1; |
| 643 | } |
| 644 | return 0; |
| 645 | } |
| 646 | |
| 647 | static int dw_i3c_handle_targ_irq(DWI3C *s, uint8_t addr) |
| 648 | { |
| 649 | if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ)) { |
| 650 | s->ibi_data.notify_ibi_nack = true; |
| 651 | } |
| 652 | |
| 653 | int table_offset = dw_i3c_addr_table_index_from_addr(s, addr); |
| 654 | /* Doesn't exist in the table, NACK it, don't DISEC. */ |
| 655 | if (table_offset < 0) { |
| 656 | return -1; |
| 657 | } |
| 658 | |
| 659 | /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ |
| 660 | table_offset += (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, |
| 661 | ADDR) / sizeof(uint32_t)); |
| 662 | if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, SIR_REJECT)) { |
| 663 | s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, |
| 664 | IBI_QUEUE_STATUS, |
| 665 | IBI_STATUS, 1); |
| 666 | s->ibi_data.ibi_nacked = true; |
| 667 | s->ibi_data.disec_addr = addr; |
| 668 | /* Tell the requester to disable interrupts. */ |
| 669 | s->ibi_data.disec_byte = DISEC_INT; |
| 670 | s->ibi_data.send_direct_disec = true; |
| 671 | return -1; |
| 672 | } |
| 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | static int dw_i3c_ibi_handle(I3CBus *bus, uint8_t addr, bool is_recv) |
| 677 | { |
| 678 | DWI3C *s = DW_I3C(bus->parent_obj.parent); |
| 679 | |
| 680 | trace_dw_i3c_ibi_handle(s->cfg.id, addr, is_recv); |
| 681 | s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, |
| 682 | IBI_QUEUE_STATUS, IBI_ID, |
| 683 | (addr << 1) | is_recv); |
| 684 | /* Is this a hot join request? */ |
| 685 | if (addr == I3C_HJ_ADDR) { |
| 686 | return dw_i3c_handle_hj(s); |
| 687 | } |
| 688 | /* Is secondary controller requesting access? */ |
| 689 | if (!is_recv) { |
| 690 | return dw_i3c_handle_ctlr_req(s, addr); |
| 691 | } |
| 692 | /* Is this a target IRQ? */ |
| 693 | if (is_recv) { |
| 694 | return dw_i3c_handle_targ_irq(s, addr); |
| 695 | } |
| 696 | |
| 697 | /* At this point the IBI should have been ACKed or NACKed. */ |
| 698 | g_assert_not_reached(); |
| 699 | return -1; |
| 700 | } |
| 701 | |
| 702 | static int dw_i3c_ibi_recv(I3CBus *bus, uint8_t data) |
| 703 | { |
| 704 | DWI3C *s = DW_I3C(bus->parent_obj.parent); |
| 705 | if (fifo8_is_full(&s->ibi_data.ibi_intermediate_queue)) { |
| 706 | return -1; |
| 707 | } |
| 708 | |
| 709 | fifo8_push(&s->ibi_data.ibi_intermediate_queue, data); |
| 710 | trace_dw_i3c_ibi_recv(s->cfg.id, data); |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | static void dw_i3c_ibi_queue_push(DWI3C *s) |
| 715 | { |
| 716 | /* Stored value is in 32-bit chunks, convert it to byte chunks. */ |
| 717 | uint8_t ibi_slice_size = dw_i3c_ibi_slice_size(s); |
| 718 | uint8_t num_slices = (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) / |
| 719 | ibi_slice_size) + |
| 720 | ((fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) % |
| 721 | ibi_slice_size) ? 1 : 0); |
| 722 | uint8_t ibi_status_count = num_slices; |
| 723 | union { |
| 724 | uint8_t b[sizeof(uint32_t)]; |
| 725 | uint32_t val32; |
| 726 | } ibi_data = { |
| 727 | .val32 = 0 |
| 728 | }; |
| 729 | |
| 730 | /* The report was suppressed, do nothing. */ |
| 731 | if (s->ibi_data.ibi_nacked && !s->ibi_data.notify_ibi_nack) { |
| 732 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 733 | DW_I3C_TRANSFER_STATE_IDLE); |
| 734 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 735 | DW_I3C_TRANSFER_STATUS_IDLE); |
| 736 | return; |
| 737 | } |
| 738 | |
| 739 | /* If we don't have any slices to push, just push the status. */ |
| 740 | if (num_slices == 0) { |
| 741 | s->ibi_data.ibi_queue_status = |
| 742 | FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, |
| 743 | LAST_STATUS, 1); |
| 744 | fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status); |
| 745 | ibi_status_count = 1; |
| 746 | } |
| 747 | |
| 748 | for (uint8_t i = 0; i < num_slices; i++) { |
| 749 | /* If this is the last slice, set LAST_STATUS. */ |
| 750 | if (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) < |
| 751 | ibi_slice_size) { |
| 752 | s->ibi_data.ibi_queue_status = |
| 753 | FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, |
| 754 | IBI_DATA_LEN, |
| 755 | fifo8_num_used(&s->ibi_data.ibi_intermediate_queue)); |
| 756 | s->ibi_data.ibi_queue_status = |
| 757 | FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, |
| 758 | LAST_STATUS, 1); |
| 759 | } else { |
| 760 | s->ibi_data.ibi_queue_status = |
| 761 | FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, |
| 762 | IBI_DATA_LEN, ibi_slice_size); |
| 763 | } |
| 764 | |
| 765 | /* Push the IBI status header. */ |
| 766 | fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status); |
| 767 | /* Move each IBI byte into a 32-bit word and push it into the queue. */ |
| 768 | for (uint8_t j = 0; j < ibi_slice_size; ++j) { |
| 769 | if (fifo8_is_empty(&s->ibi_data.ibi_intermediate_queue)) { |
| 770 | break; |
| 771 | } |
| 772 | |
| 773 | ibi_data.b[j & 3] = fifo8_pop(&s->ibi_data.ibi_intermediate_queue); |
| 774 | /* We have 32-bits, push it to the IBI FIFO. */ |
| 775 | if ((j & 0x03) == 0x03) { |
| 776 | fifo32_push(&s->ibi_queue, ibi_data.val32); |
| 777 | ibi_data.val32 = 0; |
| 778 | } |
| 779 | } |
| 780 | /* If the data isn't 32-bit aligned, push the leftover bytes. */ |
| 781 | if (ibi_slice_size & 0x03) { |
| 782 | fifo32_push(&s->ibi_queue, ibi_data.val32); |
| 783 | } |
| 784 | |
| 785 | /* Clear out the data length for the next iteration. */ |
| 786 | s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, |
| 787 | IBI_QUEUE_STATUS, IBI_DATA_LEN, 0); |
| 788 | } |
| 789 | |
| 790 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, |
| 791 | fifo32_num_used(&s->ibi_queue)); |
| 792 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, |
| 793 | ibi_status_count); |
| 794 | /* Threshold is the register value + 1. */ |
| 795 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 796 | IBI_STATUS_THLD) + 1; |
| 797 | if (fifo32_num_used(&s->ibi_queue) >= threshold) { |
| 798 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 1); |
| 799 | dw_i3c_update_irq(s); |
| 800 | } |
| 801 | |
| 802 | /* State update. */ |
| 803 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 804 | DW_I3C_TRANSFER_STATE_IDLE); |
| 805 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, |
| 806 | DW_I3C_TRANSFER_STATUS_IDLE); |
| 807 | } |
| 808 | |
| 809 | static int dw_i3c_ibi_finish(I3CBus *bus) |
| 810 | { |
| 811 | DWI3C *s = DW_I3C(bus->parent_obj.parent); |
| 812 | bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, |
| 813 | HOT_JOIN_ACK_NACK_CTRL); |
| 814 | if (nack_and_disable_hj || s->ibi_data.send_direct_disec) { |
| 815 | dw_i3c_send_disec(s); |
| 816 | } |
| 817 | dw_i3c_ibi_queue_push(s); |
| 818 | |
| 819 | /* Clear out the intermediate values. */ |
| 820 | s->ibi_data.ibi_queue_status = 0; |
| 821 | s->ibi_data.disec_addr = 0; |
| 822 | s->ibi_data.disec_byte = 0; |
| 823 | s->ibi_data.send_direct_disec = false; |
| 824 | s->ibi_data.notify_ibi_nack = false; |
| 825 | s->ibi_data.ibi_nacked = false; |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
| 830 | static uint32_t dw_i3c_intr_status_r(DWI3C *s) |
| 831 | { |
| 832 | /* Only return the status whose corresponding EN bits are set. */ |
| 833 | return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; |
| 834 | } |
| 835 | |
| 836 | static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) |
| 837 | { |
| 838 | /* INTR_STATUS[13:5] is w1c, other bits are RO. */ |
| 839 | val &= 0x3fe0; |
| 840 | s->regs[R_INTR_STATUS] &= ~val; |
| 841 | |
| 842 | dw_i3c_update_irq(s); |
| 843 | } |
| 844 | |
| 845 | static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) |
| 846 | { |
| 847 | s->regs[R_INTR_STATUS_EN] = val; |
| 848 | dw_i3c_update_irq(s); |
| 849 | } |
| 850 | |
| 851 | static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) |
| 852 | { |
| 853 | s->regs[R_INTR_SIGNAL_EN] = val; |
| 854 | dw_i3c_update_irq(s); |
| 855 | } |
| 856 | |
| 857 | static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) |
| 858 | { |
| 859 | /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ |
| 860 | s->regs[R_INTR_STATUS] = val; |
| 861 | dw_i3c_update_irq(s); |
| 862 | } |
| 863 | |
| 864 | static void dw_i3c_cmd_queue_reset(DWI3C *s) |
| 865 | { |
| 866 | fifo32_reset(&s->cmd_queue); |
| 867 | |
| 868 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, |
| 869 | fifo32_num_free(&s->cmd_queue)); |
| 870 | uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 871 | CMD_BUF_EMPTY_THLD); |
| 872 | if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) { |
| 873 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); |
| 874 | dw_i3c_update_irq(s); |
| 875 | }; |
| 876 | } |
| 877 | |
| 878 | static void dw_i3c_resp_queue_reset(DWI3C *s) |
| 879 | { |
| 880 | fifo32_reset(&s->resp_queue); |
| 881 | |
| 882 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, |
| 883 | fifo32_num_used(&s->resp_queue)); |
| 884 | /* |
| 885 | * This interrupt will always be cleared because the threshold is a minimum |
| 886 | * of 1 and the queue size is 0. |
| 887 | */ |
| 888 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); |
| 889 | dw_i3c_update_irq(s); |
| 890 | } |
| 891 | |
| 892 | static void dw_i3c_ibi_queue_reset(DWI3C *s) |
| 893 | { |
| 894 | fifo32_reset(&s->ibi_queue); |
| 895 | |
| 896 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, |
| 897 | fifo32_num_used(&s->resp_queue)); |
| 898 | /* |
| 899 | * This interrupt will always be cleared because the threshold is a minimum |
| 900 | * of 1 and the queue size is 0. |
| 901 | */ |
| 902 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0); |
| 903 | dw_i3c_update_irq(s); |
| 904 | } |
| 905 | |
| 906 | static void dw_i3c_tx_queue_reset(DWI3C *s) |
| 907 | { |
| 908 | fifo32_reset(&s->tx_queue); |
| 909 | |
| 910 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, |
| 911 | fifo32_num_free(&s->tx_queue)); |
| 912 | /* TX buf is empty, so this interrupt will always be set. */ |
| 913 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); |
| 914 | dw_i3c_update_irq(s); |
| 915 | } |
| 916 | |
| 917 | static void dw_i3c_rx_queue_reset(DWI3C *s) |
| 918 | { |
| 919 | fifo32_reset(&s->rx_queue); |
| 920 | |
| 921 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, |
| 922 | fifo32_num_used(&s->resp_queue)); |
| 923 | /* |
| 924 | * This interrupt will always be cleared because the threshold is a minimum |
| 925 | * of 1 and the queue size is 0. |
| 926 | */ |
| 927 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); |
| 928 | dw_i3c_update_irq(s); |
| 929 | } |
| 930 | |
| 931 | static void dw_i3c_reset(DeviceState *dev) |
| 932 | { |
| 933 | DWI3C *s = DW_I3C(dev); |
| 934 | trace_dw_i3c_reset(s->cfg.id); |
| 935 | |
| 936 | memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); |
| 937 | /* |
| 938 | * The user config for these may differ from our resets array, set them |
| 939 | * manually. |
| 940 | */ |
| 941 | ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, |
| 942 | s->cfg.dev_addr_table_pointer); |
| 943 | ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, |
| 944 | s->cfg.dev_addr_table_depth); |
| 945 | ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 946 | P_DEV_CHAR_TABLE_START_ADDR, |
| 947 | s->cfg.dev_char_table_pointer); |
| 948 | ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, |
| 949 | s->cfg.dev_char_table_depth); |
| 950 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, |
| 951 | s->cfg.cmd_resp_queue_capacity_words); |
| 952 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, |
| 953 | s->cfg.tx_rx_queue_capacity_words); |
| 954 | |
| 955 | dw_i3c_cmd_queue_reset(s); |
| 956 | dw_i3c_resp_queue_reset(s); |
| 957 | dw_i3c_ibi_queue_reset(s); |
| 958 | dw_i3c_tx_queue_reset(s); |
| 959 | dw_i3c_rx_queue_reset(s); |
| 960 | } |
| 961 | |
| 962 | static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val) |
| 963 | { |
| 964 | if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) { |
| 965 | dw_i3c_reset(DEVICE(s)); |
| 966 | } |
| 967 | if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) { |
| 968 | dw_i3c_cmd_queue_reset(s); |
| 969 | } |
| 970 | if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) { |
| 971 | dw_i3c_resp_queue_reset(s); |
| 972 | } |
| 973 | if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) { |
| 974 | dw_i3c_tx_queue_reset(s); |
| 975 | } |
| 976 | if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) { |
| 977 | dw_i3c_rx_queue_reset(s); |
| 978 | } |
| 979 | if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) { |
| 980 | dw_i3c_ibi_queue_reset(s); |
| 981 | } |
| 982 | } |
| 983 | |
| 984 | static uint32_t dw_i3c_pop_rx(DWI3C *s) |
| 985 | { |
| 986 | if (fifo32_is_empty(&s->rx_queue)) { |
| 987 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 988 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read RX FIFO when empty\n", |
| 989 | path); |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | uint32_t val = fifo32_pop(&s->rx_queue); |
| 994 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, |
| 995 | fifo32_num_used(&s->rx_queue)); |
| 996 | |
| 997 | /* Threshold is 2^RX_BUF_THLD. */ |
| 998 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, |
| 999 | RX_BUF_THLD); |
| 1000 | threshold = dw_i3c_fifo_threshold_from_reg(threshold); |
| 1001 | if (fifo32_num_used(&s->rx_queue) < threshold) { |
| 1002 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); |
| 1003 | dw_i3c_update_irq(s); |
| 1004 | } |
| 1005 | |
| 1006 | trace_dw_i3c_pop_rx(s->cfg.id, val); |
| 1007 | return val; |
| 1008 | } |
| 1009 | |
| 1010 | static uint32_t dw_i3c_ibi_queue_r(DWI3C *s) |
| 1011 | { |
| 1012 | if (fifo32_is_empty(&s->ibi_queue)) { |
| 1013 | return 0; |
| 1014 | } |
| 1015 | |
| 1016 | uint32_t val = fifo32_pop(&s->ibi_queue); |
| 1017 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, |
| 1018 | fifo32_num_used(&s->ibi_queue)); |
| 1019 | /* Threshold is the register value + 1. */ |
| 1020 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 1021 | IBI_STATUS_THLD) + 1; |
| 1022 | if (fifo32_num_used(&s->ibi_queue) < threshold) { |
| 1023 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0); |
| 1024 | dw_i3c_update_irq(s); |
| 1025 | } |
| 1026 | return val; |
| 1027 | } |
| 1028 | |
| 1029 | static uint32_t dw_i3c_resp_queue_port_r(DWI3C *s) |
| 1030 | { |
| 1031 | if (fifo32_is_empty(&s->resp_queue)) { |
| 1032 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1033 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read response FIFO when " |
| 1034 | "empty\n", path); |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
| 1038 | uint32_t val = fifo32_pop(&s->resp_queue); |
| 1039 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, |
| 1040 | fifo32_num_used(&s->resp_queue)); |
| 1041 | |
| 1042 | /* Threshold is the register value + 1. */ |
| 1043 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 1044 | RESP_BUF_THLD) + 1; |
| 1045 | if (fifo32_num_used(&s->resp_queue) < threshold) { |
| 1046 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); |
| 1047 | dw_i3c_update_irq(s); |
| 1048 | } |
| 1049 | |
| 1050 | return val; |
| 1051 | } |
| 1052 | |
| 1053 | static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) |
| 1054 | { |
| 1055 | DWI3C *s = DW_I3C(opaque); |
| 1056 | uint32_t addr = offset >> 2; |
| 1057 | uint64_t value; |
| 1058 | |
| 1059 | switch (addr) { |
| 1060 | /* RAZ */ |
| 1061 | case R_COMMAND_QUEUE_PORT: |
| 1062 | case R_RESET_CTRL: |
| 1063 | case R_INTR_FORCE: |
| 1064 | value = 0; |
| 1065 | break; |
| 1066 | case R_IBI_QUEUE_DATA: |
| 1067 | value = dw_i3c_ibi_queue_r(s); |
| 1068 | break; |
| 1069 | case R_INTR_STATUS: |
| 1070 | value = dw_i3c_intr_status_r(s); |
| 1071 | break; |
| 1072 | case R_RX_TX_DATA_PORT: |
| 1073 | value = dw_i3c_pop_rx(s); |
| 1074 | break; |
| 1075 | case R_RESPONSE_QUEUE_PORT: |
| 1076 | value = dw_i3c_resp_queue_port_r(s); |
| 1077 | break; |
| 1078 | default: |
| 1079 | value = s->regs[addr]; |
| 1080 | break; |
| 1081 | } |
| 1082 | |
| 1083 | trace_dw_i3c_read(s->cfg.id, offset, value); |
| 1084 | |
| 1085 | return value; |
| 1086 | } |
| 1087 | |
| 1088 | static void dw_i3c_resp_queue_push(DWI3C *s, uint8_t err, uint8_t tid, |
| 1089 | uint8_t ccc_type, uint16_t data_len) |
| 1090 | { |
| 1091 | uint32_t val = 0; |
| 1092 | val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, ERR_STATUS, err); |
| 1093 | val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, TID, tid); |
| 1094 | val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, CCCT, ccc_type); |
| 1095 | val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, DL, data_len); |
| 1096 | if (!fifo32_is_full(&s->resp_queue)) { |
| 1097 | trace_dw_i3c_resp_queue_push(s->cfg.id, val); |
| 1098 | fifo32_push(&s->resp_queue, val); |
| 1099 | } |
| 1100 | |
| 1101 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, |
| 1102 | fifo32_num_used(&s->resp_queue)); |
| 1103 | /* Threshold is the register value + 1. */ |
| 1104 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 1105 | RESP_BUF_THLD) + 1; |
| 1106 | if (fifo32_num_used(&s->resp_queue) >= threshold) { |
| 1107 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 1); |
| 1108 | dw_i3c_update_irq(s); |
| 1109 | } |
| 1110 | } |
| 1111 | |
| 1112 | static void dw_i3c_push_tx(DWI3C *s, uint32_t val) |
| 1113 | { |
| 1114 | if (fifo32_is_full(&s->tx_queue)) { |
| 1115 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1116 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to TX FIFO when " |
| 1117 | "full\n", path); |
| 1118 | return; |
| 1119 | } |
| 1120 | |
| 1121 | trace_dw_i3c_push_tx(s->cfg.id, val); |
| 1122 | fifo32_push(&s->tx_queue, val); |
| 1123 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, |
| 1124 | fifo32_num_free(&s->tx_queue)); |
| 1125 | |
| 1126 | /* Threshold is 2^TX_BUF_THLD. */ |
| 1127 | uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, |
| 1128 | TX_BUF_THLD); |
| 1129 | empty_threshold = |
| 1130 | dw_i3c_fifo_threshold_from_reg(empty_threshold); |
| 1131 | if (fifo32_num_free(&s->tx_queue) < empty_threshold) { |
| 1132 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 0); |
| 1133 | dw_i3c_update_irq(s); |
| 1134 | } |
| 1135 | } |
| 1136 | |
| 1137 | static uint32_t dw_i3c_pop_tx(DWI3C *s) |
| 1138 | { |
| 1139 | if (fifo32_is_empty(&s->tx_queue)) { |
| 1140 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1141 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to pop from TX FIFO when " |
| 1142 | "empty\n", path); |
| 1143 | return 0; |
| 1144 | } |
| 1145 | |
| 1146 | uint32_t val = fifo32_pop(&s->tx_queue); |
| 1147 | trace_dw_i3c_pop_tx(s->cfg.id, val); |
| 1148 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, |
| 1149 | fifo32_num_free(&s->tx_queue)); |
| 1150 | |
| 1151 | /* Threshold is 2^TX_BUF_THLD. */ |
| 1152 | uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, |
| 1153 | TX_BUF_THLD); |
| 1154 | empty_threshold = |
| 1155 | dw_i3c_fifo_threshold_from_reg(empty_threshold); |
| 1156 | if (fifo32_num_free(&s->tx_queue) >= empty_threshold) { |
| 1157 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); |
| 1158 | dw_i3c_update_irq(s); |
| 1159 | } |
| 1160 | return val; |
| 1161 | } |
| 1162 | |
| 1163 | static void dw_i3c_push_rx(DWI3C *s, uint32_t val) |
| 1164 | { |
| 1165 | if (fifo32_is_full(&s->rx_queue)) { |
| 1166 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1167 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to RX FIFO when " |
| 1168 | "full\n", path); |
| 1169 | return; |
| 1170 | } |
| 1171 | trace_dw_i3c_push_rx(s->cfg.id, val); |
| 1172 | fifo32_push(&s->rx_queue, val); |
| 1173 | |
| 1174 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, |
| 1175 | fifo32_num_used(&s->rx_queue)); |
| 1176 | /* Threshold is 2^RX_BUF_THLD. */ |
| 1177 | uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, |
| 1178 | RX_BUF_THLD); |
| 1179 | threshold = dw_i3c_fifo_threshold_from_reg(threshold); |
| 1180 | if (fifo32_num_used(&s->rx_queue) >= threshold) { |
| 1181 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 1); |
| 1182 | dw_i3c_update_irq(s); |
| 1183 | } |
| 1184 | } |
| 1185 | |
| 1186 | static void dw_i3c_short_transfer(DWI3C *s, DWI3CTransferCmd cmd, |
| 1187 | DWI3CShortArg arg) |
| 1188 | { |
| 1189 | uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; |
| 1190 | uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); |
| 1191 | bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); |
| 1192 | uint8_t data[4]; /* Max we can send on a short transfer is 4 bytes. */ |
| 1193 | uint8_t len = 0; |
| 1194 | uint32_t bytes_sent; /* Ignored on short transfers. */ |
| 1195 | |
| 1196 | /* Can't do reads on a short transfer. */ |
| 1197 | if (cmd.rnw) { |
| 1198 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1199 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Cannot do a read on a short " |
| 1200 | "transfer\n", path); |
| 1201 | return; |
| 1202 | } |
| 1203 | |
| 1204 | if (dw_i3c_send_start(s, addr, /*is_recv=*/false, is_i2c)) { |
| 1205 | err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; |
| 1206 | goto transfer_done; |
| 1207 | } |
| 1208 | |
| 1209 | /* Are we sending a command? */ |
| 1210 | if (cmd.cp) { |
| 1211 | data[len] = cmd.cmd; |
| 1212 | len++; |
| 1213 | /* |
| 1214 | * byte0 is the defining byte for a command, and is only sent if a |
| 1215 | * command is present and if the command has a defining byte present. |
| 1216 | * (byte_strb & 0x01) is always treated as set by the controller, and is |
| 1217 | * ignored. |
| 1218 | */ |
| 1219 | if (cmd.dbp) { |
| 1220 | data[len] = arg.byte0; |
| 1221 | len++; |
| 1222 | } |
| 1223 | } |
| 1224 | |
| 1225 | /* Send the bytes passed in the argument. */ |
| 1226 | if (arg.byte_strb & 0x02) { |
| 1227 | data[len] = arg.byte1; |
| 1228 | len++; |
| 1229 | } |
| 1230 | if (arg.byte_strb & 0x04) { |
| 1231 | data[len] = arg.byte2; |
| 1232 | len++; |
| 1233 | } |
| 1234 | |
| 1235 | if (len > 0) { |
| 1236 | if (dw_i3c_send(s, data, len, &bytes_sent, is_i2c)) { |
| 1237 | err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; |
| 1238 | } else { |
| 1239 | /* Only go to an idle state on a successful transfer. */ |
| 1240 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1241 | DW_I3C_TRANSFER_STATE_IDLE); |
| 1242 | } |
| 1243 | } else { |
| 1244 | /* No payload bytes for this short transfer. */ |
| 1245 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1246 | DW_I3C_TRANSFER_STATE_IDLE); |
| 1247 | } |
| 1248 | |
| 1249 | transfer_done: |
| 1250 | if (cmd.toc) { |
| 1251 | dw_i3c_end_transfer(s, is_i2c); |
| 1252 | } |
| 1253 | if (cmd.roc) { |
| 1254 | /* |
| 1255 | * ccc_type is always 0 in controller mode, data_len is 0 in short |
| 1256 | * transfers. |
| 1257 | */ |
| 1258 | dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, |
| 1259 | /*data_len=*/0); |
| 1260 | } |
| 1261 | } |
| 1262 | |
| 1263 | /* Returns number of bytes transmitted. */ |
| 1264 | static uint16_t dw_i3c_tx(DWI3C *s, uint16_t num, bool is_i2c) |
| 1265 | { |
| 1266 | uint16_t bytes_sent = 0; |
| 1267 | union { |
| 1268 | uint8_t b[sizeof(uint32_t)]; |
| 1269 | uint32_t val; |
| 1270 | } val32; |
| 1271 | |
| 1272 | while (bytes_sent < num) { |
| 1273 | val32.val = dw_i3c_pop_tx(s); |
| 1274 | for (uint8_t i = 0; i < sizeof(val32.val); i++) { |
| 1275 | if (dw_i3c_send_byte(s, val32.b[i], is_i2c)) { |
| 1276 | return bytes_sent; |
| 1277 | } |
| 1278 | bytes_sent++; |
| 1279 | |
| 1280 | /* We're not sending the full 32-bits, break early. */ |
| 1281 | if (bytes_sent >= num) { |
| 1282 | break; |
| 1283 | } |
| 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | return bytes_sent; |
| 1288 | } |
| 1289 | |
| 1290 | /* Returns number of bytes received. */ |
| 1291 | static uint16_t dw_i3c_rx(DWI3C *s, uint16_t num, bool is_i2c) |
| 1292 | { |
| 1293 | /* |
| 1294 | * Allocate a temporary buffer to read data from the target. |
| 1295 | * Zero it and word-align it as well in case we're reading unaligned data. |
| 1296 | */ |
| 1297 | g_autofree uint8_t *data = g_new0(uint8_t, ROUND_UP(num, 4)); |
| 1298 | uint32_t *data32 = (uint32_t *)data; |
| 1299 | /* |
| 1300 | * 32-bits since the I3C API wants a 32-bit number, even though the |
| 1301 | * controller can only do 16-bit transfers. |
| 1302 | */ |
| 1303 | uint32_t num_read = 0; |
| 1304 | |
| 1305 | /* Can NACK if the target receives an unsupported CCC. */ |
| 1306 | if (dw_i3c_recv_data(s, is_i2c, data, num, &num_read)) { |
| 1307 | return 0; |
| 1308 | } |
| 1309 | |
| 1310 | for (uint16_t i = 0; i < num_read / 4; i++) { |
| 1311 | dw_i3c_push_rx(s, *data32); |
| 1312 | data32++; |
| 1313 | } |
| 1314 | /* |
| 1315 | * If we're pushing data that isn't 32-bit aligned, push what's left. |
| 1316 | * It's software's responsibility to know what bits are valid in the partial |
| 1317 | * data. |
| 1318 | */ |
| 1319 | if (num_read & 0x03) { |
| 1320 | dw_i3c_push_rx(s, *data32); |
| 1321 | } |
| 1322 | |
| 1323 | return num_read; |
| 1324 | } |
| 1325 | |
| 1326 | static int dw_i3c_transfer_ccc(DWI3C *s, DWI3CTransferCmd cmd, |
| 1327 | DWI3CTransferArg arg) |
| 1328 | { |
| 1329 | /* CCC start is always a write. CCCs cannot be done on I2C devices. */ |
| 1330 | if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, |
| 1331 | /*is_i2c=*/false)) { |
| 1332 | return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; |
| 1333 | } |
| 1334 | trace_dw_i3c_transfer_ccc(s->cfg.id, cmd.cmd); |
| 1335 | if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { |
| 1336 | return DW_I3C_RESP_QUEUE_ERR_I2C_NACK; |
| 1337 | } |
| 1338 | |
| 1339 | /* On a direct CCC, we do a restart and then send the target's address. */ |
| 1340 | if (CCC_IS_DIRECT(cmd.cmd)) { |
| 1341 | bool is_recv = cmd.rnw; |
| 1342 | uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); |
| 1343 | if (dw_i3c_send_start(s, addr, is_recv, /*is_i2c=*/false)) { |
| 1344 | return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | return DW_I3C_RESP_QUEUE_ERR_NONE; |
| 1349 | } |
| 1350 | |
| 1351 | static void dw_i3c_transfer(DWI3C *s, DWI3CTransferCmd cmd, |
| 1352 | DWI3CTransferArg arg) |
| 1353 | { |
| 1354 | bool is_recv = cmd.rnw; |
| 1355 | uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; |
| 1356 | uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); |
| 1357 | bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); |
| 1358 | uint16_t bytes_transferred = 0; |
| 1359 | |
| 1360 | if (cmd.cp) { |
| 1361 | /* We're sending a CCC. */ |
| 1362 | err = dw_i3c_transfer_ccc(s, cmd, arg); |
| 1363 | if (err != DW_I3C_RESP_QUEUE_ERR_NONE) { |
| 1364 | goto transfer_done; |
| 1365 | } |
| 1366 | } else { |
| 1367 | if (ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_BROADCAST_ADDR_INC) && |
| 1368 | is_i2c == false) { |
| 1369 | if (dw_i3c_send_start(s, I3C_BROADCAST, |
| 1370 | /*is_recv=*/false, is_i2c)) { |
| 1371 | err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; |
| 1372 | goto transfer_done; |
| 1373 | } |
| 1374 | } |
| 1375 | /* Otherwise we're doing a private transfer. */ |
| 1376 | if (dw_i3c_send_start(s, addr, is_recv, is_i2c)) { |
| 1377 | err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; |
| 1378 | goto transfer_done; |
| 1379 | } |
| 1380 | } |
| 1381 | |
| 1382 | if (is_recv) { |
| 1383 | bytes_transferred = dw_i3c_rx(s, arg.data_len, is_i2c); |
| 1384 | } else { |
| 1385 | bytes_transferred = dw_i3c_tx(s, arg.data_len, is_i2c); |
| 1386 | } |
| 1387 | |
| 1388 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1389 | DW_I3C_TRANSFER_STATE_IDLE); |
| 1390 | |
| 1391 | transfer_done: |
| 1392 | if (cmd.toc) { |
| 1393 | dw_i3c_end_transfer(s, is_i2c); |
| 1394 | } |
| 1395 | if (cmd.roc) { |
| 1396 | /* |
| 1397 | * data_len is the number of bytes that still need to be TX'd, or the |
| 1398 | * number of bytes RX'd. |
| 1399 | */ |
| 1400 | uint16_t data_len = is_recv ? bytes_transferred : arg.data_len - |
| 1401 | bytes_transferred; |
| 1402 | /* CCCT is always 0 in controller mode. */ |
| 1403 | dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, |
| 1404 | data_len); |
| 1405 | } |
| 1406 | |
| 1407 | dw_i3c_update_irq(s); |
| 1408 | } |
| 1409 | |
| 1410 | static void dw_i3c_transfer_cmd(DWI3C *s, DWI3CTransferCmd cmd, |
| 1411 | DWI3CCmdQueueData arg) |
| 1412 | { |
| 1413 | uint8_t arg_attr = FIELD_EX32(arg.word, COMMAND_QUEUE_PORT, CMD_ATTR); |
| 1414 | |
| 1415 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CMD_TID, cmd.tid); |
| 1416 | |
| 1417 | /* User is trying to do HDR transfers, see if we can do them. */ |
| 1418 | if (cmd.speed == 0x06 && !dw_i3c_has_hdr_ddr(s)) { |
| 1419 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1420 | qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR DDR is not supported\n", path); |
| 1421 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1422 | DW_I3C_TRANSFER_STATE_HALT); |
| 1423 | return; |
| 1424 | } |
| 1425 | if (cmd.speed == 0x05 && !dw_i3c_has_hdr_ts(s)) { |
| 1426 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1427 | qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR TS is not supported\n", path); |
| 1428 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1429 | DW_I3C_TRANSFER_STATE_HALT); |
| 1430 | return; |
| 1431 | } |
| 1432 | |
| 1433 | if (arg_attr == DW_I3C_CMD_ATTR_TRANSFER_ARG) { |
| 1434 | dw_i3c_transfer(s, cmd, arg.transfer_arg); |
| 1435 | } else if (arg_attr == DW_I3C_CMD_ATTR_SHORT_DATA_ARG) { |
| 1436 | dw_i3c_short_transfer(s, cmd, arg.short_arg); |
| 1437 | } else { |
| 1438 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1439 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown command queue cmd_attr 0x%x" |
| 1440 | "\n", path, arg_attr); |
| 1441 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1442 | DW_I3C_TRANSFER_STATE_HALT); |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | static void dw_i3c_update_char_table(DWI3C *s, uint8_t offset, uint64_t pid, |
| 1447 | uint8_t bcr, uint8_t dcr, uint8_t addr) |
| 1448 | { |
| 1449 | if (offset > s->cfg.num_addressable_devices) { |
| 1450 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1451 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Device char table offset %d out of " |
| 1452 | "bounds\n", path, offset); |
| 1453 | /* If we're out of bounds, do nothing. */ |
| 1454 | return; |
| 1455 | } |
| 1456 | |
| 1457 | /* |
| 1458 | * Each device offset is 128 bits apart in the table, since each device gets |
| 1459 | * 4 * 32-bits of entries in the table. |
| 1460 | * / sizeof(uint32_t) because we're indexing into our 32-bit reg array. |
| 1461 | */ |
| 1462 | uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 1463 | P_DEV_CHAR_TABLE_START_ADDR) / |
| 1464 | sizeof(uint32_t)) + |
| 1465 | (offset * sizeof(uint32_t)); |
| 1466 | s->regs[dev_index] = (pid >> 16) & 0xffffffff; |
| 1467 | s->regs[dev_index + 1] = FIELD_DP32(s->regs[dev_index + 1], |
| 1468 | DEVICE_CHARACTERISTIC_TABLE_LOC2, |
| 1469 | MSB_PID, pid & 0xffff); |
| 1470 | s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], |
| 1471 | DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, |
| 1472 | dcr); |
| 1473 | s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], |
| 1474 | DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, |
| 1475 | bcr); |
| 1476 | s->regs[dev_index + 3] = FIELD_DP32(s->regs[dev_index + 3], |
| 1477 | DEVICE_CHARACTERISTIC_TABLE_LOC4, |
| 1478 | DEV_DYNAMIC_ADDR, addr); |
| 1479 | |
| 1480 | /* Increment PRESENT_DEV_CHAR_TABLE_INDEX. */ |
| 1481 | uint8_t idx = ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 1482 | PRESENT_DEV_CHAR_TABLE_INDEX); |
| 1483 | /* Increment and rollover. */ |
| 1484 | idx++; |
| 1485 | if (idx >= ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 1486 | DEV_CHAR_TABLE_DEPTH) / 4) { |
| 1487 | idx = 0; |
| 1488 | } |
| 1489 | ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 1490 | PRESENT_DEV_CHAR_TABLE_INDEX, idx); |
| 1491 | } |
| 1492 | |
| 1493 | static void dw_i3c_addr_assign_cmd(DWI3C *s, DWI3CAddrAssignCmd cmd) |
| 1494 | { |
| 1495 | uint8_t i = 0; |
| 1496 | uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; |
| 1497 | |
| 1498 | /* Tell everyone to ENTDAA. If these error, no one is on the bus. */ |
| 1499 | if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, |
| 1500 | /*is_i2c=*/false)) { |
| 1501 | err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; |
| 1502 | goto transfer_done; |
| 1503 | } |
| 1504 | if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { |
| 1505 | err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; |
| 1506 | goto transfer_done; |
| 1507 | } |
| 1508 | |
| 1509 | /* Go through each device in the table and assign it an address. */ |
| 1510 | for (i = 0; i < cmd.dev_count; i++) { |
| 1511 | uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index + i); |
| 1512 | union { |
| 1513 | uint64_t d; |
| 1514 | uint32_t w[2]; |
| 1515 | /* Per I3C spec: b[0]=PID MSB, b[5]=PID LSB, b[6]=BCR, b[7]=DCR */ |
| 1516 | uint8_t b[8]; |
| 1517 | } target_info; |
| 1518 | |
| 1519 | /* If this fails, there was no one left to ENTDAA. */ |
| 1520 | if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, |
| 1521 | /*is_i2c=*/false)) { |
| 1522 | err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; |
| 1523 | break; |
| 1524 | } |
| 1525 | |
| 1526 | /* |
| 1527 | * In ENTDAA, we read 8 bytes from the target, which will be the |
| 1528 | * target's PID, BCR, and DCR. After that, we send it the dynamic |
| 1529 | * address. |
| 1530 | * Don't bother checking the number of bytes received, it must send 8 |
| 1531 | * bytes during ENTDAA. |
| 1532 | */ |
| 1533 | uint32_t num_read; |
| 1534 | if (dw_i3c_recv_data(s, /*is_i2c=*/false, target_info.b, |
| 1535 | I3C_ENTDAA_SIZE, &num_read)) { |
| 1536 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1537 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed ENTDAA CCC\n", |
| 1538 | path); |
| 1539 | err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; |
| 1540 | goto transfer_done; |
| 1541 | } |
| 1542 | if (dw_i3c_send_byte(s, addr, /*is_i2c=*/false)) { |
| 1543 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1544 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed addr 0x%.2x " |
| 1545 | "during ENTDAA\n", path, addr); |
| 1546 | err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; |
| 1547 | break; |
| 1548 | } |
| 1549 | uint64_t pid = be64_to_cpu(target_info.d) >> 16; |
| 1550 | dw_i3c_update_char_table(s, cmd.dev_index + i, pid, target_info.b[6], |
| 1551 | target_info.b[7], addr); |
| 1552 | |
| 1553 | /* Push the PID, BCR, and DCR to the RX queue. */ |
| 1554 | dw_i3c_push_rx(s, target_info.w[0]); |
| 1555 | dw_i3c_push_rx(s, target_info.w[1]); |
| 1556 | } |
| 1557 | |
| 1558 | transfer_done: |
| 1559 | /* Do we send a STOP? */ |
| 1560 | if (cmd.toc) { |
| 1561 | dw_i3c_end_transfer(s, /*is_i2c=*/false); |
| 1562 | } |
| 1563 | /* |
| 1564 | * For addr assign commands, the length field is the number of devices |
| 1565 | * left to assign. CCCT is always 0 in controller mode. |
| 1566 | */ |
| 1567 | if (cmd.roc) { |
| 1568 | dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, |
| 1569 | cmd.dev_count - i); |
| 1570 | } |
| 1571 | } |
| 1572 | |
| 1573 | static uint32_t dw_i3c_cmd_queue_pop(DWI3C *s) |
| 1574 | { |
| 1575 | if (fifo32_is_empty(&s->cmd_queue)) { |
| 1576 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1577 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to dequeue command queue " |
| 1578 | "when it was empty\n", path); |
| 1579 | return 0; |
| 1580 | } |
| 1581 | uint32_t val = fifo32_pop(&s->cmd_queue); |
| 1582 | |
| 1583 | uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 1584 | CMD_BUF_EMPTY_THLD); |
| 1585 | uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, |
| 1586 | QUEUE_STATUS_LEVEL, |
| 1587 | CMD_QUEUE_EMPTY_LOC); |
| 1588 | cmd_queue_empty_loc++; |
| 1589 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, |
| 1590 | cmd_queue_empty_loc); |
| 1591 | if (cmd_queue_empty_loc >= empty_threshold) { |
| 1592 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); |
| 1593 | dw_i3c_update_irq(s); |
| 1594 | } |
| 1595 | |
| 1596 | return val; |
| 1597 | } |
| 1598 | |
| 1599 | static void dw_i3c_cmd_queue_execute(DWI3C *s) |
| 1600 | { |
| 1601 | ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, |
| 1602 | DW_I3C_TRANSFER_STATE_IDLE); |
| 1603 | if (!dw_i3c_can_transmit(s)) { |
| 1604 | return; |
| 1605 | } |
| 1606 | |
| 1607 | /* |
| 1608 | * We only start executing when a command is passed into the FIFO. |
| 1609 | * We expect there to be a multiple of 2 items in the queue. The first item |
| 1610 | * should be an argument to a command, and the command should be the second |
| 1611 | * item. |
| 1612 | */ |
| 1613 | if (fifo32_num_used(&s->cmd_queue) & 1) { |
| 1614 | return; |
| 1615 | } |
| 1616 | |
| 1617 | while (!fifo32_is_empty(&s->cmd_queue)) { |
| 1618 | DWI3CCmdQueueData arg; |
| 1619 | arg.word = dw_i3c_cmd_queue_pop(s); |
| 1620 | DWI3CCmdQueueData cmd; |
| 1621 | cmd.word = dw_i3c_cmd_queue_pop(s); |
| 1622 | trace_dw_i3c_cmd_queue_execute(s->cfg.id, cmd.word, arg.word); |
| 1623 | |
| 1624 | uint8_t cmd_attr = FIELD_EX32(cmd.word, COMMAND_QUEUE_PORT, CMD_ATTR); |
| 1625 | switch (cmd_attr) { |
| 1626 | case DW_I3C_CMD_ATTR_TRANSFER_CMD: |
| 1627 | dw_i3c_transfer_cmd(s, cmd.transfer_cmd, arg); |
| 1628 | break; |
| 1629 | case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: |
| 1630 | /* Arg is discarded for addr assign commands. */ |
| 1631 | dw_i3c_addr_assign_cmd(s, cmd.addr_assign_cmd); |
| 1632 | break; |
| 1633 | case DW_I3C_CMD_ATTR_TRANSFER_ARG: |
| 1634 | case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: |
| 1635 | { |
| 1636 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1637 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received " |
| 1638 | "argument packet when it expected a command " |
| 1639 | "packet\n", path); |
| 1640 | } |
| 1641 | break; |
| 1642 | default: |
| 1643 | /* |
| 1644 | * The caller's check before queueing an item should prevent this |
| 1645 | * from happening. |
| 1646 | */ |
| 1647 | g_assert_not_reached(); |
| 1648 | break; |
| 1649 | } |
| 1650 | } |
| 1651 | } |
| 1652 | |
| 1653 | static void dw_i3c_cmd_queue_push(DWI3C *s, uint32_t val) |
| 1654 | { |
| 1655 | if (fifo32_is_full(&s->cmd_queue)) { |
| 1656 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1657 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet when " |
| 1658 | "already full\n", path); |
| 1659 | return; |
| 1660 | } |
| 1661 | trace_dw_i3c_cmd_queue_push(s->cfg.id, val); |
| 1662 | fifo32_push(&s->cmd_queue, val); |
| 1663 | |
| 1664 | uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, |
| 1665 | CMD_BUF_EMPTY_THLD); |
| 1666 | uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, |
| 1667 | QUEUE_STATUS_LEVEL, |
| 1668 | CMD_QUEUE_EMPTY_LOC); |
| 1669 | if (cmd_queue_empty_loc) { |
| 1670 | cmd_queue_empty_loc--; |
| 1671 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, |
| 1672 | cmd_queue_empty_loc); |
| 1673 | } |
| 1674 | if (cmd_queue_empty_loc < empty_threshold) { |
| 1675 | ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 0); |
| 1676 | dw_i3c_update_irq(s); |
| 1677 | } |
| 1678 | } |
| 1679 | |
| 1680 | static void dw_i3c_cmd_queue_port_w(DWI3C *s, uint32_t val) |
| 1681 | { |
| 1682 | uint8_t cmd_attr = FIELD_EX32(val, COMMAND_QUEUE_PORT, CMD_ATTR); |
| 1683 | |
| 1684 | switch (cmd_attr) { |
| 1685 | /* If a command is received we can start executing it. */ |
| 1686 | case DW_I3C_CMD_ATTR_TRANSFER_CMD: |
| 1687 | case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: |
| 1688 | dw_i3c_cmd_queue_push(s, val); |
| 1689 | dw_i3c_cmd_queue_execute(s); |
| 1690 | break; |
| 1691 | /* If we get an argument just push it. */ |
| 1692 | case DW_I3C_CMD_ATTR_TRANSFER_ARG: |
| 1693 | case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: |
| 1694 | dw_i3c_cmd_queue_push(s, val); |
| 1695 | break; |
| 1696 | default: |
| 1697 | { |
| 1698 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
| 1699 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet " |
| 1700 | "with unknown cmd attr 0x%x\n", path, cmd_attr); |
| 1701 | } |
| 1702 | break; |
| 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, |
| 1707 | unsigned size) |
| 1708 | { |
| 1709 | DWI3C *s = DW_I3C(opaque); |
| 1710 | uint32_t addr = offset >> 2; |
| 1711 | uint32_t val32 = (uint32_t)value; |
| 1712 | |
| 1713 | trace_dw_i3c_write(s->cfg.id, offset, value); |
| 1714 | |
| 1715 | val32 &= ~dw_i3c_ro[addr]; |
| 1716 | switch (addr) { |
| 1717 | case R_HW_CAPABILITY: |
| 1718 | case R_RESPONSE_QUEUE_PORT: |
| 1719 | case R_IBI_QUEUE_DATA: |
| 1720 | case R_QUEUE_STATUS_LEVEL: |
| 1721 | case R_PRESENT_STATE: |
| 1722 | case R_CCC_DEVICE_STATUS: |
| 1723 | case R_DEVICE_ADDR_TABLE_POINTER: |
| 1724 | case R_VENDOR_SPECIFIC_REG_POINTER: |
| 1725 | case R_SLV_CHAR_CTRL: |
| 1726 | case R_SLV_MAX_LEN: |
| 1727 | case R_MAX_READ_TURNAROUND: |
| 1728 | case R_I3C_VER_ID: |
| 1729 | case R_I3C_VER_TYPE: |
| 1730 | case R_EXTENDED_CAPABILITY: |
| 1731 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1732 | "%s: write to readonly register[0x%02" HWADDR_PRIx |
| 1733 | "] = 0x%08" PRIx64 "\n", |
| 1734 | __func__, offset, value); |
| 1735 | break; |
| 1736 | case R_DEVICE_CTRL: |
| 1737 | dw_i3c_ctrl_w(s, val32); |
| 1738 | break; |
| 1739 | case R_RX_TX_DATA_PORT: |
| 1740 | dw_i3c_push_tx(s, val32); |
| 1741 | break; |
| 1742 | case R_COMMAND_QUEUE_PORT: |
| 1743 | dw_i3c_cmd_queue_port_w(s, val32); |
| 1744 | break; |
| 1745 | case R_RESET_CTRL: |
| 1746 | dw_i3c_reset_ctrl_w(s, val32); |
| 1747 | break; |
| 1748 | case R_INTR_STATUS: |
| 1749 | dw_i3c_intr_status_w(s, val32); |
| 1750 | break; |
| 1751 | case R_INTR_STATUS_EN: |
| 1752 | dw_i3c_intr_status_en_w(s, val32); |
| 1753 | break; |
| 1754 | case R_INTR_SIGNAL_EN: |
| 1755 | dw_i3c_intr_signal_en_w(s, val32); |
| 1756 | break; |
| 1757 | case R_INTR_FORCE: |
| 1758 | dw_i3c_intr_force_w(s, val32); |
| 1759 | break; |
| 1760 | default: |
| 1761 | s->regs[addr] = val32; |
| 1762 | break; |
| 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | const VMStateDescription vmstate_dw_i3c = { |
| 1767 | .name = TYPE_DW_I3C, |
| 1768 | .version_id = 1, |
| 1769 | .minimum_version_id = 1, |
| 1770 | .fields = (VMStateField[]){ |
| 1771 | VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS), |
| 1772 | VMSTATE_END_OF_LIST(), |
| 1773 | } |
| 1774 | }; |
| 1775 | |
| 1776 | static const MemoryRegionOps dw_i3c_ops = { |
| 1777 | .read = dw_i3c_read, |
| 1778 | .write = dw_i3c_write, |
| 1779 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1780 | }; |
| 1781 | |
| 1782 | static void dw_i3c_reset_enter(Object *obj, ResetType type) |
| 1783 | { |
| 1784 | DWI3C *s = DW_I3C(obj); |
| 1785 | |
| 1786 | memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); |
| 1787 | /* |
| 1788 | * The user config for these may differ from our resets array, set them |
| 1789 | * manually. |
| 1790 | */ |
| 1791 | ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, |
| 1792 | s->cfg.dev_addr_table_pointer); |
| 1793 | ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, |
| 1794 | s->cfg.dev_addr_table_depth); |
| 1795 | ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, |
| 1796 | P_DEV_CHAR_TABLE_START_ADDR, |
| 1797 | s->cfg.dev_char_table_pointer); |
| 1798 | ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, |
| 1799 | s->cfg.dev_char_table_depth); |
| 1800 | ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, |
| 1801 | s->cfg.cmd_resp_queue_capacity_words); |
| 1802 | ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, |
| 1803 | s->cfg.tx_rx_queue_capacity_words); |
| 1804 | } |
| 1805 | |
| 1806 | static void dw_i3c_realize(DeviceState *dev, Error **errp) |
| 1807 | { |
| 1808 | DWI3C *s = DW_I3C(dev); |
| 1809 | g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->cfg.id); |
| 1810 | |
| 1811 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); |
| 1812 | |
| 1813 | memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, |
| 1814 | DW_I3C_NR_REGS << 2); |
| 1815 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); |
| 1816 | |
| 1817 | fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_words); |
| 1818 | fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_words); |
| 1819 | fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_words); |
| 1820 | fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_words); |
| 1821 | fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_words); |
| 1822 | /* Arbitrarily large enough to not be an issue. */ |
| 1823 | fifo8_create(&s->ibi_data.ibi_intermediate_queue, |
| 1824 | s->cfg.ibi_queue_capacity_words * 8); |
| 1825 | |
| 1826 | s->bus = i3c_init_bus(DEVICE(s), name); |
| 1827 | I3CBusClass *bc = I3C_BUS_GET_CLASS(s->bus); |
| 1828 | bc->ibi_handle = dw_i3c_ibi_handle; |
| 1829 | bc->ibi_recv = dw_i3c_ibi_recv; |
| 1830 | bc->ibi_finish = dw_i3c_ibi_finish; |
| 1831 | } |
| 1832 | |
| 1833 | /* |
| 1834 | * The *-queue-capacity-bytes properties shipped in v11.0.0 under names that |
| 1835 | * implied a byte count, but the values are 32-bit word counts (they are passed |
| 1836 | * straight to fifo32_create()). They were renamed to *-queue-capacity-words; |
| 1837 | * keep the old names working as aliases so existing command lines using e.g. |
| 1838 | * -global driver=dw.i3c,property=tx-rx-queue-capacity-bytes,... don't break. |
| 1839 | */ |
| 1840 | static void dw_i3c_init(Object *obj) |
| 1841 | { |
| 1842 | static const char *const alias[][2] = { |
| 1843 | { "command-response-queue-capacity-bytes", |
| 1844 | "command-response-queue-capacity-words" }, |
| 1845 | { "tx-rx-queue-capacity-bytes", "tx-rx-queue-capacity-words" }, |
| 1846 | { "ibi-queue-capacity-bytes", "ibi-queue-capacity-words" }, |
| 1847 | }; |
| 1848 | |
| 1849 | for (int i = 0; i < ARRAY_SIZE(alias); i++) { |
| 1850 | object_property_add_alias(obj, alias[i][0], obj, alias[i][1]); |
| 1851 | } |
| 1852 | } |
| 1853 | |
| 1854 | static const Property dw_i3c_properties[] = { |
| 1855 | DEFINE_PROP_UINT8("device-id", DWI3C, cfg.id, 0), |
| 1856 | DEFINE_PROP_UINT8("command-response-queue-capacity-words", DWI3C, |
| 1857 | cfg.cmd_resp_queue_capacity_words, 0x10), |
| 1858 | DEFINE_PROP_UINT16("tx-rx-queue-capacity-words", DWI3C, |
| 1859 | cfg.tx_rx_queue_capacity_words, 0x40), |
| 1860 | DEFINE_PROP_UINT8("ibi-queue-capacity-words", DWI3C, |
| 1861 | cfg.ibi_queue_capacity_words, 0x10), |
| 1862 | DEFINE_PROP_UINT8("num-addressable-devices", DWI3C, |
| 1863 | cfg.num_addressable_devices, 8), |
| 1864 | DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C, |
| 1865 | cfg.dev_addr_table_pointer, 0x280), |
| 1866 | DEFINE_PROP_UINT16("dev-addr-table-depth", DWI3C, |
| 1867 | cfg.dev_addr_table_depth, 0x08), |
| 1868 | DEFINE_PROP_UINT16("dev-char-table-pointer", DWI3C, |
| 1869 | cfg.dev_char_table_pointer, 0x200), |
| 1870 | DEFINE_PROP_UINT16("dev-char-table-depth", DWI3C, |
| 1871 | cfg.dev_char_table_depth, 0x20), |
| 1872 | }; |
| 1873 | |
| 1874 | static void dw_i3c_class_init(ObjectClass *klass, const void *data) |
| 1875 | { |
| 1876 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1877 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 1878 | |
| 1879 | rc->phases.enter = dw_i3c_reset_enter; |
| 1880 | |
| 1881 | dc->desc = "DesignWare I3C Controller"; |
| 1882 | dc->realize = dw_i3c_realize; |
| 1883 | dc->vmsd = &vmstate_dw_i3c; |
| 1884 | device_class_set_props(dc, dw_i3c_properties); |
| 1885 | } |
| 1886 | |
| 1887 | static const TypeInfo dw_i3c_types[] = { |
| 1888 | { |
| 1889 | .name = TYPE_DW_I3C, |
| 1890 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1891 | .instance_size = sizeof(DWI3C), |
| 1892 | .instance_init = dw_i3c_init, |
| 1893 | .class_init = dw_i3c_class_init, |
| 1894 | }, |
| 1895 | }; |
| 1896 | |
| 1897 | DEFINE_TYPES(dw_i3c_types) |
| 1898 |