| 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 2 | |
| 3 | # aspeed_i3c.c |
| 4 | aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 5 | aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 6 | |
| 7 | # dw-i3c,c |
| 8 | dw_i3c_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 9 | dw_i3c_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 10 | dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes to bus" |
| 11 | dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus" |
| 12 | dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8 |
| 13 | dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d" |
| 14 | dw_i3c_reset(uint32_t deviceid) "I3C Dev[%u] reset" |
| 15 | dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO" |
| 16 | dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue" |
| 17 | dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO" |
| 18 | dw_i3c_pop_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from TX FIFO" |
| 19 | dw_i3c_push_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to RX FIFO" |
| 20 | dw_i3c_transfer_ccc(uint32_t deviceid, uint8_t ccc) "I3C Dev[%u] transfer CCC 0x%" PRIx8 |
| 21 | dw_i3c_cmd_queue_execute(uint32_t deviceid, uint32_t cmd, uint32_t arg) "I3C Dev[%u] execute command 0x%" PRIx32 " arg 0x%" PRIx32 |
| 22 | dw_i3c_cmd_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to cmd queue" |
| 23 | |
| 24 | # core.c |
| 25 | i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8 |
| 26 | i3c_target_handle_ccc(uint8_t address, uint8_t ccc) "I3C target 0x%" PRIx8 " handling CCC 0x%" PRIx8 |
| 27 | i3c_target_send_ibi(uint8_t address, bool is_recv) "I3C target IBI address 0x%" PRIx8 " RnW=%d" |
| 28 | i3c_target_send_ibi_bytes(uint8_t byte) "I3C target IBI byte 0x%" PRIx8 |
| 29 | i3c_target_ibi_finish(void) "I3C target IBI finish" |
| 30 | i3c_start_transfer(uint8_t address, bool is_recv) "I3C START with address 0x%" PRIx8 " is_recv=%d" |
| 31 | i3c_end_transfer(void) "I3C transfer done" |
| 32 | i3c_send(uint32_t num_sent, uint32_t num_to_send, bool ack) "I3C send %" PRId32 "/%" PRId32 " bytes, ack=%d" |
| 33 | i3c_recv(uint32_t num_read, uint32_t num_to_read, bool ack) "I3C recv %" PRId32 "/%" PRId32 " bytes, ack=%d" |
| 34 | legacy_i2c_nack(void) "Legacy I2C NACK" |
| 35 | legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8 |
| 36 | legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8 |
| 37 | legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START with address 0x%" PRIx8 " is_recv=%d" |
| 38 | legacy_i2c_end_transfer(void) "Legacy I2C STOP" |
| 39 | |
| 40 | # mock-target.c |
| 41 | mock_i3c_target_rx(uint8_t byte) "I3C mock target read 0x%" PRIx8 |
| 42 | mock_i3c_target_tx(uint8_t byte) "I3C mock target write 0x%" PRIx8 |
| 43 | mock_i3c_target_event(uint8_t event) "I3C mock target event 0x%" PRIx8 |
| 44 | mock_i3c_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "I3C mock target read %" PRId32 "/%" PRId32 " bytes" |
| 45 | mock_i3c_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8 |
| 46 | mock_i3c_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) "I3C mock target send %" PRId32 "/%" PRId32 " bytes" |
| 47 | mock_i3c_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI with address 0x%" PRIx8 " RnW=%d" |
| 48 | mock_i3c_target_do_ibi_nack(const char *reason) "NACKed from controller when %s target interrupt" |