| 1 | /* |
| 2 | * QEMU AHCI Emulation |
| 3 | * |
| 4 | * Copyright (c) 2010 qiaochong@loongson.cn |
| 5 | * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> |
| 6 | * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> |
| 7 | * Copyright (c) 2010 Alexander Graf <agraf@suse.de> |
| 8 | * |
| 9 | * This library is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU Lesser General Public |
| 11 | * License as published by the Free Software Foundation; either |
| 12 | * version 2.1 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This library is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * Lesser General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU Lesser General Public |
| 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include "qemu/osdep.h" |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "migration/vmstate.h" |
| 27 | |
| 28 | #include "qemu/error-report.h" |
| 29 | #include "qemu/log.h" |
| 30 | #include "qemu/main-loop.h" |
| 31 | #include "system/block-backend.h" |
| 32 | #include "system/dma.h" |
| 33 | #include "ahci-internal.h" |
| 34 | #include "ide-internal.h" |
| 35 | |
| 36 | #include "trace.h" |
| 37 | |
| 38 | static void check_cmd(AHCIState *s, int port); |
| 39 | static void handle_cmd(AHCIState *s, int port, uint8_t slot); |
| 40 | static void ahci_reset_port(AHCIState *s, int port, IDEResetKind kind); |
| 41 | static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); |
| 42 | static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); |
| 43 | static void ahci_init_d2h(AHCIDevice *ad); |
| 44 | static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); |
| 45 | static bool ahci_map_clb_address(AHCIDevice *ad); |
| 46 | static bool ahci_map_fis_address(AHCIDevice *ad); |
| 47 | static void ahci_unmap_clb_address(AHCIDevice *ad); |
| 48 | static void ahci_unmap_fis_address(AHCIDevice *ad); |
| 49 | |
| 50 | static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { |
| 51 | [AHCI_HOST_REG_CAP] = "CAP", |
| 52 | [AHCI_HOST_REG_CTL] = "GHC", |
| 53 | [AHCI_HOST_REG_IRQ_STAT] = "IS", |
| 54 | [AHCI_HOST_REG_PORTS_IMPL] = "PI", |
| 55 | [AHCI_HOST_REG_VERSION] = "VS", |
| 56 | [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", |
| 57 | [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", |
| 58 | [AHCI_HOST_REG_EM_LOC] = "EM_LOC", |
| 59 | [AHCI_HOST_REG_EM_CTL] = "EM_CTL", |
| 60 | [AHCI_HOST_REG_CAP2] = "CAP2", |
| 61 | [AHCI_HOST_REG_BOHC] = "BOHC", |
| 62 | }; |
| 63 | |
| 64 | static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { |
| 65 | [AHCI_PORT_REG_LST_ADDR] = "PxCLB", |
| 66 | [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", |
| 67 | [AHCI_PORT_REG_FIS_ADDR] = "PxFB", |
| 68 | [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", |
| 69 | [AHCI_PORT_REG_IRQ_STAT] = "PxIS", |
| 70 | [AHCI_PORT_REG_IRQ_MASK] = "PXIE", |
| 71 | [AHCI_PORT_REG_CMD] = "PxCMD", |
| 72 | [7] = "Reserved", |
| 73 | [AHCI_PORT_REG_TFDATA] = "PxTFD", |
| 74 | [AHCI_PORT_REG_SIG] = "PxSIG", |
| 75 | [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", |
| 76 | [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", |
| 77 | [AHCI_PORT_REG_SCR_ERR] = "PxSERR", |
| 78 | [AHCI_PORT_REG_SCR_ACT] = "PxSACT", |
| 79 | [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", |
| 80 | [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", |
| 81 | [AHCI_PORT_REG_FIS_CTL] = "PxFBS", |
| 82 | [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", |
| 83 | [18 ... 27] = "Reserved", |
| 84 | [AHCI_PORT_REG_VENDOR_1 ... |
| 85 | AHCI_PORT_REG_VENDOR_4] = "PxVS", |
| 86 | }; |
| 87 | |
| 88 | static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { |
| 89 | [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", |
| 90 | [AHCI_PORT_IRQ_BIT_PSS] = "PSS", |
| 91 | [AHCI_PORT_IRQ_BIT_DSS] = "DSS", |
| 92 | [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", |
| 93 | [AHCI_PORT_IRQ_BIT_UFS] = "UFS", |
| 94 | [AHCI_PORT_IRQ_BIT_DPS] = "DPS", |
| 95 | [AHCI_PORT_IRQ_BIT_PCS] = "PCS", |
| 96 | [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", |
| 97 | [8 ... 21] = "RESERVED", |
| 98 | [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", |
| 99 | [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", |
| 100 | [AHCI_PORT_IRQ_BIT_OFS] = "OFS", |
| 101 | [25] = "RESERVED", |
| 102 | [AHCI_PORT_IRQ_BIT_INFS] = "INFS", |
| 103 | [AHCI_PORT_IRQ_BIT_IFS] = "IFS", |
| 104 | [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", |
| 105 | [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", |
| 106 | [AHCI_PORT_IRQ_BIT_TFES] = "TFES", |
| 107 | [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" |
| 108 | }; |
| 109 | |
| 110 | static uint32_t ahci_port_read(AHCIState *s, int port, int offset) |
| 111 | { |
| 112 | uint32_t val; |
| 113 | AHCIPortRegs *pr = &s->dev[port].port_regs; |
| 114 | enum AHCIPortReg regnum = offset / sizeof(uint32_t); |
| 115 | assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); |
| 116 | |
| 117 | switch (regnum) { |
| 118 | case AHCI_PORT_REG_LST_ADDR: |
| 119 | val = pr->lst_addr; |
| 120 | break; |
| 121 | case AHCI_PORT_REG_LST_ADDR_HI: |
| 122 | val = pr->lst_addr_hi; |
| 123 | break; |
| 124 | case AHCI_PORT_REG_FIS_ADDR: |
| 125 | val = pr->fis_addr; |
| 126 | break; |
| 127 | case AHCI_PORT_REG_FIS_ADDR_HI: |
| 128 | val = pr->fis_addr_hi; |
| 129 | break; |
| 130 | case AHCI_PORT_REG_IRQ_STAT: |
| 131 | val = pr->irq_stat; |
| 132 | break; |
| 133 | case AHCI_PORT_REG_IRQ_MASK: |
| 134 | val = pr->irq_mask; |
| 135 | break; |
| 136 | case AHCI_PORT_REG_CMD: |
| 137 | val = pr->cmd; |
| 138 | break; |
| 139 | case AHCI_PORT_REG_TFDATA: |
| 140 | val = pr->tfdata; |
| 141 | break; |
| 142 | case AHCI_PORT_REG_SIG: |
| 143 | val = pr->sig; |
| 144 | break; |
| 145 | case AHCI_PORT_REG_SCR_STAT: |
| 146 | if (s->dev[port].port.ifs[0].blk) { |
| 147 | val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | |
| 148 | SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; |
| 149 | } else { |
| 150 | val = SATA_SCR_SSTATUS_DET_NODEV; |
| 151 | } |
| 152 | break; |
| 153 | case AHCI_PORT_REG_SCR_CTL: |
| 154 | val = pr->scr_ctl; |
| 155 | break; |
| 156 | case AHCI_PORT_REG_SCR_ERR: |
| 157 | val = pr->scr_err; |
| 158 | break; |
| 159 | case AHCI_PORT_REG_SCR_ACT: |
| 160 | val = pr->scr_act; |
| 161 | break; |
| 162 | case AHCI_PORT_REG_CMD_ISSUE: |
| 163 | val = pr->cmd_issue; |
| 164 | break; |
| 165 | default: |
| 166 | trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], |
| 167 | offset); |
| 168 | val = 0; |
| 169 | } |
| 170 | |
| 171 | trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); |
| 172 | return val; |
| 173 | } |
| 174 | |
| 175 | static void ahci_check_irq(AHCIState *s) |
| 176 | { |
| 177 | int i; |
| 178 | uint32_t old_irq = s->control_regs.irqstatus; |
| 179 | |
| 180 | s->control_regs.irqstatus = 0; |
| 181 | for (i = 0; i < s->ports; i++) { |
| 182 | AHCIPortRegs *pr = &s->dev[i].port_regs; |
| 183 | if (pr->irq_stat & pr->irq_mask) { |
| 184 | s->control_regs.irqstatus |= (1 << i); |
| 185 | } |
| 186 | } |
| 187 | trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); |
| 188 | if (s->control_regs.irqstatus && |
| 189 | (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { |
| 190 | trace_ahci_irq_raise(s); |
| 191 | qemu_irq_raise(s->irq); |
| 192 | } else { |
| 193 | trace_ahci_irq_lower(s); |
| 194 | qemu_irq_lower(s->irq); |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, |
| 199 | enum AHCIPortIRQ irqbit) |
| 200 | { |
| 201 | g_assert((unsigned)irqbit < 32); |
| 202 | uint32_t irq = 1U << irqbit; |
| 203 | uint32_t irqstat = d->port_regs.irq_stat | irq; |
| 204 | |
| 205 | trace_ahci_trigger_irq(s, d->port_no, |
| 206 | AHCIPortIRQ_lookup[irqbit], irq, |
| 207 | d->port_regs.irq_stat, irqstat, |
| 208 | irqstat & d->port_regs.irq_mask); |
| 209 | |
| 210 | d->port_regs.irq_stat = irqstat; |
| 211 | ahci_check_irq(s); |
| 212 | } |
| 213 | |
| 214 | static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, |
| 215 | uint32_t wanted) |
| 216 | { |
| 217 | hwaddr len = wanted; |
| 218 | |
| 219 | if (*ptr) { |
| 220 | dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); |
| 221 | } |
| 222 | |
| 223 | *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, |
| 224 | MEMTXATTRS_UNSPECIFIED); |
| 225 | if (len < wanted && *ptr) { |
| 226 | dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); |
| 227 | *ptr = NULL; |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | /** |
| 232 | * Check the cmd register to see if we should start or stop |
| 233 | * the DMA or FIS RX engines. |
| 234 | * |
| 235 | * @ad: Device to dis/engage. |
| 236 | * |
| 237 | * @return 0 on success, -1 on error. |
| 238 | */ |
| 239 | static int ahci_cond_start_engines(AHCIDevice *ad) |
| 240 | { |
| 241 | AHCIPortRegs *pr = &ad->port_regs; |
| 242 | bool cmd_start = pr->cmd & PORT_CMD_START; |
| 243 | bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; |
| 244 | bool fis_start = pr->cmd & PORT_CMD_FIS_RX; |
| 245 | bool fis_on = pr->cmd & PORT_CMD_FIS_ON; |
| 246 | |
| 247 | if (cmd_start && !cmd_on) { |
| 248 | if (!ahci_map_clb_address(ad)) { |
| 249 | pr->cmd &= ~PORT_CMD_START; |
| 250 | error_report("AHCI: Failed to start DMA engine: " |
| 251 | "bad command list buffer address"); |
| 252 | return -1; |
| 253 | } |
| 254 | } else if (!cmd_start && cmd_on) { |
| 255 | ahci_unmap_clb_address(ad); |
| 256 | } |
| 257 | |
| 258 | if (fis_start && !fis_on) { |
| 259 | if (!ahci_map_fis_address(ad)) { |
| 260 | pr->cmd &= ~PORT_CMD_FIS_RX; |
| 261 | error_report("AHCI: Failed to start FIS receive engine: " |
| 262 | "bad FIS receive buffer address"); |
| 263 | return -1; |
| 264 | } |
| 265 | } else if (!fis_start && fis_on) { |
| 266 | ahci_unmap_fis_address(ad); |
| 267 | } |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) |
| 273 | { |
| 274 | AHCIPortRegs *pr = &s->dev[port].port_regs; |
| 275 | enum AHCIPortReg regnum = offset / sizeof(uint32_t); |
| 276 | assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); |
| 277 | trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); |
| 278 | |
| 279 | switch (regnum) { |
| 280 | case AHCI_PORT_REG_LST_ADDR: |
| 281 | pr->lst_addr = val; |
| 282 | break; |
| 283 | case AHCI_PORT_REG_LST_ADDR_HI: |
| 284 | pr->lst_addr_hi = val; |
| 285 | break; |
| 286 | case AHCI_PORT_REG_FIS_ADDR: |
| 287 | pr->fis_addr = val; |
| 288 | break; |
| 289 | case AHCI_PORT_REG_FIS_ADDR_HI: |
| 290 | pr->fis_addr_hi = val; |
| 291 | break; |
| 292 | case AHCI_PORT_REG_IRQ_STAT: |
| 293 | pr->irq_stat &= ~val; |
| 294 | ahci_check_irq(s); |
| 295 | break; |
| 296 | case AHCI_PORT_REG_IRQ_MASK: |
| 297 | pr->irq_mask = val & 0xfdc000ff; |
| 298 | ahci_check_irq(s); |
| 299 | break; |
| 300 | case AHCI_PORT_REG_CMD: |
| 301 | if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { |
| 302 | pr->scr_act = 0; |
| 303 | pr->cmd_issue = 0; |
| 304 | } |
| 305 | |
| 306 | /* Block any Read-only fields from being set; |
| 307 | * including LIST_ON and FIS_ON. |
| 308 | * The spec requires to set ICC bits to zero after the ICC change |
| 309 | * is done. We don't support ICC state changes, therefore always |
| 310 | * force the ICC bits to zero. |
| 311 | */ |
| 312 | pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | |
| 313 | (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); |
| 314 | |
| 315 | /* Check FIS RX and CLB engines */ |
| 316 | ahci_cond_start_engines(&s->dev[port]); |
| 317 | |
| 318 | /* XXX usually the FIS would be pending on the bus here and |
| 319 | issuing deferred until the OS enables FIS receival. |
| 320 | Instead, we only submit it once - which works in most |
| 321 | cases, but is a hack. */ |
| 322 | if ((pr->cmd & PORT_CMD_FIS_ON) && |
| 323 | !s->dev[port].init_d2h_sent) { |
| 324 | ahci_init_d2h(&s->dev[port]); |
| 325 | } |
| 326 | |
| 327 | check_cmd(s, port); |
| 328 | break; |
| 329 | case AHCI_PORT_REG_TFDATA: |
| 330 | case AHCI_PORT_REG_SIG: |
| 331 | case AHCI_PORT_REG_SCR_STAT: |
| 332 | /* Read Only */ |
| 333 | break; |
| 334 | case AHCI_PORT_REG_SCR_CTL: |
| 335 | if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && |
| 336 | ((val & AHCI_SCR_SCTL_DET) == 0)) { |
| 337 | ahci_reset_port(s, port, IDE_RESET_HARDWARE); |
| 338 | } |
| 339 | pr->scr_ctl = val; |
| 340 | break; |
| 341 | case AHCI_PORT_REG_SCR_ERR: |
| 342 | pr->scr_err &= ~val; |
| 343 | break; |
| 344 | case AHCI_PORT_REG_SCR_ACT: |
| 345 | /* RW1 */ |
| 346 | pr->scr_act |= val; |
| 347 | break; |
| 348 | case AHCI_PORT_REG_CMD_ISSUE: |
| 349 | pr->cmd_issue |= val; |
| 350 | check_cmd(s, port); |
| 351 | break; |
| 352 | default: |
| 353 | trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], |
| 354 | offset, val); |
| 355 | qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " |
| 356 | "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, |
| 357 | port, AHCIPortReg_lookup[regnum], offset, val); |
| 358 | break; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) |
| 363 | { |
| 364 | AHCIState *s = opaque; |
| 365 | uint32_t val = 0; |
| 366 | |
| 367 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { |
| 368 | enum AHCIHostReg regnum = addr / 4; |
| 369 | assert(regnum < AHCI_HOST_REG__COUNT); |
| 370 | |
| 371 | switch (regnum) { |
| 372 | case AHCI_HOST_REG_CAP: |
| 373 | val = s->control_regs.cap; |
| 374 | break; |
| 375 | case AHCI_HOST_REG_CTL: |
| 376 | val = s->control_regs.ghc; |
| 377 | break; |
| 378 | case AHCI_HOST_REG_IRQ_STAT: |
| 379 | val = s->control_regs.irqstatus; |
| 380 | break; |
| 381 | case AHCI_HOST_REG_PORTS_IMPL: |
| 382 | val = s->control_regs.impl; |
| 383 | break; |
| 384 | case AHCI_HOST_REG_VERSION: |
| 385 | val = s->control_regs.version; |
| 386 | break; |
| 387 | default: |
| 388 | trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], |
| 389 | addr); |
| 390 | } |
| 391 | trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); |
| 392 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && |
| 393 | (addr < (AHCI_PORT_REGS_START_ADDR + |
| 394 | (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { |
| 395 | val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, |
| 396 | addr & AHCI_PORT_ADDR_OFFSET_MASK); |
| 397 | } else { |
| 398 | trace_ahci_mem_read_32_default(s, addr, val); |
| 399 | } |
| 400 | |
| 401 | trace_ahci_mem_read_32(s, addr, val); |
| 402 | return val; |
| 403 | } |
| 404 | |
| 405 | |
| 406 | /** |
| 407 | * AHCI 1.3 section 3 ("HBA Memory Registers") |
| 408 | * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. |
| 409 | * Caller is responsible for masking unwanted higher order bytes. |
| 410 | */ |
| 411 | static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) |
| 412 | { |
| 413 | hwaddr aligned = addr & ~0x3; |
| 414 | int ofst = addr - aligned; |
| 415 | uint64_t lo = ahci_mem_read_32(opaque, aligned); |
| 416 | uint64_t hi; |
| 417 | uint64_t val; |
| 418 | |
| 419 | /* if < 8 byte read does not cross 4 byte boundary */ |
| 420 | if (ofst + size <= 4) { |
| 421 | val = lo >> (ofst * 8); |
| 422 | } else { |
| 423 | g_assert(size > 1); |
| 424 | |
| 425 | /* If the 64bit read is unaligned, we will produce undefined |
| 426 | * results. AHCI does not support unaligned 64bit reads. */ |
| 427 | hi = ahci_mem_read_32(opaque, aligned + 4); |
| 428 | val = (hi << 32 | lo) >> (ofst * 8); |
| 429 | } |
| 430 | |
| 431 | trace_ahci_mem_read(opaque, size, addr, val); |
| 432 | return val; |
| 433 | } |
| 434 | |
| 435 | |
| 436 | static void ahci_mem_write(void *opaque, hwaddr addr, |
| 437 | uint64_t val, unsigned size) |
| 438 | { |
| 439 | AHCIState *s = opaque; |
| 440 | |
| 441 | trace_ahci_mem_write(s, size, addr, val); |
| 442 | |
| 443 | /* Only aligned reads are allowed on AHCI */ |
| 444 | if (addr & 3) { |
| 445 | qemu_log_mask(LOG_GUEST_ERROR, |
| 446 | "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", |
| 447 | addr); |
| 448 | return; |
| 449 | } |
| 450 | |
| 451 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { |
| 452 | enum AHCIHostReg regnum = addr / 4; |
| 453 | assert(regnum < AHCI_HOST_REG__COUNT); |
| 454 | |
| 455 | switch (regnum) { |
| 456 | case AHCI_HOST_REG_CAP: /* R/WO, RO */ |
| 457 | /* FIXME handle R/WO */ |
| 458 | break; |
| 459 | case AHCI_HOST_REG_CTL: /* R/W */ |
| 460 | if (val & HOST_CTL_RESET) { |
| 461 | ahci_reset(s); |
| 462 | } else { |
| 463 | s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; |
| 464 | ahci_check_irq(s); |
| 465 | } |
| 466 | break; |
| 467 | case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ |
| 468 | s->control_regs.irqstatus &= ~val; |
| 469 | ahci_check_irq(s); |
| 470 | break; |
| 471 | case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ |
| 472 | /* FIXME handle R/WO */ |
| 473 | break; |
| 474 | case AHCI_HOST_REG_VERSION: /* RO */ |
| 475 | /* FIXME report write? */ |
| 476 | break; |
| 477 | default: |
| 478 | qemu_log_mask(LOG_UNIMP, |
| 479 | "Attempted write to unimplemented register: " |
| 480 | "AHCI host register %s, " |
| 481 | "offset 0x%"PRIx64": 0x%"PRIx64, |
| 482 | AHCIHostReg_lookup[regnum], addr, val); |
| 483 | trace_ahci_mem_write_host_unimpl(s, size, |
| 484 | AHCIHostReg_lookup[regnum], addr); |
| 485 | } |
| 486 | trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], |
| 487 | addr, val); |
| 488 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && |
| 489 | (addr < (AHCI_PORT_REGS_START_ADDR + |
| 490 | (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { |
| 491 | ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, |
| 492 | addr & AHCI_PORT_ADDR_OFFSET_MASK, val); |
| 493 | } else { |
| 494 | qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " |
| 495 | "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, |
| 496 | addr, val); |
| 497 | trace_ahci_mem_write_unimpl(s, size, addr, val); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static const MemoryRegionOps ahci_mem_ops = { |
| 502 | .read = ahci_mem_read, |
| 503 | .write = ahci_mem_write, |
| 504 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 505 | }; |
| 506 | |
| 507 | static uint64_t ahci_idp_read(void *opaque, hwaddr addr, |
| 508 | unsigned size) |
| 509 | { |
| 510 | AHCIState *s = opaque; |
| 511 | |
| 512 | if (addr == s->idp_offset) { |
| 513 | /* index register */ |
| 514 | return s->idp_index; |
| 515 | } else if (addr == s->idp_offset + 4) { |
| 516 | /* data register - do memory read at location selected by index */ |
| 517 | return ahci_mem_read(opaque, s->idp_index, size); |
| 518 | } else { |
| 519 | return 0; |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void ahci_idp_write(void *opaque, hwaddr addr, |
| 524 | uint64_t val, unsigned size) |
| 525 | { |
| 526 | AHCIState *s = opaque; |
| 527 | |
| 528 | if (addr == s->idp_offset) { |
| 529 | /* index register - mask off reserved bits */ |
| 530 | s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); |
| 531 | } else if (addr == s->idp_offset + 4) { |
| 532 | /* data register - do memory write at location selected by index */ |
| 533 | ahci_mem_write(opaque, s->idp_index, val, size); |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | static const MemoryRegionOps ahci_idp_ops = { |
| 538 | .read = ahci_idp_read, |
| 539 | .write = ahci_idp_write, |
| 540 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 541 | }; |
| 542 | |
| 543 | |
| 544 | static void ahci_reg_init(AHCIState *s) |
| 545 | { |
| 546 | int i; |
| 547 | |
| 548 | s->control_regs.cap = (s->ports - 1) | |
| 549 | (AHCI_NUM_COMMAND_SLOTS << 8) | |
| 550 | (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | |
| 551 | HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; |
| 552 | |
| 553 | s->control_regs.impl = (1 << s->ports) - 1; |
| 554 | |
| 555 | s->control_regs.version = AHCI_VERSION_1_0; |
| 556 | |
| 557 | for (i = 0; i < s->ports; i++) { |
| 558 | s->dev[i].port_state = STATE_RUN; |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | static void check_cmd(AHCIState *s, int port) |
| 563 | { |
| 564 | AHCIPortRegs *pr = &s->dev[port].port_regs; |
| 565 | uint8_t slot; |
| 566 | |
| 567 | if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { |
| 568 | for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { |
| 569 | if (pr->cmd_issue & (1U << slot)) { |
| 570 | handle_cmd(s, port, slot); |
| 571 | } |
| 572 | } |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | static void ahci_check_cmd_bh(void *opaque) |
| 577 | { |
| 578 | AHCIDevice *ad = opaque; |
| 579 | |
| 580 | qemu_bh_delete(ad->check_bh); |
| 581 | ad->check_bh = NULL; |
| 582 | |
| 583 | check_cmd(ad->hba, ad->port_no); |
| 584 | } |
| 585 | |
| 586 | static void ahci_init_d2h(AHCIDevice *ad) |
| 587 | { |
| 588 | IDEState *ide_state = &ad->port.ifs[0]; |
| 589 | AHCIPortRegs *pr = &ad->port_regs; |
| 590 | |
| 591 | if (ad->init_d2h_sent) { |
| 592 | return; |
| 593 | } |
| 594 | |
| 595 | /* |
| 596 | * For simplicity, do not call ahci_clear_cmd_issue() for this |
| 597 | * ahci_write_fis_d2h(). (The reset value for PxCI is 0.) |
| 598 | */ |
| 599 | if (ahci_write_fis_d2h(ad, true)) { |
| 600 | ad->init_d2h_sent = true; |
| 601 | /* We're emulating receiving the first Reg D2H FIS from the device; |
| 602 | * Update the SIG register, but otherwise proceed as normal. */ |
| 603 | pr->sig = ((uint32_t)ide_state->hcyl << 24) | |
| 604 | (ide_state->lcyl << 16) | |
| 605 | (ide_state->sector << 8) | |
| 606 | (ide_state->nsector & 0xFF); |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) |
| 611 | { |
| 612 | IDEState *s = &ad->port.ifs[0]; |
| 613 | s->hcyl = sig >> 24 & 0xFF; |
| 614 | s->lcyl = sig >> 16 & 0xFF; |
| 615 | s->sector = sig >> 8 & 0xFF; |
| 616 | s->nsector = sig & 0xFF; |
| 617 | |
| 618 | trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, |
| 619 | s->lcyl, s->hcyl, sig); |
| 620 | } |
| 621 | |
| 622 | static void ahci_cancel_ncq_requests(AHCIDevice *ad) |
| 623 | { |
| 624 | int i; |
| 625 | |
| 626 | for (i = 0; i < AHCI_MAX_CMDS; i++) { |
| 627 | NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; |
| 628 | ncq_tfs->halt = false; |
| 629 | if (!ncq_tfs->used) { |
| 630 | continue; |
| 631 | } |
| 632 | |
| 633 | if (ncq_tfs->aiocb) { |
| 634 | blk_aio_cancel(ncq_tfs->aiocb); |
| 635 | ncq_tfs->aiocb = NULL; |
| 636 | } |
| 637 | |
| 638 | /* Maybe we just finished the request thanks to blk_aio_cancel() */ |
| 639 | if (!ncq_tfs->used) { |
| 640 | continue; |
| 641 | } |
| 642 | |
| 643 | qemu_sglist_destroy(&ncq_tfs->sglist); |
| 644 | ncq_tfs->used = 0; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | static void ahci_reset_port(AHCIState *s, int port, IDEResetKind kind) |
| 649 | { |
| 650 | AHCIDevice *d = &s->dev[port]; |
| 651 | AHCIPortRegs *pr = &d->port_regs; |
| 652 | IDEState *ide_state = &d->port.ifs[0]; |
| 653 | |
| 654 | trace_ahci_reset_port(s, port); |
| 655 | |
| 656 | ide_bus_reset(&d->port, kind); |
| 657 | ide_state->ncq_queues = AHCI_MAX_CMDS; |
| 658 | |
| 659 | pr->scr_stat = 0; |
| 660 | pr->scr_err = 0; |
| 661 | pr->scr_act = 0; |
| 662 | pr->tfdata = 0x7F; |
| 663 | pr->sig = 0xFFFFFFFF; |
| 664 | pr->cmd_issue = 0; |
| 665 | d->busy_slot = -1; |
| 666 | d->init_d2h_sent = false; |
| 667 | |
| 668 | ide_state = &s->dev[port].port.ifs[0]; |
| 669 | if (!ide_state->blk) { |
| 670 | return; |
| 671 | } |
| 672 | |
| 673 | ahci_cancel_ncq_requests(d); |
| 674 | |
| 675 | s->dev[port].port_state = STATE_RUN; |
| 676 | if (ide_state->drive_kind == IDE_CD) { |
| 677 | ahci_set_signature(d, SATA_SIGNATURE_CDROM); |
| 678 | ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; |
| 679 | } else { |
| 680 | ahci_set_signature(d, SATA_SIGNATURE_DISK); |
| 681 | ide_state->status = SEEK_STAT | WRERR_STAT; |
| 682 | } |
| 683 | |
| 684 | ide_state->error = 1; |
| 685 | ahci_init_d2h(d); |
| 686 | } |
| 687 | |
| 688 | /* Buffer pretty output based on a raw FIS structure. */ |
| 689 | static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) |
| 690 | { |
| 691 | int i; |
| 692 | GString *s = g_string_new("FIS:"); |
| 693 | |
| 694 | for (i = 0; i < cmd_len; i++) { |
| 695 | if ((i & 0xf) == 0) { |
| 696 | g_string_append_printf(s, "\n0x%02x: ", i); |
| 697 | } |
| 698 | g_string_append_printf(s, "%02x ", fis[i]); |
| 699 | } |
| 700 | g_string_append_c(s, '\n'); |
| 701 | |
| 702 | return g_string_free(s, FALSE); |
| 703 | } |
| 704 | |
| 705 | static bool ahci_map_fis_address(AHCIDevice *ad) |
| 706 | { |
| 707 | AHCIPortRegs *pr = &ad->port_regs; |
| 708 | map_page(ad->hba->as, &ad->res_fis, |
| 709 | ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); |
| 710 | if (ad->res_fis != NULL) { |
| 711 | pr->cmd |= PORT_CMD_FIS_ON; |
| 712 | return true; |
| 713 | } |
| 714 | |
| 715 | pr->cmd &= ~PORT_CMD_FIS_ON; |
| 716 | return false; |
| 717 | } |
| 718 | |
| 719 | static void ahci_unmap_fis_address(AHCIDevice *ad) |
| 720 | { |
| 721 | if (ad->res_fis == NULL) { |
| 722 | trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); |
| 723 | return; |
| 724 | } |
| 725 | ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; |
| 726 | dma_memory_unmap(ad->hba->as, ad->res_fis, 256, |
| 727 | DMA_DIRECTION_FROM_DEVICE, 256); |
| 728 | ad->res_fis = NULL; |
| 729 | } |
| 730 | |
| 731 | static bool ahci_map_clb_address(AHCIDevice *ad) |
| 732 | { |
| 733 | AHCIPortRegs *pr = &ad->port_regs; |
| 734 | ad->cur_cmd = NULL; |
| 735 | map_page(ad->hba->as, &ad->lst, |
| 736 | ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); |
| 737 | if (ad->lst != NULL) { |
| 738 | pr->cmd |= PORT_CMD_LIST_ON; |
| 739 | return true; |
| 740 | } |
| 741 | |
| 742 | pr->cmd &= ~PORT_CMD_LIST_ON; |
| 743 | return false; |
| 744 | } |
| 745 | |
| 746 | static void ahci_unmap_clb_address(AHCIDevice *ad) |
| 747 | { |
| 748 | /* Cancel in-flight reads that would complete against a cleared cur_cmd. */ |
| 749 | ide_cancel_dma_sync(ide_bus_active_if(&ad->port)); |
| 750 | |
| 751 | /* |
| 752 | * Whatever survives the cancel must not be left pointing into the |
| 753 | * mapping this function is about to drop. |
| 754 | */ |
| 755 | ad->cur_cmd = NULL; |
| 756 | |
| 757 | if (ad->lst == NULL) { |
| 758 | trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); |
| 759 | return; |
| 760 | } |
| 761 | ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; |
| 762 | dma_memory_unmap(ad->hba->as, ad->lst, 1024, |
| 763 | DMA_DIRECTION_FROM_DEVICE, 1024); |
| 764 | ad->lst = NULL; |
| 765 | } |
| 766 | |
| 767 | static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) |
| 768 | { |
| 769 | AHCIDevice *ad = ncq_tfs->drive; |
| 770 | AHCIPortRegs *pr = &ad->port_regs; |
| 771 | IDEState *ide_state; |
| 772 | SDBFIS *sdb_fis; |
| 773 | |
| 774 | if (!ad->res_fis || |
| 775 | !(pr->cmd & PORT_CMD_FIS_RX)) { |
| 776 | return; |
| 777 | } |
| 778 | |
| 779 | sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; |
| 780 | ide_state = &ad->port.ifs[0]; |
| 781 | |
| 782 | sdb_fis->type = SATA_FIS_TYPE_SDB; |
| 783 | /* Interrupt pending & Notification bit */ |
| 784 | sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ |
| 785 | sdb_fis->status = ide_state->status & 0x77; |
| 786 | sdb_fis->error = ide_state->error; |
| 787 | /* update SAct field in SDB_FIS */ |
| 788 | sdb_fis->payload = cpu_to_le32(ad->finished); |
| 789 | |
| 790 | /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ |
| 791 | pr->tfdata = (ad->port.ifs[0].error << 8) | |
| 792 | (ad->port.ifs[0].status & 0x77) | |
| 793 | (pr->tfdata & 0x88); |
| 794 | pr->scr_act &= ~ad->finished; |
| 795 | ad->finished = 0; |
| 796 | |
| 797 | /* |
| 798 | * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. |
| 799 | * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set |
| 800 | * (which currently, it always is). |
| 801 | */ |
| 802 | if (sdb_fis->status & ERR_STAT) { |
| 803 | ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES); |
| 804 | } else if (sdb_fis->flags & 0x40) { |
| 805 | ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) |
| 810 | { |
| 811 | AHCIPortRegs *pr = &ad->port_regs; |
| 812 | uint8_t *pio_fis; |
| 813 | IDEState *s = &ad->port.ifs[0]; |
| 814 | |
| 815 | if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { |
| 816 | return; |
| 817 | } |
| 818 | |
| 819 | pio_fis = &ad->res_fis[RES_FIS_PSFIS]; |
| 820 | |
| 821 | pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; |
| 822 | pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); |
| 823 | pio_fis[2] = s->status; |
| 824 | pio_fis[3] = s->error; |
| 825 | |
| 826 | pio_fis[4] = s->sector; |
| 827 | pio_fis[5] = s->lcyl; |
| 828 | pio_fis[6] = s->hcyl; |
| 829 | pio_fis[7] = s->select; |
| 830 | pio_fis[8] = s->hob_sector; |
| 831 | pio_fis[9] = s->hob_lcyl; |
| 832 | pio_fis[10] = s->hob_hcyl; |
| 833 | pio_fis[11] = 0; |
| 834 | pio_fis[12] = s->nsector & 0xFF; |
| 835 | pio_fis[13] = (s->nsector >> 8) & 0xFF; |
| 836 | pio_fis[14] = 0; |
| 837 | pio_fis[15] = s->status; |
| 838 | pio_fis[16] = len & 255; |
| 839 | pio_fis[17] = len >> 8; |
| 840 | pio_fis[18] = 0; |
| 841 | pio_fis[19] = 0; |
| 842 | |
| 843 | /* Update shadow registers: */ |
| 844 | pr->tfdata = (ad->port.ifs[0].error << 8) | |
| 845 | ad->port.ifs[0].status; |
| 846 | |
| 847 | if (pio_fis[2] & ERR_STAT) { |
| 848 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) |
| 853 | { |
| 854 | AHCIPortRegs *pr = &ad->port_regs; |
| 855 | uint8_t *d2h_fis; |
| 856 | int i; |
| 857 | IDEState *s = &ad->port.ifs[0]; |
| 858 | |
| 859 | if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { |
| 860 | return false; |
| 861 | } |
| 862 | |
| 863 | d2h_fis = &ad->res_fis[RES_FIS_RFIS]; |
| 864 | |
| 865 | d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; |
| 866 | d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ |
| 867 | d2h_fis[2] = s->status; |
| 868 | d2h_fis[3] = s->error; |
| 869 | |
| 870 | d2h_fis[4] = s->sector; |
| 871 | d2h_fis[5] = s->lcyl; |
| 872 | d2h_fis[6] = s->hcyl; |
| 873 | d2h_fis[7] = s->select; |
| 874 | d2h_fis[8] = s->hob_sector; |
| 875 | d2h_fis[9] = s->hob_lcyl; |
| 876 | d2h_fis[10] = s->hob_hcyl; |
| 877 | d2h_fis[11] = 0; |
| 878 | d2h_fis[12] = s->nsector & 0xFF; |
| 879 | d2h_fis[13] = (s->nsector >> 8) & 0xFF; |
| 880 | for (i = 14; i < 20; i++) { |
| 881 | d2h_fis[i] = 0; |
| 882 | } |
| 883 | |
| 884 | /* Update shadow registers: */ |
| 885 | pr->tfdata = (ad->port.ifs[0].error << 8) | |
| 886 | ad->port.ifs[0].status; |
| 887 | |
| 888 | /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ |
| 889 | if (d2h_fis[2] & ERR_STAT) { |
| 890 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); |
| 891 | } else if (d2h_fis_i) { |
| 892 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); |
| 893 | } |
| 894 | |
| 895 | return true; |
| 896 | } |
| 897 | |
| 898 | static int prdt_tbl_entry_size(const AHCI_SG *tbl) |
| 899 | { |
| 900 | /* flags_size is zero-based */ |
| 901 | return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; |
| 902 | } |
| 903 | |
| 904 | /** |
| 905 | * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. |
| 906 | * @ad: The AHCIDevice for whom we are building the SGList. |
| 907 | * @sglist: The SGList target to add PRD entries to. |
| 908 | * @cmd: The AHCI Command Header that describes where the PRDT is. |
| 909 | * @limit: The remaining size of the S/ATA transaction, in bytes. |
| 910 | * @offset: The number of bytes already transferred, in bytes. |
| 911 | * |
| 912 | * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of |
| 913 | * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop |
| 914 | * building the sglist from the PRDT as soon as we hit @limit bytes, |
| 915 | * which is <= INT32_MAX/2GiB. |
| 916 | */ |
| 917 | static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, |
| 918 | AHCICmdHdr *cmd, int64_t limit, uint64_t offset) |
| 919 | { |
| 920 | uint16_t opts; |
| 921 | uint16_t prdtl; |
| 922 | uint64_t cfis_addr; |
| 923 | uint64_t prdt_addr; |
| 924 | dma_addr_t prdt_len; |
| 925 | dma_addr_t real_prdt_len; |
| 926 | uint8_t *prdt; |
| 927 | int i; |
| 928 | int r = 0; |
| 929 | uint64_t sum = 0; |
| 930 | int off_idx = -1; |
| 931 | int64_t off_pos = -1; |
| 932 | IDEBus *bus = &ad->port; |
| 933 | BusState *qbus = BUS(bus); |
| 934 | |
| 935 | trace_ahci_populate_sglist(ad->hba, ad->port_no); |
| 936 | |
| 937 | if (!cmd) { |
| 938 | trace_ahci_populate_sglist_no_cmd(ad->hba, ad->port_no); |
| 939 | return -1; |
| 940 | } |
| 941 | |
| 942 | opts = le16_to_cpu(cmd->opts); |
| 943 | prdtl = le16_to_cpu(cmd->prdtl); |
| 944 | cfis_addr = le64_to_cpu(cmd->tbl_addr); |
| 945 | prdt_addr = cfis_addr + 0x80; |
| 946 | prdt_len = (prdtl * sizeof(AHCI_SG)); |
| 947 | real_prdt_len = prdt_len; |
| 948 | |
| 949 | if (!prdtl) { |
| 950 | trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); |
| 951 | return -1; |
| 952 | } |
| 953 | |
| 954 | /* map PRDT */ |
| 955 | if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, |
| 956 | DMA_DIRECTION_TO_DEVICE, |
| 957 | MEMTXATTRS_UNSPECIFIED))){ |
| 958 | trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); |
| 959 | return -1; |
| 960 | } |
| 961 | |
| 962 | if (prdt_len < real_prdt_len) { |
| 963 | trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); |
| 964 | r = -1; |
| 965 | goto out; |
| 966 | } |
| 967 | |
| 968 | /* Get entries in the PRDT, init a qemu sglist accordingly */ |
| 969 | if (prdtl > 0) { |
| 970 | AHCI_SG *tbl = (AHCI_SG *)prdt; |
| 971 | int tbl_entry_size = 0; |
| 972 | |
| 973 | sum = 0; |
| 974 | for (i = 0; i < prdtl; i++) { |
| 975 | tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); |
| 976 | if (offset < (sum + tbl_entry_size)) { |
| 977 | off_idx = i; |
| 978 | off_pos = offset - sum; |
| 979 | break; |
| 980 | } |
| 981 | sum += tbl_entry_size; |
| 982 | } |
| 983 | if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { |
| 984 | trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, |
| 985 | off_idx, off_pos); |
| 986 | r = -1; |
| 987 | goto out; |
| 988 | } |
| 989 | |
| 990 | qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), |
| 991 | ad->hba->as); |
| 992 | qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, |
| 993 | MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, |
| 994 | limit)); |
| 995 | |
| 996 | for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { |
| 997 | qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), |
| 998 | MIN(prdt_tbl_entry_size(&tbl[i]), |
| 999 | limit - sglist->size)); |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | out: |
| 1004 | dma_memory_unmap(ad->hba->as, prdt, prdt_len, |
| 1005 | DMA_DIRECTION_TO_DEVICE, prdt_len); |
| 1006 | return r; |
| 1007 | } |
| 1008 | |
| 1009 | static void ncq_err(NCQTransferState *ncq_tfs) |
| 1010 | { |
| 1011 | IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; |
| 1012 | |
| 1013 | ide_state->error = ABRT_ERR; |
| 1014 | ide_state->status = READY_STAT | ERR_STAT; |
| 1015 | qemu_sglist_destroy(&ncq_tfs->sglist); |
| 1016 | ncq_tfs->used = 0; |
| 1017 | } |
| 1018 | |
| 1019 | static void ncq_finish(NCQTransferState *ncq_tfs) |
| 1020 | { |
| 1021 | /* If we didn't error out, set our finished bit. Errored commands |
| 1022 | * do not get a bit set for the SDB FIS ACT register, nor do they |
| 1023 | * clear the outstanding bit in scr_act (PxSACT). */ |
| 1024 | if (ncq_tfs->used) { |
| 1025 | ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); |
| 1026 | } |
| 1027 | |
| 1028 | ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); |
| 1029 | |
| 1030 | trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, |
| 1031 | ncq_tfs->tag); |
| 1032 | |
| 1033 | block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), |
| 1034 | &ncq_tfs->acct); |
| 1035 | qemu_sglist_destroy(&ncq_tfs->sglist); |
| 1036 | ncq_tfs->used = 0; |
| 1037 | } |
| 1038 | |
| 1039 | static void ncq_cb(void *opaque, int ret) |
| 1040 | { |
| 1041 | NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; |
| 1042 | IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; |
| 1043 | |
| 1044 | ncq_tfs->aiocb = NULL; |
| 1045 | |
| 1046 | if (ret < 0) { |
| 1047 | bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; |
| 1048 | BlockErrorAction action = blk_get_error_action(ide_state->blk, |
| 1049 | is_read, -ret); |
| 1050 | if (action == BLOCK_ERROR_ACTION_STOP) { |
| 1051 | ncq_tfs->halt = true; |
| 1052 | ide_state->bus->error_status = IDE_RETRY_HBA; |
| 1053 | } else if (action == BLOCK_ERROR_ACTION_REPORT) { |
| 1054 | ncq_err(ncq_tfs); |
| 1055 | } |
| 1056 | blk_error_action(ide_state->blk, action, is_read, -ret); |
| 1057 | } else { |
| 1058 | ide_state->status = READY_STAT | SEEK_STAT; |
| 1059 | } |
| 1060 | |
| 1061 | if (!ncq_tfs->halt) { |
| 1062 | ncq_finish(ncq_tfs); |
| 1063 | } |
| 1064 | } |
| 1065 | |
| 1066 | static int is_ncq(uint8_t ata_cmd) |
| 1067 | { |
| 1068 | /* Based on SATA 3.2 section 13.6.3.2 */ |
| 1069 | switch (ata_cmd) { |
| 1070 | case READ_FPDMA_QUEUED: |
| 1071 | case WRITE_FPDMA_QUEUED: |
| 1072 | case NCQ_NON_DATA: |
| 1073 | case RECEIVE_FPDMA_QUEUED: |
| 1074 | case SEND_FPDMA_QUEUED: |
| 1075 | return 1; |
| 1076 | default: |
| 1077 | return 0; |
| 1078 | } |
| 1079 | } |
| 1080 | |
| 1081 | static void execute_ncq_command(NCQTransferState *ncq_tfs) |
| 1082 | { |
| 1083 | AHCIDevice *ad = ncq_tfs->drive; |
| 1084 | IDEState *ide_state = &ad->port.ifs[0]; |
| 1085 | int port = ad->port_no; |
| 1086 | |
| 1087 | g_assert(is_ncq(ncq_tfs->cmd)); |
| 1088 | ncq_tfs->halt = false; |
| 1089 | |
| 1090 | switch (ncq_tfs->cmd) { |
| 1091 | case READ_FPDMA_QUEUED: |
| 1092 | trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, |
| 1093 | ncq_tfs->sector_count, ncq_tfs->lba); |
| 1094 | dma_acct_start(ide_state->blk, &ncq_tfs->acct, |
| 1095 | &ncq_tfs->sglist, BLOCK_ACCT_READ); |
| 1096 | ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, |
| 1097 | ncq_tfs->lba << BDRV_SECTOR_BITS, |
| 1098 | BDRV_SECTOR_SIZE, |
| 1099 | ncq_cb, ncq_tfs); |
| 1100 | break; |
| 1101 | case WRITE_FPDMA_QUEUED: |
| 1102 | trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag, |
| 1103 | ncq_tfs->sector_count, ncq_tfs->lba); |
| 1104 | dma_acct_start(ide_state->blk, &ncq_tfs->acct, |
| 1105 | &ncq_tfs->sglist, BLOCK_ACCT_WRITE); |
| 1106 | ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, |
| 1107 | ncq_tfs->lba << BDRV_SECTOR_BITS, |
| 1108 | BDRV_SECTOR_SIZE, |
| 1109 | ncq_cb, ncq_tfs); |
| 1110 | break; |
| 1111 | default: |
| 1112 | trace_execute_ncq_command_unsup(ad->hba, port, |
| 1113 | ncq_tfs->tag, ncq_tfs->cmd); |
| 1114 | ncq_err(ncq_tfs); |
| 1115 | } |
| 1116 | } |
| 1117 | |
| 1118 | |
| 1119 | static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, |
| 1120 | uint8_t slot) |
| 1121 | { |
| 1122 | AHCIDevice *ad = &s->dev[port]; |
| 1123 | const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; |
| 1124 | uint8_t tag = ncq_fis->tag >> 3; |
| 1125 | NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; |
| 1126 | size_t size; |
| 1127 | |
| 1128 | g_assert(is_ncq(ncq_fis->command)); |
| 1129 | if (ncq_tfs->used) { |
| 1130 | /* error - already in use */ |
| 1131 | qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", |
| 1132 | __func__, tag); |
| 1133 | return; |
| 1134 | } |
| 1135 | |
| 1136 | /* |
| 1137 | * A NCQ command clears the bit in PxCI after the command has been QUEUED |
| 1138 | * successfully (ERROR not set, BUSY and DRQ cleared). |
| 1139 | * |
| 1140 | * For NCQ commands, PxCI will always be cleared here. |
| 1141 | * |
| 1142 | * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with |
| 1143 | * the interrupt bit set, which will clear PxSACT and raise an interrupt.) |
| 1144 | */ |
| 1145 | ahci_clear_cmd_issue(ad, slot); |
| 1146 | |
| 1147 | /* |
| 1148 | * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS |
| 1149 | * without the interrupt bit set, but since ahci_write_fis_d2h() can raise |
| 1150 | * an IRQ on error, we need to call them in reverse order. |
| 1151 | */ |
| 1152 | ahci_write_fis_d2h(ad, false); |
| 1153 | |
| 1154 | ncq_tfs->used = 1; |
| 1155 | ncq_tfs->drive = ad; |
| 1156 | ncq_tfs->slot = slot; |
| 1157 | ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; |
| 1158 | ncq_tfs->cmd = ncq_fis->command; |
| 1159 | ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | |
| 1160 | ((uint64_t)ncq_fis->lba4 << 32) | |
| 1161 | ((uint64_t)ncq_fis->lba3 << 24) | |
| 1162 | ((uint64_t)ncq_fis->lba2 << 16) | |
| 1163 | ((uint64_t)ncq_fis->lba1 << 8) | |
| 1164 | (uint64_t)ncq_fis->lba0; |
| 1165 | ncq_tfs->tag = tag; |
| 1166 | |
| 1167 | /* Sanity-check the NCQ packet */ |
| 1168 | if (tag != slot) { |
| 1169 | trace_process_ncq_command_mismatch(s, port, tag, slot); |
| 1170 | } |
| 1171 | |
| 1172 | if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { |
| 1173 | trace_process_ncq_command_aux(s, port, tag); |
| 1174 | } |
| 1175 | if (ncq_fis->prio || ncq_fis->icc) { |
| 1176 | trace_process_ncq_command_prioicc(s, port, tag); |
| 1177 | } |
| 1178 | if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { |
| 1179 | trace_process_ncq_command_fua(s, port, tag); |
| 1180 | } |
| 1181 | if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { |
| 1182 | trace_process_ncq_command_rarc(s, port, tag); |
| 1183 | } |
| 1184 | |
| 1185 | ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | |
| 1186 | ncq_fis->sector_count_low); |
| 1187 | if (!ncq_tfs->sector_count) { |
| 1188 | ncq_tfs->sector_count = 0x10000; |
| 1189 | } |
| 1190 | size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; |
| 1191 | ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); |
| 1192 | |
| 1193 | if (ncq_tfs->sglist.size < size) { |
| 1194 | error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") " |
| 1195 | "is smaller than the requested size (0x%zx)", |
| 1196 | ncq_tfs->sglist.size, size); |
| 1197 | ncq_err(ncq_tfs); |
| 1198 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); |
| 1199 | return; |
| 1200 | } else if (ncq_tfs->sglist.size != size) { |
| 1201 | trace_process_ncq_command_large(s, port, tag, |
| 1202 | ncq_tfs->sglist.size, size); |
| 1203 | } |
| 1204 | |
| 1205 | trace_process_ncq_command(s, port, tag, |
| 1206 | ncq_fis->command, |
| 1207 | ncq_tfs->lba, |
| 1208 | ncq_tfs->lba + ncq_tfs->sector_count - 1); |
| 1209 | execute_ncq_command(ncq_tfs); |
| 1210 | } |
| 1211 | |
| 1212 | static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) |
| 1213 | { |
| 1214 | if (port >= s->ports || slot >= AHCI_MAX_CMDS) { |
| 1215 | return NULL; |
| 1216 | } |
| 1217 | |
| 1218 | return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; |
| 1219 | } |
| 1220 | |
| 1221 | static void handle_reg_h2d_fis(AHCIState *s, int port, |
| 1222 | uint8_t slot, const uint8_t *cmd_fis) |
| 1223 | { |
| 1224 | IDEState *ide_state = &s->dev[port].port.ifs[0]; |
| 1225 | AHCICmdHdr *cmd = get_cmd_header(s, port, slot); |
| 1226 | AHCIDevice *ad = &s->dev[port]; |
| 1227 | uint16_t opts = le16_to_cpu(cmd->opts); |
| 1228 | |
| 1229 | if (cmd_fis[1] & 0x0F) { |
| 1230 | trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], |
| 1231 | cmd_fis[2], cmd_fis[3]); |
| 1232 | return; |
| 1233 | } |
| 1234 | |
| 1235 | if (cmd_fis[1] & 0x70) { |
| 1236 | trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], |
| 1237 | cmd_fis[2], cmd_fis[3]); |
| 1238 | return; |
| 1239 | } |
| 1240 | |
| 1241 | if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { |
| 1242 | switch (s->dev[port].port_state) { |
| 1243 | case STATE_RUN: |
| 1244 | if (cmd_fis[15] & ATA_SRST) { |
| 1245 | s->dev[port].port_state = STATE_RESET; |
| 1246 | /* |
| 1247 | * When setting SRST in the first H2D FIS in the reset sequence, |
| 1248 | * the device does not send a D2H FIS. Host software thus has to |
| 1249 | * set the "Clear Busy upon R_OK" bit such that PxCI (and BUSY) |
| 1250 | * gets cleared. See AHCI 1.3.1, section 10.4.1 Software Reset. |
| 1251 | */ |
| 1252 | if (opts & AHCI_CMD_CLR_BUSY) { |
| 1253 | ahci_clear_cmd_issue(ad, slot); |
| 1254 | } |
| 1255 | } |
| 1256 | break; |
| 1257 | case STATE_RESET: |
| 1258 | if (!(cmd_fis[15] & ATA_SRST)) { |
| 1259 | /* |
| 1260 | * When clearing SRST in the second H2D FIS in the reset |
| 1261 | * sequence, the device will execute diagnostics. When this is |
| 1262 | * done, the device will send a D2H FIS with the good status. |
| 1263 | * See SATA 3.5a Gold, section 11.4 Software reset protocol. |
| 1264 | * |
| 1265 | * This D2H FIS is the first D2H FIS received from the device, |
| 1266 | * and is received regardless if the reset was performed by a |
| 1267 | * COMRESET or by setting and clearing the SRST bit. Therefore, |
| 1268 | * the logic for this is found in ahci_init_d2h() and not here. |
| 1269 | */ |
| 1270 | ahci_reset_port(s, port, IDE_RESET_SOFTWARE); |
| 1271 | } |
| 1272 | break; |
| 1273 | } |
| 1274 | return; |
| 1275 | } |
| 1276 | |
| 1277 | /* Check for NCQ command */ |
| 1278 | if (is_ncq(cmd_fis[2])) { |
| 1279 | process_ncq_command(s, port, cmd_fis, slot); |
| 1280 | return; |
| 1281 | } |
| 1282 | |
| 1283 | /* Decompose the FIS: |
| 1284 | * AHCI does not interpret FIS packets, it only forwards them. |
| 1285 | * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. |
| 1286 | * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. |
| 1287 | * |
| 1288 | * ATA4 describes sector number for LBA28/CHS commands. |
| 1289 | * ATA6 describes sector number for LBA48 commands. |
| 1290 | * ATA8 deprecates CHS fully, describing only LBA28/48. |
| 1291 | * |
| 1292 | * We dutifully convert the FIS into IDE registers, and allow the |
| 1293 | * core layer to interpret them as needed. */ |
| 1294 | ide_state->feature = cmd_fis[3]; |
| 1295 | ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ |
| 1296 | ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ |
| 1297 | ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ |
| 1298 | ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ |
| 1299 | ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ |
| 1300 | ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ |
| 1301 | ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ |
| 1302 | ide_state->hob_feature = cmd_fis[11]; |
| 1303 | ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); |
| 1304 | /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ |
| 1305 | /* 15: Only valid when UPDATE_COMMAND not set. */ |
| 1306 | |
| 1307 | /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command |
| 1308 | * table to ide_state->io_buffer */ |
| 1309 | if (opts & AHCI_CMD_ATAPI) { |
| 1310 | memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); |
| 1311 | if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { |
| 1312 | char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); |
| 1313 | trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); |
| 1314 | g_free(pretty_fis); |
| 1315 | } |
| 1316 | } |
| 1317 | |
| 1318 | ide_state->error = 0; |
| 1319 | s->dev[port].done_first_drq = false; |
| 1320 | /* Reset transferred byte counter */ |
| 1321 | cmd->status = 0; |
| 1322 | |
| 1323 | /* |
| 1324 | * A non-NCQ command clears the bit in PxCI after the command has COMPLETED |
| 1325 | * successfully (ERROR not set, BUSY and DRQ cleared). |
| 1326 | * |
| 1327 | * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). |
| 1328 | */ |
| 1329 | ad->busy_slot = slot; |
| 1330 | |
| 1331 | /* We're ready to process the command in FIS byte 2. */ |
| 1332 | ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); |
| 1333 | } |
| 1334 | |
| 1335 | static void handle_cmd(AHCIState *s, int port, uint8_t slot) |
| 1336 | { |
| 1337 | IDEState *ide_state; |
| 1338 | uint64_t tbl_addr; |
| 1339 | AHCICmdHdr *cmd; |
| 1340 | uint8_t *cmd_fis; |
| 1341 | dma_addr_t cmd_len; |
| 1342 | uint8_t cfl; |
| 1343 | |
| 1344 | if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { |
| 1345 | /* Engine currently busy, try again later */ |
| 1346 | trace_handle_cmd_busy(s, port); |
| 1347 | return; |
| 1348 | } |
| 1349 | |
| 1350 | if (!s->dev[port].lst) { |
| 1351 | trace_handle_cmd_nolist(s, port); |
| 1352 | return; |
| 1353 | } |
| 1354 | cmd = get_cmd_header(s, port, slot); |
| 1355 | |
| 1356 | /* AHCI 1.3.1: a CFL below 2 dwords or above 16 is illegal */ |
| 1357 | cfl = le16_to_cpu(cmd->opts) & AHCI_CMD_HDR_CMD_FIS_LEN; |
| 1358 | if (cfl < 2 || cfl > 16) { |
| 1359 | trace_handle_cmd_badcfl(s, port, le16_to_cpu(cmd->opts)); |
| 1360 | return; |
| 1361 | } |
| 1362 | |
| 1363 | /* remember current slot handle for later */ |
| 1364 | s->dev[port].cur_cmd = cmd; |
| 1365 | |
| 1366 | /* The device we are working for */ |
| 1367 | ide_state = &s->dev[port].port.ifs[0]; |
| 1368 | if (!ide_state->blk) { |
| 1369 | trace_handle_cmd_badport(s, port); |
| 1370 | return; |
| 1371 | } |
| 1372 | |
| 1373 | tbl_addr = le64_to_cpu(cmd->tbl_addr); |
| 1374 | cmd_len = 0x80; |
| 1375 | cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, |
| 1376 | DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); |
| 1377 | if (!cmd_fis) { |
| 1378 | trace_handle_cmd_badfis(s, port); |
| 1379 | return; |
| 1380 | } else if (cmd_len != 0x80) { |
| 1381 | ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); |
| 1382 | trace_handle_cmd_badmap(s, port, cmd_len); |
| 1383 | goto out; |
| 1384 | } |
| 1385 | if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { |
| 1386 | char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); |
| 1387 | trace_handle_cmd_fis_dump(s, port, pretty_fis); |
| 1388 | g_free(pretty_fis); |
| 1389 | } |
| 1390 | switch (cmd_fis[0]) { |
| 1391 | case SATA_FIS_TYPE_REGISTER_H2D: |
| 1392 | handle_reg_h2d_fis(s, port, slot, cmd_fis); |
| 1393 | break; |
| 1394 | default: |
| 1395 | trace_handle_cmd_unhandled_fis(s, port, |
| 1396 | cmd_fis[0], cmd_fis[1], cmd_fis[2]); |
| 1397 | break; |
| 1398 | } |
| 1399 | |
| 1400 | out: |
| 1401 | dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, |
| 1402 | cmd_len); |
| 1403 | } |
| 1404 | |
| 1405 | /* Transfer PIO data between RAM and device */ |
| 1406 | static bool ahci_pio_transfer(const IDEDMA *dma) |
| 1407 | { |
| 1408 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1409 | IDEState *s = &ad->port.ifs[0]; |
| 1410 | uint32_t size = (uint32_t)(s->data_end - s->data_ptr); |
| 1411 | /* write == ram -> device */ |
| 1412 | uint16_t opts; |
| 1413 | int is_write; |
| 1414 | int is_atapi; |
| 1415 | int has_sglist = 0; |
| 1416 | bool pio_fis_i; |
| 1417 | |
| 1418 | if (ad->cur_cmd == NULL) { |
| 1419 | trace_ahci_pio_transfer_no_cmd(ad->hba, ad->port_no); |
| 1420 | return false; |
| 1421 | } |
| 1422 | |
| 1423 | opts = le16_to_cpu(ad->cur_cmd->opts); |
| 1424 | is_write = opts & AHCI_CMD_WRITE; |
| 1425 | is_atapi = opts & AHCI_CMD_ATAPI; |
| 1426 | |
| 1427 | /* The PIO Setup FIS is received prior to transfer, but the interrupt |
| 1428 | * is only triggered after data is received. |
| 1429 | * |
| 1430 | * The device only sets the 'I' bit in the PIO Setup FIS for device->host |
| 1431 | * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after |
| 1432 | * the first (see "DPIOO1"). The latter is consistent with the spec's |
| 1433 | * description of the PACKET protocol, where the command part of ATAPI requests |
| 1434 | * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests |
| 1435 | * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. |
| 1436 | */ |
| 1437 | pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); |
| 1438 | ahci_write_fis_pio(ad, size, pio_fis_i); |
| 1439 | |
| 1440 | if (is_atapi && !ad->done_first_drq) { |
| 1441 | /* already prepopulated iobuffer */ |
| 1442 | goto out; |
| 1443 | } |
| 1444 | |
| 1445 | if (ahci_dma_prepare_buf(dma, size) > 0) { |
| 1446 | has_sglist = 1; |
| 1447 | } |
| 1448 | |
| 1449 | trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", |
| 1450 | size, is_atapi ? "atapi" : "ata", |
| 1451 | has_sglist ? "" : "o"); |
| 1452 | |
| 1453 | if (has_sglist && size) { |
| 1454 | const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; |
| 1455 | |
| 1456 | if (is_write) { |
| 1457 | dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs); |
| 1458 | } else { |
| 1459 | dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs); |
| 1460 | } |
| 1461 | } |
| 1462 | |
| 1463 | /* Update number of transferred bytes, destroy sglist */ |
| 1464 | ide_dma_buf_commit(s, size); |
| 1465 | |
| 1466 | out: |
| 1467 | /* declare that we processed everything */ |
| 1468 | s->data_ptr = s->data_end; |
| 1469 | |
| 1470 | ad->done_first_drq = true; |
| 1471 | if (pio_fis_i) { |
| 1472 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); |
| 1473 | } |
| 1474 | |
| 1475 | return true; |
| 1476 | } |
| 1477 | |
| 1478 | static void ahci_start_dma(const IDEDMA *dma, IDEState *s, |
| 1479 | BlockCompletionFunc *dma_cb) |
| 1480 | { |
| 1481 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1482 | trace_ahci_start_dma(ad->hba, ad->port_no); |
| 1483 | s->io_buffer_offset = 0; |
| 1484 | dma_cb(s, 0); |
| 1485 | } |
| 1486 | |
| 1487 | static void ahci_restart_dma(const IDEDMA *dma) |
| 1488 | { |
| 1489 | /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ |
| 1490 | } |
| 1491 | |
| 1492 | /** |
| 1493 | * IDE/PIO restarts are handled by the core layer, but NCQ commands |
| 1494 | * need an extra kick from the AHCI HBA. |
| 1495 | */ |
| 1496 | static void ahci_restart(const IDEDMA *dma) |
| 1497 | { |
| 1498 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1499 | int i; |
| 1500 | |
| 1501 | for (i = 0; i < AHCI_MAX_CMDS; i++) { |
| 1502 | NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; |
| 1503 | if (ncq_tfs->halt) { |
| 1504 | execute_ncq_command(ncq_tfs); |
| 1505 | } |
| 1506 | } |
| 1507 | } |
| 1508 | |
| 1509 | /** |
| 1510 | * Called in DMA and PIO R/W chains to read the PRDT. |
| 1511 | * Not shared with NCQ pathways. |
| 1512 | */ |
| 1513 | static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) |
| 1514 | { |
| 1515 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1516 | IDEState *s = &ad->port.ifs[0]; |
| 1517 | |
| 1518 | if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, |
| 1519 | limit, s->io_buffer_offset) == -1) { |
| 1520 | trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); |
| 1521 | return -1; |
| 1522 | } |
| 1523 | s->io_buffer_size = s->sg.size; |
| 1524 | |
| 1525 | trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); |
| 1526 | return s->io_buffer_size; |
| 1527 | } |
| 1528 | |
| 1529 | /** |
| 1530 | * Updates the command header with a bytes-read value. |
| 1531 | * Called via ide_dma_buf_commit, for both DMA and PIO paths. |
| 1532 | * sglist destruction is handled within ide_dma_buf_commit. |
| 1533 | */ |
| 1534 | static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) |
| 1535 | { |
| 1536 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1537 | |
| 1538 | if (ad->cur_cmd == NULL) { |
| 1539 | return; |
| 1540 | } |
| 1541 | |
| 1542 | tx_bytes += le32_to_cpu(ad->cur_cmd->status); |
| 1543 | ad->cur_cmd->status = cpu_to_le32(tx_bytes); |
| 1544 | } |
| 1545 | |
| 1546 | static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) |
| 1547 | { |
| 1548 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1549 | IDEState *s = &ad->port.ifs[0]; |
| 1550 | uint8_t *p = s->io_buffer + s->io_buffer_index; |
| 1551 | int l = s->io_buffer_size - s->io_buffer_index; |
| 1552 | |
| 1553 | if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { |
| 1554 | return 0; |
| 1555 | } |
| 1556 | |
| 1557 | if (is_write) { |
| 1558 | dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); |
| 1559 | } else { |
| 1560 | dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); |
| 1561 | } |
| 1562 | |
| 1563 | /* free sglist, update byte count */ |
| 1564 | ide_dma_buf_commit(s, l); |
| 1565 | s->io_buffer_index += l; |
| 1566 | |
| 1567 | trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); |
| 1568 | return 1; |
| 1569 | } |
| 1570 | |
| 1571 | static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) |
| 1572 | { |
| 1573 | IDEState *ide_state = &ad->port.ifs[0]; |
| 1574 | |
| 1575 | if (!(ide_state->status & ERR_STAT) && |
| 1576 | !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { |
| 1577 | ad->port_regs.cmd_issue &= ~(1 << slot); |
| 1578 | } |
| 1579 | } |
| 1580 | |
| 1581 | /* Non-NCQ command is done - This function is never called for NCQ commands. */ |
| 1582 | static void ahci_cmd_done(const IDEDMA *dma) |
| 1583 | { |
| 1584 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); |
| 1585 | IDEState *ide_state = &ad->port.ifs[0]; |
| 1586 | |
| 1587 | trace_ahci_cmd_done(ad->hba, ad->port_no); |
| 1588 | |
| 1589 | /* no longer busy */ |
| 1590 | if (ad->busy_slot != -1) { |
| 1591 | ahci_clear_cmd_issue(ad, ad->busy_slot); |
| 1592 | ad->busy_slot = -1; |
| 1593 | } |
| 1594 | |
| 1595 | /* |
| 1596 | * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H |
| 1597 | * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise |
| 1598 | * an IRQ, we need to call them in reverse order. |
| 1599 | */ |
| 1600 | ahci_write_fis_d2h(ad, true); |
| 1601 | |
| 1602 | if (!(ide_state->status & ERR_STAT) && |
| 1603 | ad->port_regs.cmd_issue && !ad->check_bh) { |
| 1604 | ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, |
| 1605 | &ad->mem_reentrancy_guard); |
| 1606 | qemu_bh_schedule(ad->check_bh); |
| 1607 | } |
| 1608 | } |
| 1609 | |
| 1610 | static void ahci_irq_set(void *opaque, int n, int level) |
| 1611 | { |
| 1612 | qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); |
| 1613 | } |
| 1614 | |
| 1615 | static const IDEDMAOps ahci_dma_ops = { |
| 1616 | .start_dma = ahci_start_dma, |
| 1617 | .restart = ahci_restart, |
| 1618 | .restart_dma = ahci_restart_dma, |
| 1619 | .pio_transfer = ahci_pio_transfer, |
| 1620 | .prepare_buf = ahci_dma_prepare_buf, |
| 1621 | .commit_buf = ahci_commit_buf, |
| 1622 | .rw_buf = ahci_dma_rw_buf, |
| 1623 | .cmd_done = ahci_cmd_done, |
| 1624 | }; |
| 1625 | |
| 1626 | void ahci_init(AHCIState *s, DeviceState *qdev) |
| 1627 | { |
| 1628 | /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ |
| 1629 | memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, |
| 1630 | "ahci", AHCI_MEM_BAR_SIZE); |
| 1631 | memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, |
| 1632 | "ahci-idp", 32); |
| 1633 | } |
| 1634 | |
| 1635 | void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) |
| 1636 | { |
| 1637 | qemu_irq *irqs; |
| 1638 | int i; |
| 1639 | |
| 1640 | s->as = as; |
| 1641 | assert(s->ports > 0); |
| 1642 | s->dev = g_new0(AHCIDevice, s->ports); |
| 1643 | ahci_reg_init(s); |
| 1644 | irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); |
| 1645 | for (i = 0; i < s->ports; i++) { |
| 1646 | AHCIDevice *ad = &s->dev[i]; |
| 1647 | |
| 1648 | ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); |
| 1649 | ide_bus_init_output_irq(&ad->port, irqs[i]); |
| 1650 | |
| 1651 | ad->hba = s; |
| 1652 | ad->port_no = i; |
| 1653 | ad->port.dma = &ad->dma; |
| 1654 | ad->port.dma->ops = &ahci_dma_ops; |
| 1655 | ide_bus_register_restart_cb(&ad->port); |
| 1656 | } |
| 1657 | g_free(irqs); |
| 1658 | } |
| 1659 | |
| 1660 | void ahci_uninit(AHCIState *s) |
| 1661 | { |
| 1662 | int i, j; |
| 1663 | |
| 1664 | for (i = 0; i < s->ports; i++) { |
| 1665 | AHCIDevice *ad = &s->dev[i]; |
| 1666 | |
| 1667 | /* |
| 1668 | * Unplug does not go through a reset, so this is the only chance to |
| 1669 | * detach the requests and the bottom half that would otherwise walk |
| 1670 | * s->dev after it is freed below. |
| 1671 | */ |
| 1672 | ahci_cancel_ncq_requests(ad); |
| 1673 | if (ad->check_bh) { |
| 1674 | qemu_bh_delete(ad->check_bh); |
| 1675 | ad->check_bh = NULL; |
| 1676 | } |
| 1677 | |
| 1678 | for (j = 0; j < 2; j++) { |
| 1679 | IDEState *ide_state = &ad->port.ifs[j]; |
| 1680 | |
| 1681 | /* |
| 1682 | * Everything the port still owns points into the allocation this |
| 1683 | * function frees, io_buffer included, so nothing may be left in |
| 1684 | * flight once ide_exit() has run. |
| 1685 | */ |
| 1686 | if (ide_state->blk) { |
| 1687 | blk_drain(ide_state->blk); |
| 1688 | } |
| 1689 | ide_exit(ide_state); |
| 1690 | } |
| 1691 | object_unparent(OBJECT(&ad->port)); |
| 1692 | } |
| 1693 | |
| 1694 | g_free(s->dev); |
| 1695 | } |
| 1696 | |
| 1697 | void ahci_reset(AHCIState *s) |
| 1698 | { |
| 1699 | AHCIPortRegs *pr; |
| 1700 | int i; |
| 1701 | |
| 1702 | trace_ahci_reset(s); |
| 1703 | |
| 1704 | s->control_regs.irqstatus = 0; |
| 1705 | /* AHCI Enable (AE) |
| 1706 | * The implementation of this bit is dependent upon the value of the |
| 1707 | * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and |
| 1708 | * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be |
| 1709 | * read-only and shall have a reset value of '1'. |
| 1710 | * |
| 1711 | * We set HOST_CAP_AHCI so we must enable AHCI at reset. |
| 1712 | */ |
| 1713 | s->control_regs.ghc = HOST_CTL_AHCI_EN; |
| 1714 | |
| 1715 | for (i = 0; i < s->ports; i++) { |
| 1716 | pr = &s->dev[i].port_regs; |
| 1717 | pr->irq_stat = 0; |
| 1718 | pr->irq_mask = 0; |
| 1719 | pr->scr_ctl = 0; |
| 1720 | pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; |
| 1721 | ahci_reset_port(s, i, IDE_RESET_HARDWARE); |
| 1722 | } |
| 1723 | } |
| 1724 | |
| 1725 | static const VMStateDescription vmstate_ncq_tfs = { |
| 1726 | .name = "ncq state", |
| 1727 | .version_id = 1, |
| 1728 | .fields = (const VMStateField[]) { |
| 1729 | VMSTATE_UINT32(sector_count, NCQTransferState), |
| 1730 | VMSTATE_UINT64(lba, NCQTransferState), |
| 1731 | VMSTATE_UINT8(tag, NCQTransferState), |
| 1732 | VMSTATE_UINT8(cmd, NCQTransferState), |
| 1733 | VMSTATE_UINT8(slot, NCQTransferState), |
| 1734 | VMSTATE_BOOL(used, NCQTransferState), |
| 1735 | VMSTATE_BOOL(halt, NCQTransferState), |
| 1736 | VMSTATE_END_OF_LIST() |
| 1737 | }, |
| 1738 | }; |
| 1739 | |
| 1740 | static const VMStateDescription vmstate_ahci_device = { |
| 1741 | .name = "ahci port", |
| 1742 | .version_id = 1, |
| 1743 | .fields = (const VMStateField[]) { |
| 1744 | VMSTATE_IDE_BUS(port, AHCIDevice), |
| 1745 | VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), |
| 1746 | VMSTATE_UINT32(port_state, AHCIDevice), |
| 1747 | VMSTATE_UINT32(finished, AHCIDevice), |
| 1748 | VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), |
| 1749 | VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), |
| 1750 | VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), |
| 1751 | VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), |
| 1752 | VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), |
| 1753 | VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), |
| 1754 | VMSTATE_UINT32(port_regs.cmd, AHCIDevice), |
| 1755 | VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), |
| 1756 | VMSTATE_UINT32(port_regs.sig, AHCIDevice), |
| 1757 | VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), |
| 1758 | VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), |
| 1759 | VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), |
| 1760 | VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), |
| 1761 | VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), |
| 1762 | VMSTATE_BOOL(done_first_drq, AHCIDevice), |
| 1763 | VMSTATE_INT32(busy_slot, AHCIDevice), |
| 1764 | VMSTATE_BOOL(init_d2h_sent, AHCIDevice), |
| 1765 | VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, |
| 1766 | 1, vmstate_ncq_tfs, NCQTransferState), |
| 1767 | VMSTATE_END_OF_LIST() |
| 1768 | }, |
| 1769 | }; |
| 1770 | |
| 1771 | static int ahci_state_post_load(void *opaque, int version_id) |
| 1772 | { |
| 1773 | int i, j; |
| 1774 | struct AHCIDevice *ad; |
| 1775 | NCQTransferState *ncq_tfs; |
| 1776 | AHCIPortRegs *pr; |
| 1777 | AHCIState *s = opaque; |
| 1778 | |
| 1779 | for (i = 0; i < s->ports; i++) { |
| 1780 | ad = &s->dev[i]; |
| 1781 | pr = &ad->port_regs; |
| 1782 | |
| 1783 | if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { |
| 1784 | error_report("AHCI: DMA engine should be off, but status bit " |
| 1785 | "indicates it is still running."); |
| 1786 | return -1; |
| 1787 | } |
| 1788 | if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { |
| 1789 | error_report("AHCI: FIS RX engine should be off, but status bit " |
| 1790 | "indicates it is still running."); |
| 1791 | return -1; |
| 1792 | } |
| 1793 | |
| 1794 | /* After a migrate, the DMA/FIS engines are "off" and |
| 1795 | * need to be conditionally restarted */ |
| 1796 | pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); |
| 1797 | if (ahci_cond_start_engines(ad) != 0) { |
| 1798 | return -1; |
| 1799 | } |
| 1800 | |
| 1801 | for (j = 0; j < AHCI_MAX_CMDS; j++) { |
| 1802 | ncq_tfs = &ad->ncq_tfs[j]; |
| 1803 | ncq_tfs->drive = ad; |
| 1804 | |
| 1805 | if (ncq_tfs->used != ncq_tfs->halt) { |
| 1806 | return -1; |
| 1807 | } |
| 1808 | if (!ncq_tfs->halt) { |
| 1809 | continue; |
| 1810 | } |
| 1811 | if (!is_ncq(ncq_tfs->cmd)) { |
| 1812 | return -1; |
| 1813 | } |
| 1814 | if (ncq_tfs->slot != ncq_tfs->tag) { |
| 1815 | return -1; |
| 1816 | } |
| 1817 | /* If ncq_tfs->halt is justly set, the engine should be engaged, |
| 1818 | * and the command list buffer should be mapped. */ |
| 1819 | ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); |
| 1820 | if (!ncq_tfs->cmdh) { |
| 1821 | return -1; |
| 1822 | } |
| 1823 | ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, |
| 1824 | ncq_tfs->cmdh, |
| 1825 | ncq_tfs->sector_count * BDRV_SECTOR_SIZE, |
| 1826 | 0); |
| 1827 | if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { |
| 1828 | return -1; |
| 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | |
| 1833 | /* |
| 1834 | * If an error is present, ad->busy_slot will be valid and not -1. |
| 1835 | * In this case, an operation is waiting to resume and will re-check |
| 1836 | * for additional AHCI commands to execute upon completion. |
| 1837 | * |
| 1838 | * In the case where no error was present, busy_slot will be -1, |
| 1839 | * and we should check to see if there are additional commands waiting. |
| 1840 | */ |
| 1841 | if (ad->busy_slot == -1) { |
| 1842 | check_cmd(s, i); |
| 1843 | } else { |
| 1844 | /* We are in the middle of a command, and may need to access |
| 1845 | * the command header in guest memory again. */ |
| 1846 | if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { |
| 1847 | return -1; |
| 1848 | } |
| 1849 | ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); |
| 1850 | } |
| 1851 | } |
| 1852 | |
| 1853 | return 0; |
| 1854 | } |
| 1855 | |
| 1856 | const VMStateDescription vmstate_ahci = { |
| 1857 | .name = "ahci", |
| 1858 | .version_id = 1, |
| 1859 | .post_load = ahci_state_post_load, |
| 1860 | .fields = (const VMStateField[]) { |
| 1861 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports, |
| 1862 | vmstate_ahci_device, AHCIDevice), |
| 1863 | VMSTATE_UINT32(control_regs.cap, AHCIState), |
| 1864 | VMSTATE_UINT32(control_regs.ghc, AHCIState), |
| 1865 | VMSTATE_UINT32(control_regs.irqstatus, AHCIState), |
| 1866 | VMSTATE_UINT32(control_regs.impl, AHCIState), |
| 1867 | VMSTATE_UINT32(control_regs.version, AHCIState), |
| 1868 | VMSTATE_UINT32(idp_index, AHCIState), |
| 1869 | VMSTATE_UINT32_EQUAL(ports, AHCIState), |
| 1870 | VMSTATE_END_OF_LIST() |
| 1871 | }, |
| 1872 | }; |
| 1873 | |
| 1874 | void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) |
| 1875 | { |
| 1876 | int i; |
| 1877 | |
| 1878 | for (i = 0; i < ahci->ports; i++) { |
| 1879 | if (hd[i] == NULL) { |
| 1880 | continue; |
| 1881 | } |
| 1882 | ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); |
| 1883 | } |
| 1884 | } |