| 1 | /* |
| 2 | * QEMU ICH Emulation |
| 3 | * |
| 4 | * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> |
| 5 | * Copyright (c) 2010 Alexander Graf <agraf@suse.de> |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | * |
| 20 | * |
| 21 | * lspci dump of a ICH-9 real device |
| 22 | * |
| 23 | * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0]) |
| 24 | * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] |
| 25 | * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
| 26 | * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
| 27 | * Latency: 0 |
| 28 | * Interrupt: pin B routed to IRQ 222 |
| 29 | * Region 0: I/O ports at d000 [size=8] |
| 30 | * Region 1: I/O ports at cc00 [size=4] |
| 31 | * Region 2: I/O ports at c880 [size=8] |
| 32 | * Region 3: I/O ports at c800 [size=4] |
| 33 | * Region 4: I/O ports at c480 [size=32] |
| 34 | * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K] |
| 35 | * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+ |
| 36 | * Address: fee0f00c Data: 41d9 |
| 37 | * Capabilities: [70] Power Management version 3 |
| 38 | * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) |
| 39 | * Status: D0 PME-Enable- DSel=0 DScale=0 PME- |
| 40 | * Capabilities: [a8] SATA HBA <?> |
| 41 | * Capabilities: [b0] Vendor Specific Information <?> |
| 42 | * Kernel driver in use: ahci |
| 43 | * Kernel modules: ahci |
| 44 | * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 |
| 45 | * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 |
| 46 | * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 |
| 47 | * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 |
| 48 | * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 |
| 49 | * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 50 | * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 51 | * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 |
| 52 | * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 |
| 53 | * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00 |
| 54 | * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00 |
| 55 | * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 |
| 56 | * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 57 | * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 58 | * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 59 | * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 |
| 60 | * |
| 61 | */ |
| 62 | |
| 63 | #include "qemu/osdep.h" |
| 64 | #include "hw/pci/msi.h" |
| 65 | #include "hw/pci/pci.h" |
| 66 | #include "migration/vmstate.h" |
| 67 | #include "qemu/module.h" |
| 68 | #include "hw/isa/isa.h" |
| 69 | #include "system/dma.h" |
| 70 | #include "hw/ide/pci.h" |
| 71 | #include "hw/ide/ahci-pci.h" |
| 72 | #include "ahci-internal.h" |
| 73 | |
| 74 | #define ICH9_MSI_CAP_OFFSET 0x80 |
| 75 | #define ICH9_SATA_CAP_OFFSET 0xA8 |
| 76 | |
| 77 | #define ICH9_IDP_BAR 4 |
| 78 | #define ICH9_MEM_BAR 5 |
| 79 | |
| 80 | #define ICH9_IDP_INDEX 0x10 |
| 81 | #define ICH9_IDP_INDEX_LOG2 0x04 |
| 82 | |
| 83 | static const VMStateDescription vmstate_ich9_ahci = { |
| 84 | .name = "ich9_ahci", |
| 85 | .version_id = 1, |
| 86 | .fields = (const VMStateField[]) { |
| 87 | VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState), |
| 88 | VMSTATE_AHCI(ahci, AHCIPCIState), |
| 89 | VMSTATE_END_OF_LIST() |
| 90 | }, |
| 91 | }; |
| 92 | |
| 93 | static void pci_ich9_ahci_update_irq(void *opaque, int irq_num, int level) |
| 94 | { |
| 95 | PCIDevice *pci_dev = opaque; |
| 96 | |
| 97 | if (msi_enabled(pci_dev)) { |
| 98 | if (level) { |
| 99 | msi_notify(pci_dev, 0); |
| 100 | } |
| 101 | } else { |
| 102 | pci_set_irq(pci_dev, level); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | static void pci_ich9_reset(DeviceState *dev) |
| 107 | { |
| 108 | AHCIPCIState *d = ICH9_AHCI(dev); |
| 109 | |
| 110 | ahci_reset(&d->ahci); |
| 111 | } |
| 112 | |
| 113 | static void pci_ich9_ahci_init(Object *obj) |
| 114 | { |
| 115 | AHCIPCIState *d = ICH9_AHCI(obj); |
| 116 | |
| 117 | qemu_init_irq_child(obj, "update-irq", &d->irq, |
| 118 | pci_ich9_ahci_update_irq, d, 0); |
| 119 | ahci_init(&d->ahci, DEVICE(obj)); |
| 120 | d->ahci.irq = &d->irq; |
| 121 | } |
| 122 | |
| 123 | static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) |
| 124 | { |
| 125 | AHCIPCIState *d; |
| 126 | int sata_cap_offset; |
| 127 | uint8_t *sata_cap; |
| 128 | d = ICH9_AHCI(dev); |
| 129 | int ret; |
| 130 | |
| 131 | d->ahci.ports = 6; |
| 132 | ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev)); |
| 133 | |
| 134 | pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1); |
| 135 | |
| 136 | dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
| 137 | dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ |
| 138 | pci_config_set_interrupt_pin(dev->config, 1); |
| 139 | |
| 140 | /* XXX Software should program this register */ |
| 141 | dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ |
| 142 | |
| 143 | pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, |
| 144 | &d->ahci.idp); |
| 145 | pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 146 | &d->ahci.mem); |
| 147 | |
| 148 | sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA, |
| 149 | ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE, |
| 150 | errp); |
| 151 | if (sata_cap_offset < 0) { |
| 152 | return; |
| 153 | } |
| 154 | |
| 155 | sata_cap = dev->config + sata_cap_offset; |
| 156 | pci_set_word(sata_cap + SATA_CAP_REV, 0x10); |
| 157 | pci_set_long(sata_cap + SATA_CAP_BAR, |
| 158 | (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); |
| 159 | d->ahci.idp_offset = ICH9_IDP_INDEX; |
| 160 | |
| 161 | /* Although the AHCI 1.3 specification states that the first capability |
| 162 | * should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9 |
| 163 | * AHCI device puts the MSI capability first, pointing to 0x80. */ |
| 164 | ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL); |
| 165 | /* Any error other than -ENOTSUP(board's MSI support is broken) |
| 166 | * is a programming error. Fall back to INTx silently on -ENOTSUP */ |
| 167 | assert(!ret || ret == -ENOTSUP); |
| 168 | } |
| 169 | |
| 170 | static void pci_ich9_uninit(PCIDevice *dev) |
| 171 | { |
| 172 | AHCIPCIState *d; |
| 173 | d = ICH9_AHCI(dev); |
| 174 | |
| 175 | msi_uninit(dev); |
| 176 | ahci_uninit(&d->ahci); |
| 177 | } |
| 178 | |
| 179 | static void ich_ahci_class_init(ObjectClass *klass, const void *data) |
| 180 | { |
| 181 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 182 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 183 | |
| 184 | k->realize = pci_ich9_ahci_realize; |
| 185 | k->exit = pci_ich9_uninit; |
| 186 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 187 | k->device_id = PCI_DEVICE_ID_INTEL_82801IR; |
| 188 | k->revision = 0x02; |
| 189 | k->class_id = PCI_CLASS_STORAGE_SATA; |
| 190 | dc->vmsd = &vmstate_ich9_ahci; |
| 191 | device_class_set_legacy_reset(dc, pci_ich9_reset); |
| 192 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 193 | } |
| 194 | |
| 195 | static const TypeInfo ich_ahci_info = { |
| 196 | .name = TYPE_ICH9_AHCI, |
| 197 | .parent = TYPE_PCI_DEVICE, |
| 198 | .instance_size = sizeof(AHCIPCIState), |
| 199 | .instance_init = pci_ich9_ahci_init, |
| 200 | .class_init = ich_ahci_class_init, |
| 201 | .interfaces = (const InterfaceInfo[]) { |
| 202 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 203 | { }, |
| 204 | }, |
| 205 | }; |
| 206 | |
| 207 | static void ich_ahci_register_types(void) |
| 208 | { |
| 209 | type_register_static(&ich_ahci_info); |
| 210 | } |
| 211 | |
| 212 | type_init(ich_ahci_register_types) |